; -------------------------------------------------------------------------------- ; @Title: FM3 On-Chip Peripherals ; @Props: Released ; @Author: KAR, SLA, STR, ZAN, ASK, LSD, SEB ; @Changelog: 2011-05-24 ; 2016-03-09 ASK ; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation ; @Doc: FCR4-Cluster-MN707-00001-0v16-E.pdf ; peripherals_MN706-00002-5v0-E.pdf ; peripherals_communication_MN706-00024-1v0-E.pdf ; peripherals_analog_MN706-00023-1v0-E.pdf ; peripherals_timer_MN706-00022-1v0-E.pdf ; reference_manual_MN706-00002-7v0-E.pdf ; roduct_selector_guide_ad709-00001.pdf ; @Core: Cortex-M3 ; @Chip: MB9AF102N MB9AF102R MB9AF104N MB9AF104R MB9AF105NA MB9AF105RA MB9AF111K MB9AF112K MB9AF315M MB9AF315N MB9AF316M MB9AF316N ; MB9BF104N MB9BF104R MB9BF105N MB9BF105R MB9AF311K MB9AF312K MB9AF111L MB9AF111M MB9AF141L MB9AF141M MB9AF141N MB9AF142L ; MB9BF106N MB9BF106R MB9BF304N MB9BF304R MB9AF111N MB9AF112L MB9AF112M MB9AF112N MB9AF142M MB9AF142N MB9AF144L MB9AF144M ; MB9BF305N MB9BF305R MB9BF306N MB9BF306R MB9AF114L MB9AF114M MB9AF114N MB9AF115M MB9AF144N MB9AF341L MB9AF341M MB9AF341N ; MB9BF404N MB9BF404R MB9BF405N MB9BF405R MB9AF115N MB9AF116M MB9AF116N MB9AF311L MB9AF342L MB9AF342M MB9AF342N MB9AF344L ; MB9BF406N MB9BF406R MB9BF504N MB9BF504R MB9AF311M MB9AF311N MB9AF312L MB9AF312M MB9AF344M MB9AF344N MB9AFA41L MB9AFA41M ; MB9BF505N MB9BF505R MB9BF506N MB9BF506R MB9AF312N MB9AF314L MB9AF314M MB9AF314N MB9AFA41N MB9AFA42L MB9AFA42M MB9AFA42N ; MB9AFA44L MB9AFA44M MB9AFA44N MB9AFB41L MB9AFB41M MB9AFB41N MB9AFB42L MB9AFB42M MB9AFB42N MB9AFB44M MB9AFB44N MB9BFD17T ; MB9AFB44L MB9AF131L MB9AF132K MB9AF132L MB9AF131N MB9AF131M MB9AF132N MB9AF132M MB9AFA31L MB9AFA31M MB9AFA31N MB9AFA32L ; MB9AFA32M MB9AFA32N MB9BF112N MB9BF112R MB9BF114N MB9BF114R MB9BF115N MB9BF115R MB9BF116N MB9BF116R MB9BF116S MB9BF116T ; MB9BF117S MB9BF117T MB9BF118S MB9BF118T MB9BF216S MB9BF216T MB9BF217S MB9BF217T MB9BF218S MB9BF218T MB9BF312N MB9BF312R ; MB9BF314N MB9BF314R MB9BF315N MB9BF315R MB9BF316N MB9BF316R MB9BF316S MB9BF316T MB9BF317S MB9BF317T MB9BF318S MB9BF318T ; MB9BF412N MB9BF412R MB9BF414N MB9BF414R MB9BF415N MB9BF415R MB9BF416N MB9BF416R MB9BF416S MB9BF416T MB9BF417S MB9BF417T ; MB9BF418S MB9BF418T MB9BF512N MB9BF512R MB9BF514N MB9BF514R MB9BF515N MB9BF515R MB9BF516N MB9BF516R MB9BF516S MB9BF516T ; MB9BF517S MB9BF517T MB9BF518S MB9BF518T MB9BF616S MB9BF616T MB9BF617S MB9BF617T MB9BF618S MB9BF618T MB9BF128T MB9BF129S ; MB9AF121K MB9AF121L MB9AF131K MB9AF154M MB9AF154N MB9AF154R MB9AF155M MB9AF155R MB9AF156M MB9AF156N MB9AF156R MB9AF1A1L ; MB9AF1A1M MB9AF1A1N MB9AF1A2L MB9AF1A2M MB9AF1A2N MB9AF421K MB9AF421L MB9AFAA1L MB9AFAA1M MB9AFAA1N MB9AFAA2L MB9AFAA2M ; MB9AFAA2N MB9BF102N MB9BF102R MB9BF121J MB9BF121K MB9BF121L MB9BF121M MB9BF122K MB9BF122L MB9BF122M MB9BF124K MB9BF124L ; MB9BF124M MB9BF129T MB9BF321K MB9BF321L MB9BF321M MB9BF322K MB9BF322L MB9BF322M MB9BF324K MB9BF324L MB9BF324M MB9BF328S ; MB9BF328T MB9BF329S MB9BF329T MB9BF428S MB9BF428T MB9BF429S MB9BF429T MB9BF521K MB9BF521L MB9BF521M MB9BF522K MB9BF522L ; MB9BF522M MB9BF524K MB9BF524L MB9BF524M MB9BF528S MB9BF528T MB9BF529S MB9BF529T MB9BFD16S MB9BFD16T MB9BF128S MB9BFD17S ; MB9BFD18T MB9BFD18S ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perfm3.per 17736 2024-04-08 09:26:07Z kwisniewski $ ; Known problems ; No definition of USB Clock's UPCR4 & UPCR5 registers for TYPE2 products. ; No information about which channels of Multi-functional Serial Interface are available for MB9AF132K. ; Ethernet: FCR.DZPQ and FCR.PLT described as 'reserved'. ; TYPE12 Multi-function Serial Interface (MFSI) description - "max. 16 channels, 4 channels with FIFO" - not specified WHICH channels have FIFO. ch.0/1/2/3? tree.close "Core Registers (Cortex-M3)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 11. group 0x10--0x1b line.long 0x00 "SYST_CSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,Clock Source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "Not SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" ;group 0x14++0x03 line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" ;group 0x18++0x03 line.long 0x08 "SYST_CVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current Value" rgroup 0x1c++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" textline " " rgroup 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Implementation Defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " CONSTANT ,Constant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Number of Processor" bitfld.long 0x00 0.--3. " REVISION ,Implementation Defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group 0xd04--0xd17 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Not set,Set" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not set,Set" bitfld.long 0x00 27. " PENDSVCLR ,Clear Pending pendSV Bit" "Not cleared,Cleared" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not set,Set" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "Not cleared,Cleared" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Interrupt Pending Flag" "Not pending,Pending" hexmask.long.word 0x00 12.--21. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,Active ISR Number Field" ;group 0xd08++0x03 line.long 0x04 "VTOR,Vector Table Offset Register" bitfld.long 0x04 29. " TBLBASE ,Table Base" "Code,RAM" hexmask.long.tbyte 0x04 7.--28. 1. " TBLOFF ,Vector Table Base Offset Field" ;group 0xd0c++0x03 line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "Not cleared,Cleared all" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No reset,Reset" ;group 0xd10++0x03 line.long 0x0c "SCR,System Control Register" bitfld.long 0x0c 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0c 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x0c 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" ;group 0xd14++0x03 line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte,8-byte" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI, Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " USERSETMPEND ,Enable User Access to the Software Trigger Exception Register" "Disabled,Enabled" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" group 0xd18--0xd23 line.long 0x00 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x00 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x00 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x00 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x04 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x04 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x04 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x04 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x04 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x08 "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x08 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x08 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x08 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x08 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" group 0xd24++0x3 line.long 0x00 "SHCSR,System Handler Control and State Register" bitfld.long 0x00 18. " USGFAULTENA ,USGFAULTENA" "Disabled,Enabled" bitfld.long 0x00 17. " BUSFAULTENA ,BUSFAULTENA" "Disabled,Enabled" bitfld.long 0x00 16. " MEMFAULTENA ,MEMFAULTENA" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SVCALLPENDED ,SVCall is Pended Started" "Not replaced,Replaced" bitfld.long 0x00 14. " BUSFAULTPENDED ,BusFault is Pended Started" "Not replaced,Replaced" bitfld.long 0x00 13. " MEMFAULTPENDED ,MemManage is Pended Started" "Not replaced,Replaced" textline " " bitfld.long 0x00 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x00 10. " PENDSVACT ,PendSV is Active" "Not active,Active" bitfld.long 0x00 8. " MONITORACT ,Monitor is Active" "Not active,Active" textline " " bitfld.long 0x00 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x00 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" bitfld.long 0x00 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" textline " " bitfld.long 0x00 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group 0xd28--0xd3b line.byte 0x0 "MMFSR,Memory Manage Fault Status Register" bitfld.byte 0x0 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x0 4. " MSTKERR ,Stacking Access Violations" "No error,Error" bitfld.byte 0x0 3. " MUNSTKERR ,Unstack Access Violations" "No error,Error" textline " " bitfld.byte 0x0 1. " DACCVIOL ,Data Access Violation" "No error,Error" bitfld.byte 0x0 0. " IACCVIOL ,Instruction Access Violation" "No error,Error" ;group 0xd29++0x00 line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid" "Not valid,Valid" bitfld.byte 0x01 4. " STKERR ,Stacking from Exception has Caused Bus Faults" "No error,Error" bitfld.byte 0x01 3. " UNSTKERR ,Unstack from Exception Return has Caused Bus Faults" "No error,Error" textline " " bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise Data Bus Error" "No error,Error" bitfld.byte 0x01 1. " PRECISERR ,Precise Data Bus Error Return" "No error,Error" bitfld.byte 0x01 0. " IBUSERR ,Instruction Bus Error Flag" "No error,Error" ;group 0xd2a++0x01 line.word 0x02 "USAFAULT,Usage Fault Status Register" bitfld.word 0x02 9. " DIVBYZERO ,Illegal PC Load" "No error,Error" bitfld.word 0x02 8. " UNALIGNED ,Illegal Unaligned Access" "No error,Error" bitfld.word 0x02 3. " NOCP ,Attempt to use a coprocessor instruction" "No error,Error" textline " " bitfld.word 0x02 2. " INVPC ,Attempt to Load EXC_RETURN into PC Illegally" "No error,Error" bitfld.word 0x02 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x02 0. " UNDEFINSTR ,Illegal Processor State" "No error,Error" ;group 0xd2c++0x03 line.long 0x04 "HFSR,Hard Fault Status Register" bitfld.long 0x04 31. " DEBUGEVT ,This Bit is Set if There is a Fault Related to Debug" "No error,Error" bitfld.long 0x04 30. " FORCED ,Hard Fault Activated" "No error,Error" bitfld.long 0x04 1. " VECTTBL ,Bus Fault" "No error,Error" ;group 0xd30++0x03 line.long 0x08 "DFSR,Debug Fault Status Register" bitfld.long 0x08 4. " EXTERNAL ,External Debug Request Flag" "Not asserted,Asserted" bitfld.long 0x08 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x08 2. " DWTTRAP ,Data Watchpoint and Trace (DWT) Flag" "Not matched,Matched" textline " " bitfld.long 0x08 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x08 0. " HALTED ,Halt Request Flag" "Not requested,Requested" ;group 0xd34++0x03 line.long 0xc "MMFAR,Memory Manage Fault Address Register" ;group 0xd38++0x03 line.long 0x10 "BFAR,Bus Fault Address Register" wgroup 0xf00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" tree "Feature Registers" width 10. rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end tree "CoreSight Identification Registers" width 6. rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20000) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x20001) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 5. " C_SNAPSTALL ,Halting debug to gain control of the core" "Disabled,Enabled" bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step" bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x0) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x20001)==0x00001) group 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core running and Lockup/Debug Key" "Not running,Running" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core is sleeping/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register Read/Write on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 2. " C_STEP ,Core Step" "No step,Step" bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" textline " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif wgroup 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,xPSR/ Flags,MSP,PSP,RAZ/WI,CONTROL/FAULTMASK/BASEPRI/PRIMASK,?..." group 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" textline " " bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" textline " " bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group 0x00--0x27 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 8.--11. " NUM_LIT ,Number of Literal Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " NUM_CODE ,Number of Code Slots Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" ;group 0x04++0x03 line.long 0x04 "FP_REMAP,Flash Patch Remap Register" hexmask.long.tbyte 0x04 5.--28. 1. " REMAP ,Remap Base Address Field" ;group 0x08++0x03 line.long 0x8 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x8 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x8 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x8 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0xC "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0xC 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0xC 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0xC 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x10 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x10 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x10 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x10 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x14 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x14 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x14 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x14 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x18 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x18 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x18 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x18 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x1C "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x1C 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x1C 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x1C 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x20 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x20 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x20 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x20 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" line.long 0x24 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x24 30.--31. " REPLACE ,REPLACE" "Remap to remap address,Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x24 2.--28. 1. " COMP ,Comparison Address" bitfld.long 0x24 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" tree "Coresight Management Registers" rgroup 0xfd0--0xfff line.long 0x00 "PID4,Peripheral ID4" line.long 0x04 "PID5,Peripheral ID5" line.long 0x08 "PID6,Peripheral ID6" line.long 0x0c "PID7,Peripheral ID7" line.long 0x10 "PID0,Peripheral ID0" line.long 0x14 "PID1,Peripheral ID1" line.long 0x18 "PID2,Peripheral ID2" line.long 0x1c "PID3,Peripheral ID3" line.long 0x20 "CID0,Component ID0" line.long 0x24 "CID1,Component ID1" line.long 0x28 "CID2,Component ID2" line.long 0x2c "CID3,Component ID3" tree.end else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group 0x00--0x1B line.long 0x00 "DWT_CTRL,DWT Control Register" bitfld.long 0x00 28.--31. " NUMCOMP ,Number of Comparators Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22. " CYCEVTENA ,Enables Cycle Count Event" "Disabled,Enabled" bitfld.long 0x00 21. " FOLDEVTENA ,Enables Folded Instruction Count Event" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " LSUEVTENA ,Enables LSU Count Event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables Sleep Count Event" "Disabled,Enabled" bitfld.long 0x00 18. " EXCEVTENA ,Enables Interrupt Overhead Event" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CPIEVTENA ,Enables CPI Count Event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables Interrupt Event Tracing" "Disabled,Enabled" bitfld.long 0x00 12. " PCSAMPLEENA ,Enables PC Sampling Event" "Disabled,Enabled" textline " " bitfld.long 0x00 10.--11. " SYNCTAP ,Feed Synchronization Pulse to the ITM SYNCEN Control" "Disabled,24,26,28" bitfld.long 0x00 9. " CYCTAP ,Selects a Tap on the DWT_CYCCNT Register" "Bit 6,Bit 10" bitfld.long 0x00 5.--8. " POSTCNT ,Post-Scalar Counter for CYCTAP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1.--4. " POSTPRESET ,Reload Value for POSTCNT Post-Scalar Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enable the DWT_CYCCNT Counter" "Disabled,Enabled" ;group 0x04++0x03 line.long 0x04 "DWT_CYCCNT,Cycle Count register" ;group 0x08++0x03 line.long 0x08 "DWT_CPICNT,DWT CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" ;group 0x0c++0x03 line.long 0x0c "DWT_EXCCNT,DWT Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" ;group 0x10++0x03 line.long 0x10 "DWT_SLEEPCNT,DWT Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" ;group 0x14++0x03 line.long 0x14 "DWT_LSUCNT,DWT LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" ;group 0x18++0x03 line.long 0x18 "DWT_FOLDCNT,DWT Fold Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" group.long 0x20++0x03 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" group.long 0x30++0x03 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" group.long 0x40++0x03 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" group.long 0x50++0x03 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" group.long 0x24++0x03 line.long 0x00 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x03 line.long 0x00 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44++0x03 line.long 0x00 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x54++0x03 line.long 0x00 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x00 0.--3. " MASK ,Mask on Data Address when Matching Against COMP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x20)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x38))&0x20)==0x00) group.long 0x38++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x38++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x48))&0x20)==0x00) group.long 0x48++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x48++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x58))&0x20)==0x00) group.long 0x58++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Sample and emit PC through ITM,Emit data through ITM,Sample PC and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." else group.long 0x58++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "byte,half,word,res" bitfld.long 0x00 9. " LNK1ENA ,DATAVADDR1 support" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Comparator Compares Against the PC Sampler Counter" "Cleared,Set" bitfld.long 0x00 5. " EMITRANGE ,Emit Range Field" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " FUNCTION ,FUNCTION settings" "Disabled,Emit address offset through ITM,Emit data and address offset through ITM,Emit address offset and data value through ITM,Watchpoint on PC match,Watchpoint on read,Watchpoint on write,Watchpoint on read or write,ETM trigger on PC match,ETM trigger on read,ETM trigger on write,ETM trigger on read or write,?..." endif tree "Coresight Management Registers" rgroup 0xfd0--0xfff line.long 0x00 "PID4,Peripheral ID4" line.long 0x04 "PID5,Peripheral ID5" line.long 0x08 "PID6,Peripheral ID6" line.long 0x0c "PID7,Peripheral ID7" line.long 0x10 "PID0,Peripheral ID1" line.long 0x14 "PID1,Peripheral ID2" line.long 0x18 "PID2,Peripheral ID3" line.long 0x1c "PID3,Peripheral ID4" line.long 0x20 "CID0,Component ID0" line.long 0x24 "CID1,Component ID1" line.long 0x28 "CID2,Component ID2" line.long 0x2c "CID3,Component ID3" tree.end else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end config 16. 8. tree "Flash IF" base ad:0x40000000 width 8. sif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) group.long 0x00++0x03 line.long 0x00 "FASZR,Flash Access Size Register" bitfld.long 0x00 0.--1. " ASZ ,Flash Access Size Register" ",16-bit read/write,32-bit read,?..." endif sif (!cpuis("MB9AF13?K")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AFA3?L")&&!cpuis("MB9AFA3?M")&&!cpuis("MB9AFA3?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")&&!cpuis("MB9AFAA?N")) group.long 0x04++0x03 line.long 0x00 "FRWTR,Flash Read Wait Register" sif (cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF15*")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,Pre-fetch,?..." elif (cpuis("MB9BF524*")||cpuis("MB9BF522*")||cpuis("MB9BF521*")||cpuis("MB9BF324*")||cpuis("MB9BF322*")||cpuis("MB9BF321*")||cpuis("MB9BF124*")||cpuis("MB9BF122*")||cpuis("MB9BF121K")||cpuis("MB9BF121L")||cpuis("MB9BF121M")||cpuis("MB9BF122K")||cpuis("MB9BF122L")||cpuis("MB9BF122M")||cpuis("MB9BF124K")||cpuis("MB9BF124L")||cpuis("MB9BF124M")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,Pre-fetch (HCLK < 40MHz),Pre-fetch (HCLK > 40MHz),?..." textline " " elif (cpuis("MB9BF121J")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,0 to 1 cycles,Pre-fetch,?..." elif (cpuis("MB9BF529*")||cpuis("MB9BF528*")||cpuis("MB9BF429*")||cpuis("MB9BF428*")||cpuis("MB9BF329*")||cpuis("MB9BF328*")||cpuis("MB9BF129*")||cpuis("MB9BF128*")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,,Pre-fetch,?..." elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,,Acceleration,?..." elif (cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,?..." elif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,,2 cycles,?..." else bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,0 to 1 cycles,?..." endif endif sif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")||cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF15*")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")||cpuis("MB9BF524*")||cpuis("MB9BF522*")||cpuis("MB9BF521*")||cpuis("MB9BF324*")||cpuis("MB9BF322*")||cpuis("MB9BF321*")||cpuis("MB9BF124*")||cpuis("MB9BF122*")||cpuis("MB9BF121*")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")||cpuis("MB9AF121*")||cpuis("MB9AF421*")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF529*")||cpuis("MB9BF528*")||cpuis("MB9BF429*")||cpuis("MB9BF428*")||cpuis("MB9BF329*")||cpuis("MB9BF328*")||cpuis("MB9BF129*")||cpuis("MB9BF128*")) rgroup.long 0x08++0x03 else group.long 0x08++0x03 endif line.long 0x00 "FSTR,Flash Status Register" sif (cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")) bitfld.long 0x00 2. " CERS ,Flash Chip Erase Error" "Not occurred,Occurred" rbitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" rbitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" elif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) bitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" bitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" else bitfld.long 0x00 5. " PGMS ,Flash Program Status" "Not written,Written" bitfld.long 0x00 4. " SERS ,Flash Sector Erase Status" "Not erased,Erased" bitfld.long 0x00 3. " ESPS ,Flash Erase Suspend Status" "Not suspended,Suspended" textline " " bitfld.long 0x00 2. " CERS ,Flash Chip Erase Error" "Not occurred,Occurred" bitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" bitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" endif sif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) group.long 0x10++0x03 line.long 0x00 "FSYNDN,Flash Sync Down Register" bitfld.long 0x00 0.--2. " SD ,Number of wait set" "+0,+1,,+3,,+5,,+7" endif sif (cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")) group.long 0x14++0x03 line.long 0x00 "FBFCR,Flash Buffer Control Register" rbitfld.long 0x00 1. " BS ,Buffer Status" "Stopped/Initializing,Allowed" bitfld.long 0x00 0. " BE ,Buffer Enable" "Disabled,Enabled" endif sif (!cpuis("MB9AF10*")&&!cpuis("MB9BF30*")&&!cpuis("MB9BF10*")&&!cpuis("MB9BF40*")&&!cpuis("MB9BF50*")&&!cpuis("MB9BFD1?S")&&!cpuis("MB9BFD1?T")&&!cpuis("MB9AF31?L")&&!cpuis("MB9AF31?M")&&!cpuis("MB9AF31?N")&&!cpuis("MB9AF11?L")&&!cpuis("MB9AF11?M")&&!cpuis("MB9AF11?N")&&!cpuis("MB9AF111K")&&!cpuis("MB9AF112K")&&!cpuis("MB9AF311K")&&!cpuis("MB9AF312K")&&!cpuis("MB9AF13?K")&&!cpuis("MB9AF13?L")&&!cpuis("MB9BF51?S")&&!cpuis("MB9BF51?T")&&!cpuis("MB9BF41?S")&&!cpuis("MB9BF41?T")&&!cpuis("MB9BF61?S")&&!cpuis("MB9BF61?T")&&!cpuis("MB9BF31?S")&&!cpuis("MB9BF31?T")&&!cpuis("MB9BF21?S")&&!cpuis("MB9BF21?T")&&!cpuis("MB9BF11?S")&&!cpuis("MB9BF11?T")&&!cpuis("MB9BF51?N")&&!cpuis("MB9BF51?R")&&!cpuis("MB9BF41?N")&&!cpuis("MB9BF41?R")&&!cpuis("MB9BF31?N")&&!cpuis("MB9BF31?R")&&!cpuis("MB9BF11?N")&&!cpuis("MB9BF11?R")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AFA3?L")&&!cpuis("MB9AFA3?M")&&!cpuis("MB9AFA3?N")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")&&!cpuis("MB9AFAA?N")) group.long 0x20++0x07 line.long 0x00 "FICR,Flash Interrupt Control Register" bitfld.long 0x00 1. " HANGIE ,HANG Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " RDYIE ,RDY Interrupt Enable" "Disabled,Enabled" line.long 0x04 "FISR,Flash Interrupt Status Register" bitfld.long 0x04 1. " HANGIF ,HANG Interrupt Flag" "No interrupt,Interrupt" bitfld.long 0x04 0. " RDYIF ,RDY Interrupt Flag" "No interrupt,Interrupt" wgroup.long 0x28++0x03 line.long 0x00 "FICLR,Flash Interrupt Clear Register" bitfld.long 0x00 1. " HANGC ,HANG Interrupt Clear" "No effect,Clear" bitfld.long 0x00 0. " RDYC ,RDY Interrupt Clear" "No effect,Clear" sif (cpuis("MB9BF129*")||cpuis("MB9BF128*")) rgroup.long 0x88++0x03 line.long 0x00 "FSTR1,Flash Status Register" bitfld.long 0x00 5. " PGMS ,Flash Program Status" "Not written,Written" bitfld.long 0x00 4. " SERS ,Flash Sector Erase Status" "Not erased,Erased" bitfld.long 0x00 3. " ESPS ,Flash Erase Suspend Status" "Not suspended,Suspended" textline " " bitfld.long 0x00 2. " CERS ,Flash Chip Erase Error" "Not occurred,Occurred" bitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" bitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" endif endif rgroup.long 0x100++0x03 line.long 0x00 "CRTRMM,CR Trimming Data Mirror Register" sif (cpuis("MB9BF121*")||cpuis("MB9BF122*")||cpuis("MB9BF124*")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")||cpuis("MB9BF521?")||cpuis("MB9BF522?")||cpuis("MB9BF524?")||cpuis("MB9AF121K")||cpuis("MB9AF121L")||cpuis("MB9AF121*")||cpuis("MB9AF421*")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF529*")||cpuis("MB9BF528*")||cpuis("MB9BF429*")||cpuis("MB9BF428*")||cpuis("MB9BF329*")||cpuis("MB9BF328*")||cpuis("MB9BF129*")||cpuis("MB9BF128*")) bitfld.long 0x00 16.--20. 1. " TTRMM ,CR Temperature Trimming Data Mirror Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--9. 1. " TRMM ,CR Trimming Data Mirror Bits" else hexmask.long.word 0x00 0.--9. 1. " TRMM ,CR trimming data" endif width 0xb tree.end tree "WorkFlash IF" base ad:0x200E0000 width 7. sif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) group.long 0x00++0x03 line.long 0x00 "FASZR,Flash Access Size Register" bitfld.long 0x00 0.--1. " ASZ ,Flash Access Size Register" ",16-bit read/write,32-bit read,?..." endif sif (!cpuis("MB9AF13?K")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AFA3?L")&&!cpuis("MB9AFA3?M")&&!cpuis("MB9AFA3?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")&&!cpuis("MB9AFAA?N")) group.long 0x04++0x03 line.long 0x00 "FRWTR,Flash Read Wait Register" sif (cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF15*")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,Pre-fetch,?..." elif (cpuis("MB9BF524*")||cpuis("MB9BF522*")||cpuis("MB9BF521*")||cpuis("MB9BF324*")||cpuis("MB9BF322*")||cpuis("MB9BF321*")||cpuis("MB9BF124*")||cpuis("MB9BF122*")||cpuis("MB9BF121K")||cpuis("MB9BF121L")||cpuis("MB9BF121M")||cpuis("MB9BF122K")||cpuis("MB9BF122L")||cpuis("MB9BF122M")||cpuis("MB9BF124K")||cpuis("MB9BF124L")||cpuis("MB9BF124M")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,Pre-fetch (HCLK < 40MHz),Pre-fetch (HCLK > 40MHz),?..." textline " " elif (cpuis("MB9BF121J")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,0 to 1 cycles,Pre-fetch,?..." elif (cpuis("MB9BF529*")||cpuis("MB9BF528*")||cpuis("MB9BF429*")||cpuis("MB9BF428*")||cpuis("MB9BF329*")||cpuis("MB9BF328*")||cpuis("MB9BF129*")||cpuis("MB9BF128*")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,,Pre-fetch,?..." elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,,Acceleration,?..." elif (cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,?..." elif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")) bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,,2 cycles,?..." else bitfld.long 0x00 0.--1. " RWT ,Read Wait Cycle" "0 cycle,0 to 1 cycles,?..." endif endif sif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")||cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF15*")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")||cpuis("MB9BF524*")||cpuis("MB9BF522*")||cpuis("MB9BF521*")||cpuis("MB9BF324*")||cpuis("MB9BF322*")||cpuis("MB9BF321*")||cpuis("MB9BF124*")||cpuis("MB9BF122*")||cpuis("MB9BF121*")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")||cpuis("MB9AF121*")||cpuis("MB9AF421*")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF529*")||cpuis("MB9BF528*")||cpuis("MB9BF429*")||cpuis("MB9BF428*")||cpuis("MB9BF329*")||cpuis("MB9BF328*")||cpuis("MB9BF129*")||cpuis("MB9BF128*")) rgroup.long 0x08++0x03 else group.long 0x08++0x03 endif line.long 0x00 "FSTR,Flash Status Register" sif (cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")) bitfld.long 0x00 2. " CERS ,Flash Chip Erase Error" "Not occurred,Occurred" rbitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" rbitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" elif (cpuis("MB9AF10*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?L")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) bitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" bitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" else bitfld.long 0x00 5. " PGMS ,Flash Program Status" "Not written,Written" bitfld.long 0x00 4. " SERS ,Flash Sector Erase Status" "Not erased,Erased" bitfld.long 0x00 3. " ESPS ,Flash Erase Suspend Status" "Not suspended,Suspended" textline " " bitfld.long 0x00 2. " CERS ,Flash Chip Erase Error" "Not occurred,Occurred" bitfld.long 0x00 1. " HNG ,Flash Hang" "Not detected,Detected" bitfld.long 0x00 0. " RDY ,Flash Ready Status" "In progress,Finished" endif width 0xb tree.end tree "Clock and Reset Control" base ad:0x40010000 width 11. group.long 0x00++0x03 line.byte 0x00 "SCM_CTL,System Clock Mode Control Register" bitfld.byte 0x00 5.--7. " RCS ,Master clock switch control bits" "Hi-speed CR,Main,PLL,,Low-speed CR,Sub,?..." bitfld.byte 0x00 4. " PLLE ,PLL oscillation enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " SOSCE ,Sub clock oscillation enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " MOSCE ,Main clock oscillation enable bit" "Disabled,Enabled" rgroup.long 0x04++0x03 line.byte 0x00 "SCM_STR,System Clock Mode Status Register" bitfld.byte 0x00 5.--7. " RCM[2:0] ,Master clock selection bits" "Hi-speed CR,Main,PLL,,Low-speed CR,Sub,?..." bitfld.byte 0x00 4. " PLRDY ,PLL oscillation stable bit" "Not stable/Stopped,Stable" textline " " bitfld.byte 0x00 3. " SORDY ,Sub clock oscillation stable bit" "Not stable/Stopped,Stable" textline " " bitfld.byte 0x00 1. " MORDY ,Main clock oscillation stable bit" "Not stable/Stopped,Stable" if ((((d.l(ad:0x40010000+0x08))&0x04)==0x00)&&(((d.l(ad:0x40035800))&0x01)==0x00)) group.long 0x08++0x03 line.long 0x00 "STB_CTL,Standby Mode Control Register" hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bit" bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Hold,Set" bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby" textline " " bitfld.long 0x00 0.--1. " STM ,Standby mode selection bit" "Timer,,Stop,?..." elif ((((d.l(ad:0x40010000+0x08))&0x04)==0x00)&&(((d.l(ad:0x40035800))&0x01)==0x01)) group.long 0x08++0x03 line.long 0x00 "STB_CTL,Standby Mode Control Register" hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bit" bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Hold,Set" bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby" textline " " bitfld.long 0x00 0.--1. " STM ,Standby mode selection bit" "Timer,,RTC,?..." elif ((((d.l(ad:0x40010000+0x08))&0x04)==0x04)&&(((d.l(ad:0x40035800))&0x01)==0x00)) group.long 0x08++0x03 line.long 0x00 "STB_CTL,Standby Mode Control Register" hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bit" bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Hold,Set" bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby" textline " " bitfld.long 0x00 0.--1. " STM ,Standby mode selection bit" "Timer,,Deep standby stop,?..." else group.long 0x08++0x03 line.long 0x00 "STB_CTL,Standby Mode Control Register" hexmask.long.word 0x00 16.--31. 1. " KEY ,Standby mode control write control bit" bitfld.long 0x00 4. " SPL ,Standby pin level setting bit" "Hold,Set" bitfld.long 0x00 2. " DSTM ,Deep standby mode select bit" "Standby,Deep standby" textline " " bitfld.long 0x00 0.--1. " STM ,Standby mode selection bit" "Timer,,Deep standby RTC,?..." endif rgroup.long 0x0C++0x03 line.word 0x00 "RST_STR,Reset cause register" bitfld.word 0x00 8. " SRST ,Software reset flag" "No reset,Reset" bitfld.word 0x00 7. " FCSR ,Flag for anomalous frequency detection reset" "No reset,Reset" bitfld.word 0x00 6. " CSVR ,Clock failure detection reset flag" "No reset,Reset" textline " " bitfld.word 0x00 5. " HWDT ,Hardware watchdog reset flag" "No reset,Reset" bitfld.word 0x00 4. " SWDT ,Software watchdog reset flag" "No reset,Reset" sif (cpuis("MB9AF13??")||cpuis("MB9AFA3??")||cpuis("MB9AF1A1L")||cpuis("MB9AF1A1M")||cpuis("MB9AF1A1N")||cpuis("MB9AF1A2L")||cpuis("MB9AF1A2M")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2L")||cpuis("MB9AFAA2M")||cpuis("MB9AFAA2N")) textline " " bitfld.word 0x00 3. " LVDH ,Low-voltage detection reset flag" "No reset,Reset" bitfld.word 0x00 1. " INITX ,INITX pin input reset flag" "No reset,Reset" bitfld.word 0x00 0. " PONR ,Power-on reset flag" "No reset,Reset" else textline " " bitfld.word 0x00 1. " INITX ,INITX pin input reset flag" "No reset,Reset" bitfld.word 0x00 0. " PONR ,Power-on reset/low-voltage detection reset flag" "No reset,Reset" endif group.long 0x10++0x03 line.byte 0x00 "BSC_PSR,Base Clock Prescaler Register" bitfld.byte 0x00 0.--2. " BSR ,Base clock frequency division ratio setting bit" "1/1,1/2,1/3,1/4,1/6,1/8,1/16," group.long 0x14++0x03 line.byte 0x00 "APBC0_PSR,APB0 Prescaler Register" bitfld.byte 0x00 0.--1. " APBC0 ,APB0 bus clock frequency division ratio setting bit" "1/1,1/2,1/4,1/8" group.long 0x018++0x03 line.byte 0x00 "APBC1_PSR,APB1 Prescaler Register" bitfld.byte 0x00 7. " APBC1EN ,APB1 clock enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " APBC1RST ,APB1 bus reset control bit" "Inactive,Active" bitfld.byte 0x00 0.--1. " APBC1 ,APB1 bus clock frequency division ratio setting bit" "1/1,1/2,1/4,1/8" group.long 0x01C++0x03 line.byte 0x00 "APBC2_PSR,APB2 Prescaler Register" bitfld.byte 0x00 7. " APBC2EN ,APB2 clock enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " APBC2RST ,APB2 bus reset control bit" "Inactive,Active" bitfld.byte 0x00 0.--1. " APBC2 ,APB2 bus clock frequency division ratio setting bit" "1/1,1/2,1/4,1/8" group.long 0x20++0x03 line.byte 0x00 "SWC_PSR,Software Watchdog Clock Prescaler Register" bitfld.byte 0x00 7. " TESTB ,Test bit" ",1" bitfld.byte 0x00 0.--1. " SWDS ,Software watchdog clock frequency division ratio setting bit" "1/1,1/2,1/4,1/8" group.long 0x28++0x03 line.byte 0x00 "TTC_PSR,Trace Clock Prescaler Register" sif (cpuis("MB9BF102N*")||cpuis("MB9BF102R*")||cpuis("MB9BF104N*")||cpuis("MB9BF104R*")||cpuis("MB9BF105N*")||cpuis("MB9BF105R*")||cpuis("MB9BF106N*")||cpuis("MB9BF106R*")) bitfld.byte 0x00 0. " TTC ,Trace clock frequency division ratio setting bit" "1/1,1/2" else bitfld.byte 0x00 0.--1. " TTC ,Trace clock frequency division ratio setting bit" "1/1,1/2,1/4,1/8" endif group.long 0x30++0x03 line.byte 0x00 "CSW_TMR,Clock Stabilization Wait Time Register" bitfld.byte 0x00 4.--6. " SOWT ,Sub clock stabilization wait time setup bit" "2^10/Fcl,2^11/Fcl,2^12/Fcl,2^13/Fcl,2^14/Fcl,2^15/Fcl,2^16/Fcl,2^17/Fcl" bitfld.byte 0x00 0.--3. " MOWT ,Main clock stabilization wait time setup bit" "2^1/Fch,2^5/Fch,2^6/Fch,2^7/Fch,2^8/Fch,2^9/Fch,2^10/Fch,2^11/Fch,2^12/Fch,2^13/Fch,2^14/Fch,2^15/Fch,2^17/Fch,2^19/Fch,2^21/Fch,2^23/Fch" group.long 0x34++0x03 line.byte 0x00 "PSW_TMR,PLL Clock Stabilization Wait Time Setup Register" bitfld.byte 0x00 4. " PINC ,PLL input clock select bit" "CLKMO,Disabled" bitfld.byte 0x00 0.--2. " POWT ,PLL clock stabilization wait time setup bit" "2^9/Fch,2^10/Fch,2^11/Fch,2^12/Fch,2^13/Fch,2^14/Fch,2^15/Fch,2^16/Fch" group.long 0x38++0x03 line.byte 0x00 "PLL_CTL1,PLL Control Register 1" bitfld.byte 0x00 4.--7. " PLLK ,PLL input clock frequency division ratio setting bit" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16" bitfld.byte 0x00 0.--3. " PLLM ,PLL VCO clock frequency division ratio setting bit" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16" group.long 0x3C++0x03 line.byte 0x00 "PLL_CTL2,PLL Control Register 2" sif (cpuis("MB9BF50*")||cpuis("MB9BF40*")||cpuis("MB9BF30*")||cpuis("MB9BF10*")) bitfld.byte 0x00 0.--4. " PLLN ,PLL feedback frequency division ratio setting bit" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32" else bitfld.byte 0x00 0.--5. " PLLN ,PLL feedback frequency division ratio setting bit" "1/1,1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32,1/33,1/34,1/35,1/36,1/37,1/38,1/39,1/40,1/41,1/42,1/43,1/44,1/45,1/46,1/47,1/48,1/49,1/50,..." endif group.long 0x40++0x03 line.word 0x00 "CSV_CTL,CSV control register" bitfld.word 0x00 12.--14. " FCD ,FCS count cycle setting bits" "Disabled,Disabled,Disabled,Disabled,Disabled,1/256,1/512,1/1024" bitfld.word 0x00 9. " FCSRE ,FCS reset output enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " FCSDE ,FCS function enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " SCSVE ,Sub CSV function enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " MCSVE ,Main CSV function enable bit" "Disabled,Enabled" rgroup.long 0x44++0x03 line.byte 0x00 "CSV_STR,CSV status register" bitfld.byte 0x00 1. " SCMF ,Sub clock failure detection flag" "Not detected,Detected" bitfld.byte 0x00 0. " MCMF ,Main clock failure detection flag" "Not detected,Detected" group.long 0x48++0x03 line.word 0x00 "FCSWH_CTL,Frequency detection window setting register (Upper)" group.long 0x4C++0x03 line.word 0x00 "FCSWL_CTL,Frequency detection window setting register (Lower)" rgroup.long 0x50++0x03 line.word 0x00 "FCSWD_CTL,Frequency detection counter register" group.long 0x54++0x03 line.byte 0x00 "DBWDT_CTL,Debug Break Watchdog Timer Control Register" bitfld.byte 0x00 7. " DPHWBE ,HW-WDG debug mode break bit" "Stop count,Continue count" bitfld.byte 0x00 5. " DPSWBE ,SW-WDG debug mode break bit" "Stop count,Continue count" group.long 0x60++0x03 line.byte 0x00 "INT_ENR,Interrupt Enable Register" bitfld.byte 0x00 5. " FCSE ,Anomalous frequency detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " PCSE ,PLL oscillation stabilization completion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " SCSE ,Sub oscillation stabilization completion interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " MCSE ,Main oscillation stabilization completion interrupt enable bit" "Disabled,Enabled" rgroup.long 0x64++0x03 line.byte 0x00 "INT_STR,Interrupt Status Register" bitfld.byte 0x00 5. " FCSI ,Anomalous frequency detection interrupt status bit" "No asserted,Asserted" bitfld.byte 0x00 2. " PCSI ,PLL oscillation stabilization completion interrupt status bit" "No asserted,Asserted" bitfld.byte 0x00 1. " SCSI ,Sub oscillation stabilization completion interrupt status bit" "No asserted,Asserted" textline " " bitfld.byte 0x00 0. " MCSI ,Main oscillation stabilization completion interrupt status bit" "No asserted,Asserted" wgroup.long 0x68++0x03 line.byte 0x00 "INT_CLR,Interrupt Clear Register" bitfld.byte 0x00 5. " FCSC ,Anomalous frequency detection interrupt cause clear bit" "Not clear,Clear" bitfld.byte 0x00 2. " PCSC ,PLL oscillation stabilization completion interrupt cause clear bit" "Not clear,Clear" bitfld.byte 0x00 1. " SCSC ,Sub oscillation stabilization completion interrupt cause clear bit" "Not clear,Clear" textline " " bitfld.byte 0x00 0. " MCSC ,Main oscillation stabilization completion interrupt cause clear bit" "Not clear,Clear" width 0xb tree.end tree "High-Speed CR Trimming" base ad:0x4002E000 width 10. group.byte 0x00++0x00 line.byte 0x00 "MCR_PSR,High-speed CR oscillation Frequency Division Setup Register" sif (cpuis("MB9AF13??")||cpuis("MB9AFA3??")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2L")||cpuis("MB9AFAA2M")||cpuis("MB9AFAA2N")||cpuis("MB9AF1A1L")||cpuis("MB9AF1A1M")||cpuis("MB9AF1A1N")||cpuis("MB9AF1A2L")||cpuis("MB9AF1A2M")||cpuis("MB9AF1A2N")) bitfld.byte 0x00 0.--2. " CSR ,High-speed CR oscillation frequency division ratio setting bit" "1/4,1/8,1/16,1/32,1/64,1/128,1/256,1/512" else bitfld.byte 0x00 0.--1. " CSR ,High-speed CR oscillation frequency division ratio setting bit" "1/4,1/8,1/16,1/32" endif group.long 0x04++0x03 line.long 0x00 "MCR_FTRM,High-speed CR oscillation Frequency Trimming Register" sif (cpuis("MB9AF31??")||cpuis("MB9AF11??")||cpuis("MB9BF61??")||cpuis("MB9BF51??")||cpuis("MB9BF41??")||cpuis("MB9BF31??")||cpuis("MB9BF21??")||cpuis("MB9BF11??")||cpuis("MB9BFD16S")||cpuis("MB9BFD16T")||cpuis("MB9BFD17S")||cpuis("MB9BFD17T")||cpuis("MB9BFD18S")||cpuis("MB9BFD18T")) hexmask.long.byte 0x00 0.--7. 1. " TRD ,Frequency trimming setup bit" else bitfld.long 0x00 5.--9. " TRD[9:5] ,Frequency trimming setup bit (approximately 6% each time)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " TRD[4:0] ,Frequency trimming setup bit (approximately 0.4% each time)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.long 0x0C++0x03 line.long 0x00 "MCR_RLR,High-Speed CR Oscillator Register Write-Protect Register" sif (cpuis("MB9B12??")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155N")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")||cpuis("MB9AF121K")||cpuis("MB9AF121L")||cpuis("MB9BF124K")||cpuis("MB9BF124L")||cpuis("MB9BF124M")||cpuis("MB9BF122K")||cpuis("MB9BF122L")||cpuis("MB9BF122M")||cpuis("MB9BF121K")||cpuis("MB9BF121L")||cpuis("MB9BF121M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF524K")||cpuis("MB9BF524L")||cpuis("MB9BF524M")||cpuis("MB9BF522K")||cpuis("MB9BF522L")||cpuis("MB9BF522M")||cpuis("MB9BF521K")||cpuis("MB9BF521L")||cpuis("MB9BF521M")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")||cpuis("MB9BF329S")||cpuis("MB9BF329T")||cpuis("MB9BF328S")||cpuis("MB9BF328T")||cpuis("MB9BF129S")||cpuis("MB9BF129T")||cpuis("MB9BF128S")||cpuis("MB9BF128T")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF428S")||cpuis("MB9BF428T")) group.long 0x00++0x03 line.long 0x00 "MCR_TTRM,High-Speed CR Oscillation Temperature Trimming Register" bitfld.long 0x00 0.--4. " TRT , Temperature trimming setup bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif width 0xb tree.end tree "Low-voltage Detection" base ad:0x40035000 width 10. sif (cpuis("MB9AF13??")||cpuis("MB9AFA3??")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2L")||cpuis("MB9AFAA2M")||cpuis("MB9AFAA2N")||cpuis("MB9AF1A1L")||cpuis("MB9AF1A1M")||cpuis("MB9AF1A1N")||cpuis("MB9AF1A2L")||cpuis("MB9AF1A2M")||cpuis("MB9AF1A2N")) group.word 0x0++0x1 line.word 0x0 "LVD_CTL,Low-voltage Detection Voltage Control Register" bitfld.word 0x00 15. " LVDRE ,Low-voltage detection reset operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--13. " SVHR ,Low-voltage detection reset voltage setting" ",1.53V,,,1.93V,,,,,,,,,,," textline " " bitfld.word 0x00 7. " LVDIE ,Low-voltage detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 2.--5. " SVHI ,Low-voltage detection interrupt voltage setting" "2.0V,2.1V,2.2V,2.3V,2.4V,2.5V,2.6V,2.8V,3.0V,3.2V,3.6V,3.7V,4.0V,4.1V,4.2V," textline " " bitfld.word 0x00 1. " LVDIM ,Low-voltage detection interrupt low power mode select bit" "Normal,Low power" elif (cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155N")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")) group.word 0x0++0x1 line.word 0x0 "LVD_CTL,Low-voltage Detection Voltage Control Register" bitfld.word 0x00 15. " LVDRE ,Low-voltage detection reset operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--14. " SVHR ,Low-voltage detection reset voltage setting" "1.50V,1.55V,1.60V,1.65V,1.70V,1.75V,1.80V,1.85V,1.90V,1.95V,2.00V,2.05V,2.50V,2.60,2.70V,2.80V,2.90V,3.00V,3.10V,3.20V,,,,,,,,,,,," textline " " bitfld.word 0x00 7. " LVDIE ,Low-voltage detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 2.--6. " SVHI ,Low-voltage detection interrupt voltage setting" ",,,,1.70V,1.75V,1.80V,1.85V,1.90V,1.95V,2.00V,2.05V,2.50V,2.60V,2.70V,2.80V,2.90V,3.00V,3.10V,3.20V,,,,,,,,,,,," textline " " bitfld.word 0x00 1. " LVDIM ,Low-voltage detection interrupt low power mode select bit" "Normal,Low power" elif (cpuis("MB9BF121J")||cpuis("MB9BF129T")||cpuis("MB9BF129S")||cpuis("MB9BF128T")||cpuis("MB9BF128S")||cpuis("MB9BF329S")||cpuis("MB9BF329T")||cpuis("MB9BF328S")||cpuis("MB9BF328T")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF428S")||cpuis("MB9BF428T")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")||cpuis("MB9AF121K")||cpuis("MB9AF121L")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF124K")||cpuis("MB9BF124L")||cpuis("MB9BF124M")||cpuis("MB9BF122K")||cpuis("MB9BF122L")||cpuis("MB9BF122M")||cpuis("MB9BF121K")||cpuis("MB9BF121L")||cpuis("MB9BF121M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF524K")||cpuis("MB9BF524L")||cpuis("MB9BF524M")||cpuis("MB9BF522K")||cpuis("MB9BF522L")||cpuis("MB9BF522M")||cpuis("MB9BF521K")||cpuis("MB9BF521L")||cpuis("MB9BF521M")) group.word 0x0++0x1 line.word 0x0 "LVD_CTL,Low-voltage Detection Voltage Control Register" bitfld.word 0x00 15. " LVDRE ,Low-voltage detection reset operation enable bit" "Disabled,Enabled" bitfld.word 0x00 10.--14. " SVHR ,Low-voltage detection reset voltage setting" "2.45V,2.60V,2.70V,2.80V,3.00V,3.20V,3.60V,3.70V,4.00V,4.10V,4.20V,?..." textline " " bitfld.word 0x00 7. " LVDIE ,Low-voltage detection interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 2.--6. " SVHI ,Low-voltage detection interrupt voltage setting" ",,,2.80V,3.00V,3.20V,3.60V,3.70V,4.00V,4.10V,4.20V,?..." else group.byte 0x0++0x0 line.byte 0x0 "LVD_CTL,Low-voltage Detection Voltage Control Register" bitfld.byte 0x00 7. " LVDIE ,Low-voltage detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--5. " SVHI ,Low-voltage detection interrupt voltage setting" "2.8V,3.0V,3.2V,3.6V,3.7V,,,4.0V,4.1V,4.2V,,,,,," endif rgroup.byte 0x4++0x0 line.byte 0x0 "LVD_STR,Low-voltage Detection Interrupt Register" bitfld.byte 0x00 7. " LVDIR ,Low-voltage detection interrupt bit" "Not detected,Detected" group.byte 0x8++0x0 line.byte 0x0 "LVD_CLR,Low-voltage Detection Interrupt Clear Register" bitfld.byte 0x00 7. " LVDCL ,Low-voltage detection interrupt clear bit" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "LVD_RLR,Low-voltage Detection Voltage Protection Register" rgroup.byte 0x10++0x0 line.byte 0x0 "LVD_STR2,Low-voltage Detection Circuit Status Register" bitfld.byte 0x00 7. " LVDIRDY ,Low-voltage detection interrupt status flag" "Stabilization wait or monitoring stop,Monitoring" textline " " bitfld.byte 0x00 6. " LVDRRDY ,Low-voltage detection reset status flag" "Stabilization wait or monitoring stop,Monitoring" width 0xb tree.end tree "Low Power Consumption Mode" base ad:0x40035100 width 9. sif (cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF52?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF32?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")) group.byte 0x00++0x0 line.byte 0x0 "REG_CTL,Sub Oscillation Circuit Power Supply Control Register" bitfld.byte 0x00 1.--2. " ISUBSEL ,Sub oscillation circuit current setting bits" ",,360nA,?..." endif sif (cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AFA3??")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF52?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF32?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")) group.byte 0x04++0x0 line.byte 0x0 "RCK_CTL,Sub Clock Control Register" bitfld.byte 0x00 1. " CECCKE ,CEC clock control bit" "Not supplied,Supplied" bitfld.byte 0x00 0. " RTCCKE ,RTC clock control bit" "Not supplied,Supplied" endif sif (cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AFA3??")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF11?K")||cpuis("MB9AF31?K")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")) group.byte 0x700++0x0 line.byte 0x0 "PMD_CTL,RTC Mode Control Register" bitfld.byte 0x00 0. " RTCE ,RTC mode control bit" "STOP,RTC" endif sif (!cpuis("MB9AF10*")&&!cpuis("MB9BF30*")&&!cpuis("MB9BF10*")&&!cpuis("MB9BF40*")&&!cpuis("MB9BF50*")&&!cpuis("MB9AF31?L")&&!cpuis("MB9AF31?M")&&!cpuis("MB9AF31?N")&&!cpuis("MB9AF11?L")&&!cpuis("MB9AF11?M")&&!cpuis("MB9AF11?N")&&!cpuis("MB9BF51??")&&!cpuis("MB9BF41??")&&!cpuis("MB9BF61??")&&!cpuis("MB9BF31??")&&!cpuis("MB9BF21??")&&!cpuis("MB9BF11??")&&!cpuis("MB9BFD1??")&&!cpuis("MB9AF121K")&&!cpuis("MB9AF121L")&&!cpuis("MB9BF121J")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")) hgroup.byte 0x704++0x0 hide.byte 0x0 "WRFSR,Deep Standby Return Factor Register 1" in hgroup.word 0x708++0x1 hide.word 0x0 "WIFSR,Deep Standby Return Factor Register 2" in group.word 0x70C++0x1 line.word 0x0 "WIER,Deep Standby Return Enable Register" bitfld.word 0x00 9. " WCEC1E ,CEC ch.1 interrupt return enable bit" "Disabled,Enabled" bitfld.word 0x00 8. " WCEC0E ,CEC ch.0 interrupt return enable bit" "Disabled,Enabled" bitfld.word 0x00 7. " WUI5E ,WKUP pin input return enable bit 5" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " WUI4E ,WKUP pin input return bit enable 4" "Disabled,Enabled" bitfld.word 0x00 5. " WUI3E ,WKUP pin input return bit enable 3" "Disabled,Enabled" bitfld.word 0x00 4. " WUI2E ,WKUP pin input return bit enable 2" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " WUI1E ,WKUP pin input return bit enable 1" "Disabled,Enabled" bitfld.word 0x00 1. " WLVDE ,LVD interrupt return enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " WRTCE ,RTC interrupt return enable bit" "Disabled,Enabled" group.byte 0x710++0x0 line.byte 0x0 "WILVR,WKUP Pin Input Level Register" bitfld.byte 0x00 4. " WUI5LV ,WKUP pin input level select bit 5" "Low,High" bitfld.byte 0x00 3. " WUI4LV ,WKUP pin input level select bit 4" "Low,High" bitfld.byte 0x00 2. " WUI3LV ,WKUP pin input level select bit 3" "Low,High" textline " " bitfld.byte 0x00 1. " WUI2LV ,WKUP pin input level select bit 2" "Low,High" bitfld.byte 0x00 0. " WUI1LV ,WKUP pin input level select bit 1" "Low,High" endif sif (cpuis("MB9AF11?K")||cpuis("MB9AF31?K")||cpuis("MB9AFB4??")||cpuis("MB9AFA4??")||cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF52?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")) sif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")) group.byte 0x714++0x0 line.byte 0x0 "DSRAMR,Deep Standby RAM Retention Register" bitfld.byte 0x00 0.--1. " SRAMR ,On-chip SRAM retention control bits" "Not retained,SRAM1,SRAM0,Both" else group.byte 0x714++0x0 line.byte 0x0 "DSRAMR,Deep Standby RAM Retention Register" bitfld.byte 0x00 0.--1. " SRAMR ,On-chip SRAM retention control bits" "Not retained,,,Retained" endif endif sif (!cpuis("MB9AF10*")&&!cpuis("MB9BF30*")&&!cpuis("MB9BF10*")&&!cpuis("MB9BF40*")&&!cpuis("MB9BF50*")&&!cpuis("MB9AF31?L")&&!cpuis("MB9AF31?M")&&!cpuis("MB9AF31?N")&&!cpuis("MB9AF11?L")&&!cpuis("MB9AF11?M")&&!cpuis("MB9AF11?N")&&!cpuis("MB9BF51??")&&!cpuis("MB9BF41??")&&!cpuis("MB9BF61??")&&!cpuis("MB9BF31??")&&!cpuis("MB9BF21??")&&!cpuis("MB9BF11??")&&!cpuis("MB9BFD1??")&&!cpuis("MB9AF121K")&&!cpuis("MB9AF121L")&&!cpuis("MB9BF121J")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")) group.byte 0x800++0xF line.byte 0x0 "BUR1,Backup Register 1" line.byte 0x1 "BUR2,Backup Register 2" line.byte 0x2 "BUR3,Backup Register 3" line.byte 0x3 "BUR4,Backup Register 4" line.byte 0x4 "BUR5,Backup Register 5" line.byte 0x5 "BUR6,Backup Register 6" line.byte 0x6 "BUR7,Backup Register 7" line.byte 0x7 "BUR8,Backup Register 8" line.byte 0x8 "BUR9,Backup Register 9" line.byte 0x9 "BUR10,Backup Register 10" line.byte 0xA "BUR11,Backup Register 11" line.byte 0xB "BUR12,Backup Register 12" line.byte 0xC "BUR13,Backup Register 13" line.byte 0xD "BUR14,Backup Register 14" line.byte 0xE "BUR15,Backup Register 15" line.byte 0xF "BUR16,Backup Register 16" endif width 0xb tree.end tree "Interrupts" base ad:0x40031000 sif (cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AFA3??")||cpuis("MB9AFAA*")||cpuis("MB9AF1A*")) width 10. rgroup.long 0x10++0x1B line.long 0x0 "EXC02MON,EXC02 Batch Read Register" bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " NMI ,External NMIX pin interrupt request" "Not requested,Requested" line.long 0x4 "IRQ00MON,IRQ00 Batch Read Register" bitfld.long 0x04 0. " FCSINT ,Abnormal frequency detection by CSV interrupt request" "Not requested,Requested" line.long 0x8 "IRQ01MON,IRQ01 Batch Read Register" bitfld.long 0x08 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested" line.long 0xC "IRQ02MON,IRQ02 Batch Read Register" bitfld.long 0x0C 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested" line.long 0x10 "IRQ03MON,IRQ03 Batch Read Register" bitfld.long 0x10 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " WAVE0INT[2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " WAVE0INT[1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " WAVE0INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ04MON,IRQ04 Batch Read Register" sif (!cpuis("MB9AF13?K")&&!cpuis("MB9AF*L")) bitfld.long 0x14 7. " EXTINT[7] ,Interrupt request on external interrupt ch. 7" "Not requested,Requested" textline " " endif bitfld.long 0x14 6. " EXTINT[6] ,Interrupt request on external interrupt ch. 6" "Not requested,Requested" textline " " sif (!cpuis("MB9AF13?K")) bitfld.long 0x14 5. " EXTINT[5] ,Interrupt request on external interrupt ch. 5" "Not requested,Requested" bitfld.long 0x14 4. " EXTINT[4] ,Interrupt request on external interrupt ch. 4" "Not requested,Requested" textline " " endif bitfld.long 0x14 3. " EXTINT[3] ,Interrupt request on external interrupt ch. 3" "Not requested,Requested" bitfld.long 0x14 2. " EXTINT[2] ,Interrupt request on external interrupt ch. 2" "Not requested,Requested" textline " " bitfld.long 0x14 1. " EXTINT[1] ,Interrupt request on external interrupt ch. 1" "Not requested,Requested" bitfld.long 0x14 0. " EXTINT[0] ,Interrupt request on external interrupt ch. 0" "Not requested,Requested" line.long 0x18 "IRQ05MON,IRQ05 Batch Read Register" bitfld.long 0x18 7. " EXTINT[15] ,Interrupt request on external interrupt ch. 15" "Not requested,Requested" sif (!cpuis("MB9AF13?K")&&!cpuis("MB9AF*L")) textline " " bitfld.long 0x18 6. " EXTINT[14] ,Interrupt request on external interrupt ch. 14" "Not requested,Requested" endif sif (cpuis("MB9AF*N")) textline " " bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " bitfld.long 0x18 3. " EXTINT[11] ,Interrupt request on external interrupt ch. 11" "Not requested,Requested" bitfld.long 0x18 2. " EXTINT[10] ,Interrupt request on external interrupt ch. 10" "Not requested,Requested" textline " " bitfld.long 0x18 1. " EXTINT[9] ,Interrupt request on external interrupt ch. 9" "Not requested,Requested" endif sif (!cpuis("MB9AF13?K")&&!cpuis("MB9AF*L")) textline " " bitfld.long 0x18 0. " EXTINT[8] ,Interrupt request on external interrupt ch. 8" "Not requested,Requested" endif sif (cpuis("MB9AF13?K")) rgroup.long 0x2C++0x1F line.long 0x0 "IRQ6MON,IRQ6 Batch Read Register" bitfld.long 0x0 0. " MFSINT ,Reception interrupt request on MFS channel 0" "Not requested,Requested" line.long (0x0+0x4) "IRQ7MON,IRQ7 Batch Read Register" bitfld.long (0x0+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x0+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" line.long 0x8 "IRQ8MON,IRQ8 Batch Read Register" bitfld.long 0x8 0. " MFSINT ,Reception interrupt request on MFS channel 1" "Not requested,Requested" line.long (0x8+0x4) "IRQ9MON,IRQ9 Batch Read Register" bitfld.long (0x8+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x8+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" line.long 0x10 "IRQ10MON,IRQ10 Batch Read Register" bitfld.long 0x10 0. " MFSINT ,Reception interrupt request on MFS channel 2" "Not requested,Requested" line.long (0x10+0x4) "IRQ11MON,IRQ11 Batch Read Register" bitfld.long (0x10+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x10+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" line.long 0x18 "IRQ12MON,IRQ12 Batch Read Register" bitfld.long 0x18 0. " MFSINT ,Reception interrupt request on MFS channel 3" "Not requested,Requested" line.long (0x18+0x4) "IRQ13MON,IRQ13 Batch Read Register" bitfld.long (0x18+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x18+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" else rgroup.long 0x2C++0x3F line.long 0x0 "IRQ6MON,IRQ6 Batch Read Register" bitfld.long 0x0 0. " MFSINT ,Reception interrupt request on MFS channel 0" "Not requested,Requested" line.long (0x0+0x4) "IRQ7MON,IRQ7 Batch Read Register" bitfld.long (0x0+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x0+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" line.long 0x8 "IRQ8MON,IRQ8 Batch Read Register" bitfld.long 0x8 0. " MFSINT ,Reception interrupt request on MFS channel 1" "Not requested,Requested" line.long (0x8+0x4) "IRQ9MON,IRQ9 Batch Read Register" bitfld.long (0x8+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x8+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" line.long 0x10 "IRQ10MON,IRQ10 Batch Read Register" bitfld.long 0x10 0. " MFSINT ,Reception interrupt request on MFS channel 2" "Not requested,Requested" line.long (0x10+0x4) "IRQ11MON,IRQ11 Batch Read Register" bitfld.long (0x10+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x10+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" line.long 0x18 "IRQ12MON,IRQ12 Batch Read Register" bitfld.long 0x18 0. " MFSINT ,Reception interrupt request on MFS channel 3" "Not requested,Requested" line.long (0x18+0x4) "IRQ13MON,IRQ13 Batch Read Register" bitfld.long (0x18+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x18+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" line.long 0x20 "IRQ14MON,IRQ14 Batch Read Register" bitfld.long 0x20 0. " MFSINT ,Reception interrupt request on MFS channel 4" "Not requested,Requested" line.long (0x20+0x4) "IRQ15MON,IRQ15 Batch Read Register" bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 4" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 4" "Not requested,Requested" line.long 0x28 "IRQ16MON,IRQ16 Batch Read Register" bitfld.long 0x28 0. " MFSINT ,Reception interrupt request on MFS channel 5" "Not requested,Requested" line.long (0x28+0x4) "IRQ17MON,IRQ17 Batch Read Register" bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" line.long 0x30 "IRQ18MON,IRQ18 Batch Read Register" bitfld.long 0x30 0. " MFSINT ,Reception interrupt request on MFS channel 6" "Not requested,Requested" line.long (0x30+0x4) "IRQ19MON,IRQ19 Batch Read Register" bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 6" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 6" "Not requested,Requested" line.long 0x38 "IRQ20MON,IRQ20 Batch Read Register" bitfld.long 0x38 0. " MFSINT ,Reception interrupt request on MFS channel 7" "Not requested,Requested" line.long (0x38+0x4) "IRQ21MON,IRQ21 Batch Read Register" bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 7" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 7" "Not requested,Requested" endif rgroup.long 0x6C++0x1B line.long 0x00 "IRQ22MON,IRQ22 Batch Read Register" bitfld.long 0x00 2. " PPGINT[2] ,Interrupt request on PPG ch. 4" "Not requested,Requested" bitfld.long 0x00 1. " PPGINT[1] ,Interrupt request on PPG ch. 2" "Not requested,Requested" bitfld.long 0x00 0. " PPGINT[0] ,Interrupt request on PPG ch. 0" "Not requested,Requested" line.long 0x04 "IRQ23MON,IRQ23 Batch Read Register" bitfld.long 0x04 5. " RTCINT ,RTC interrupt request" "Not requested,Requested" bitfld.long 0x04 2. " MPLLINT ,Stabilization wait completion interrupt request for PLL oscillation" "Not requested,Requested" bitfld.long 0x04 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested" bitfld.long 0x04 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested" line.long 0x08 "IRQ24MON,IRQ24 Batch Read Register" bitfld.long 0x08 3. " ADCINT[3] ,ADC unit0 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x08 2. " ADCINT[2] ,ADC unit0 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x08 1. " ADCINT[1] ,ADC unit0 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x08 0. " ADCINT[0] ,ADC unit0 priority conversion interrupt request" "Not requested,Requested" line.long 0x0C "IRQ25MON,IRQ25 Batch Read Register" bitfld.long 0x0C 5. " FRT0INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x0C 4. " FRT0INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x0C 3. " FRT0INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x0C 2. " FRT0INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x0C 1. " FRT0INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x0C 0. " FRT0INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" line.long 0x10 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x10 3. " ICU0INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " ICU0INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " ICU0INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " ICU0INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ27MON,IRQ27 Batch Read Register" bitfld.long 0x14 5. " OCU0INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x14 4. " OCU0INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x14 3. " OCU0INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x14 2. " OCU0INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x14 1. " OCU0INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x14 0. " OCU0INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 0" "Not requested,Requested" line.long 0x18 "IRQ28MON,IRQ28 Batch Read Register" bitfld.long 0x18 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x18 14. " BTINT[14] ,IRQ0 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x18 13. " BTINT[13] ,IRQ1 interrupt request on the base timer ch. 6" "Not requested,Requested" bitfld.long 0x18 12. " BTINT[12] ,IRQ0 interrupt request on the base timer ch. 6" "Not requested,Requested" textline " " bitfld.long 0x18 11. " BTINT[11] ,IRQ1 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x18 10. " BTINT[10] ,IRQ0 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x18 9. " BTINT[9] ,IRQ1 interrupt request on the base timer ch. 4" "Not requested,Requested" bitfld.long 0x18 8. " BTINT[8] ,IRQ0 interrupt request on the base timer ch. 4" "Not requested,Requested" textline " " bitfld.long 0x18 7. " BTINT[7] ,IRQ1 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x18 6. " BTINT[6] ,IRQ0 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x18 5. " BTINT[5] ,IRQ1 interrupt request on the base timer ch. 2" "Not requested,Requested" bitfld.long 0x18 4. " BTINT[4] ,IRQ0 interrupt request on the base timer ch. 2" "Not requested,Requested" textline " " bitfld.long 0x18 3. " BTINT[3] ,IRQ1 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x18 2. " BTINT[2] ,IRQ0 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x18 1. " BTINT[1] ,IRQ1 interrupt request on the base timer ch. 0" "Not requested,Requested" bitfld.long 0x18 0. " BTINT[0] ,IRQ0 interrupt request on the base timer ch. 0" "Not requested,Requested" sif (cpuis("MB9AFA*")||cpuis("MB9AFB*")) rgroup.long 0x88++0x03 line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register" bitfld.long 0x00 4. " LCDCINT ,LCDC interrupt request of LCD controller" "Not requested,Requested" endif sif (cpuis("MB9AFA*")||cpuis("MB9AF1A*")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF14?L")||cpuis("MB9AF14?M")||cpuis("MB9AF14?N")||cpuis("MB9AF34?L")||cpuis("MB9AF34?M")||cpuis("MB9AF34?N")||cpuis("MB9AF14?M")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AFA3??")) group.long 0x8C++0x07 line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register" bitfld.long 0x00 5. " RCEC0INT ,Interrupt request of HDMI-CEC/Remote controller reception ch.0" "Not requested,Requested" line.long 0x04 "IRQ31MON,IRQ31 Batch Read Register" bitfld.long 0x04 6. " RECE1INT ,Interrupt request of HDMI-CEC/Remote controller reception ch.1" "Not requested,Requested" endif width 12. elif (cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF11?K")||cpuis("MB9AF31?K")||cpuis("MB9AF?4*")) group.long 0x0C++0x03 line.long 0x00 "IRQCMODE,Interrupt Factor Vector Relocate Setting Register" bitfld.long 0x00 0. " IRQCMODER ,Relocate Exception and Interrupt Factor" "Not relocated,Relocated" textline " " if (((d.l(ad:0x40031000+0x0C))&0x01)==0x00) sif (cpuis("MB9BF?28?")||cpuis("MB9BF?29?")||cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF121J")||cpuis("MB9BF1?1K")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) width 10. group.long 0x0++0x03 line.long 0x0 "DRQSEL,DMA Request Selection Register" bitfld.long 0x0 31. " DRQSEL_[31] ,DMA Request for external interrupt ch.3" "CPU,DMAC" bitfld.long 0x0 30. " [30] ,DMA Request for external interrupt ch.2" "CPU,DMAC" bitfld.long 0x0 29. " [29] ,DMA Request for external interrupt ch.1" "CPU,DMAC" bitfld.long 0x0 28. " [28] ,DMA Request for external interrupt ch.0" "CPU,DMAC" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF52?K") bitfld.long 0x0 27. " [27] ,DMA Request for MFS ch.7 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 26. " [26] ,DMA Request for MFS ch.7 reception interrupt" "CPU,DMAC" bitfld.long 0x0 25. " [25] ,DMA Request for MFS ch.6 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 24. " [24] ,DMA Request for MFS ch.6 reception interrupt" "CPU,DMAC" endif textline " " sif cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L") bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" elif cpuis("MB9BF121J") bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" else bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 21. " [21] ,DMA Request for MFS ch.4 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 20. " [20] ,DMA Request for MFS ch.4 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" endif textline " " bitfld.long 0x0 15. " [15] ,DMA Request for MFS ch.1 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 14. " [14] ,DMA Request for MFS ch.1 reception interrupt" "CPU,DMAC" bitfld.long 0x0 13. " [13] ,DMA Request for MFS ch.0 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 12. " [12] ,DMA Request for MFS ch.0 reception interrupt" "CPU,DMAC" bitfld.long 0x0 11. " [11] ,DMA Request for base timer ch.6 interrupt" "CPU,DMAC" bitfld.long 0x0 10. " [10] ,DMA Request for base timer ch.4 interrupt" "CPU,DMAC" bitfld.long 0x0 9. " [9] ,DMA Request for base timer ch.2 interrupt" "CPU,DMAC" bitfld.long 0x0 8. " [8] ,DMA Request for base timer ch.0 interrupt" "CPU,DMAC" textline " " sif cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF121J") bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" elif cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" else bitfld.long 0x0 7. " [7] ,DMA Request for ADC unit2 interrupt" "CPU,DMAC" bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" endif textline " " sif cpuis("MB9BF328?")||cpuis("MB9BF329?")||cpuis("MB9BF528?")||cpuis("MB9BF529?")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") bitfld.long 0x0 4. " [4] ,DMA Request for USB ch.0 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 3. " [3] ,DMA Request for USB ch.0 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 2. " [2] ,DMA Request for USB ch.0 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 1. " [1] ,DMA Request for USB ch.0 EP2 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 0. " [0] ,DMA Request for USB ch.0 EP1 DRQ interrupt" "CPU,DMAC" endif textline " " rgroup.long 0x10++0x67 line.long 0x0 "EXC02MON,EXC02 Batch Read Register" bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " NMI ,External NMIX pin interrupt request" "Not requested,Requested" line.long 0x4 "IRQ00MON,IRQ00 Batch Read Register" bitfld.long 0x04 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested" line.long 0x8 "IRQ01MON,IRQ01 Batch Read Register" bitfld.long 0x08 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested" line.long 0xC "IRQ02MON,IRQ02 Batch Read Register" bitfld.long 0x0C 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested" line.long 0x10 "IRQ03MON,IRQ03 Batch Read Register" bitfld.long 0x10 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " WAVE0INT[2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " WAVE0INT[1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " WAVE0INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ04MON,IRQ04 Batch Read Register" bitfld.long 0x14 7. " EXTINT[7] ,Interrupt request on external interrupt ch. 7" "Not requested,Requested" bitfld.long 0x14 6. " EXTINT[6] ,Interrupt request on external interrupt ch. 6" "Not requested,Requested" bitfld.long 0x14 5. " EXTINT[5] ,Interrupt request on external interrupt ch. 5" "Not requested,Requested" bitfld.long 0x14 4. " EXTINT[4] ,Interrupt request on external interrupt ch. 4" "Not requested,Requested" textline " " bitfld.long 0x14 3. " EXTINT[3] ,Interrupt request on external interrupt ch. 3" "Not requested,Requested" bitfld.long 0x14 2. " EXTINT[2] ,Interrupt request on external interrupt ch. 2" "Not requested,Requested" bitfld.long 0x14 1. " EXTINT[1] ,Interrupt request on external interrupt ch. 1" "Not requested,Requested" bitfld.long 0x14 0. " EXTINT[0] ,Interrupt request on external interrupt ch. 0" "Not requested,Requested" sif !cpuis("MB9BF121J") line.long 0x18 "IRQ05MON,IRQ05 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L") sif cpuis("MB9BF12?M")||cpuis("MB9BF32?M")||cpuis("MB9BF52?M") bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " else bitfld.long 0x18 23. " EXTINT[31] ,Interrupt request on external interrupt ch. 31" "Not requested,Requested" bitfld.long 0x18 22. " EXTINT[30] ,Interrupt request on external interrupt ch. 30" "Not requested,Requested" bitfld.long 0x18 21. " EXTINT[29] ,Interrupt request on external interrupt ch. 29" "Not requested,Requested" bitfld.long 0x18 20. " EXTINT[28] ,Interrupt request on external interrupt ch. 28" "Not requested,Requested" textline " " bitfld.long 0x18 19. " EXTINT[27] ,Interrupt request on external interrupt ch. 27" "Not requested,Requested" bitfld.long 0x18 18. " EXTINT[26] ,Interrupt request on external interrupt ch. 26" "Not requested,Requested" bitfld.long 0x18 17. " EXTINT[25] ,Interrupt request on external interrupt ch. 25" "Not requested,Requested" bitfld.long 0x18 16. " EXTINT[24] ,Interrupt request on external interrupt ch. 24" "Not requested,Requested" textline " " bitfld.long 0x18 15. " EXTINT[23] ,Interrupt request on external interrupt ch. 23" "Not requested,Requested" bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " endif endif sif !cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF52?K") sif cpuis("MB9BF12?L")||cpuis("MB9BF32?L")||cpuis("MB9BF52?L") bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " else bitfld.long 0x18 11. " EXTINT[19] ,Interrupt request on external interrupt ch. 19" "Not requested,Requested" bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " else bitfld.long 0x18 7. " EXTINT[15] ,Interrupt request on external interrupt ch. 15" "Not requested,Requested" bitfld.long 0x18 6. " EXTINT[14] ,Interrupt request on external interrupt ch. 14" "Not requested,Requested" bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " endif bitfld.long 0x18 3. " EXTINT[11] ,Interrupt request on external interrupt ch. 11" "Not requested,Requested" bitfld.long 0x18 2. " EXTINT[10] ,Interrupt request on external interrupt ch. 10" "Not requested,Requested" bitfld.long 0x18 1. " EXTINT[9] ,Interrupt request on external interrupt ch. 9" "Not requested,Requested" bitfld.long 0x18 0. " EXTINT[8] ,Interrupt request on external interrupt ch. 8" "Not requested,Requested" endif line.long 0x1C "IRQ06MON,IRQ06 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?") sif cpuis("MB9BF129?")||cpuis("MB9BF329?")||cpuis("MB9BF429?")||cpuis("MB9BF529?")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") bitfld.long 0x1C 13. " QUD1INT[5] ,PC match & RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 12. " QUD1INT[4] ,Interrupt request detected RC out of range on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 11. " QUD1INT[3] ,PC counter direction change interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " bitfld.long 0x1C 10. " QUD1INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 9. " QUD1INT[1] ,PC&RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 8. " QUD1INT[0] ,PC match interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " endif bitfld.long 0x1C 7. " QUD0INT[5] ,PC match & RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 6. " QUD0INT[4] ,Interrupt request detected RC out of range on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 5. " QUD0INT[3] ,PC counter direction change interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " bitfld.long 0x1C 4. " QUD0INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 3. " QUD0INT[1] ,PC&RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 2. " QUD0INT[0] ,PC match interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " endif bitfld.long 0x1C 1. " TIMINT[1] ,Dual timer TIMINT2 interrupt request" "Not requested,Requested" bitfld.long 0x1C 0. " TIMINT[0] ,Dual timer TIMINT1 interrupt request" "Not requested,Requested" line.long 0x20 "IRQ7MON,IRQ7 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" else bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" endif line.long (0x20+0x4) "IRQ8MON,IRQ8 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" else bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" endif line.long 0x28 "IRQ9MON,IRQ9 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" else bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" endif line.long (0x28+0x4) "IRQ10MON,IRQ10 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" else bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" endif line.long 0x30 "IRQ11MON,IRQ11 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " else bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" endif line.long (0x30+0x4) "IRQ12MON,IRQ12 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " else bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" endif line.long 0x38 "IRQ13MON,IRQ13 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " else bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" else bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" endif line.long (0x38+0x4) "IRQ14MON,IRQ14 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " else bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" else bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" endif line.long 0x40 "IRQ15MON,IRQ15 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x40 0. " MFSINT[0] ,Reception interrupt request on MFS channel 4" "Not requested,Requested" endif line.long (0x40+0x4) "IRQ16MON,IRQ16 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x40+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 4" "Not requested,Requested" bitfld.long (0x40+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 4" "Not requested,Requested" endif line.long 0x48 "IRQ17MON,IRQ17 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" else bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" endif line.long (0x48+0x4) "IRQ18MON,IRQ18 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" else bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" endif line.long 0x50 "IRQ19MON,IRQ19 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long 0x50 1. " MFSINT[1] ,Reception interrupt request on MFS channel 14" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x50 0. " MFSINT[0] ,Reception interrupt request on MFS channel 6" "Not requested,Requested" endif line.long (0x50+0x4) "IRQ20MON,IRQ20 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long (0x50+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 14" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x50+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 6" "Not requested,Requested" bitfld.long (0x50+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 6" "Not requested,Requested" endif line.long 0x58 "IRQ21MON,IRQ21 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long 0x58 1. " MFSINT[1] ,Reception interrupt request on MFS channel 15" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x58 0. " MFSINT[0] ,Reception interrupt request on MFS channel 7" "Not requested,Requested" endif line.long (0x58+0x4) "IRQ22MON,IRQ22 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long (0x58+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 15" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x58+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 7" "Not requested,Requested" bitfld.long (0x58+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 7" "Not requested,Requested" endif line.long 0x60 "IRQ23MON,IRQ23 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M")&&!cpuis("MB9AF15?M")&&!cpuis("MB9AF15?N")&&!cpuis("MB9AF15?R") bitfld.long 0x60 5. " PPGINT[5] ,Interrupt request on PPG ch. 12" "Not requested,Requested" bitfld.long 0x60 4. " PPGINT[4] ,Interrupt request on PPG ch. 10" "Not requested,Requested" bitfld.long 0x60 3. " PPGINT[3] ,Interrupt request on PPG ch. 8" "Not requested,Requested" bitfld.long 0x60 2. " PPGINT[2] ,Interrupt request on PPG ch. 4" "Not requested,Requested" textline " " endif bitfld.long 0x60 1. " PPGINT[1] ,Interrupt request on PPG ch. 2" "Not requested,Requested" bitfld.long 0x60 0. " PPGINT[0] ,Interrupt request on PPG ch. 0" "Not requested,Requested" line.long 0x64 "IRQ24MON,IRQ24 Batch Read Register" bitfld.long 0x64 5. " RTCINT ,RTC interrupt request" "Not requested,Requested" bitfld.long 0x64 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested" textline " " sif cpuis("MB9BF32*")||cpuis("MB9BF52*") bitfld.long 0x64 3. " UPLLINT ,Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation" "Not requested,Requested" textline " " endif bitfld.long 0x64 2. " MPLLINT ,Stabilization wait completion interrupt request for PLL oscillation" "Not requested,Requested" bitfld.long 0x64 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested" textline " " bitfld.long 0x64 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested" rgroup.long 0x78++0x03 line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit0 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit0 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit0 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit0 priority conversion interrupt request" "Not requested,Requested" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J") sif cpuis("MB9BF?28?")||cpuis("MB9BF?29?")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" else rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" rgroup.long 0x80++0x03 line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit2 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit2 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit2 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit2 priority conversion interrupt request" "Not requested,Requested" endif endif rgroup.long 0x84++0x03 line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register" bitfld.long 0x00 5. " FRT0INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " FRT0INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 3. " FRT0INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " FRT0INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " FRT0INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " FRT0INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x88++0x03 line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register" bitfld.long 0x00 3. " ICU0INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " ICU0INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " ICU0INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " ICU0INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x8C++0x03 line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register" bitfld.long 0x00 5. " OCU0INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " OCU0INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 3. " OCU0INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " OCU0INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " OCU0INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " OCU0INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x90++0x03 line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[14] ,IRQ0 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[13] ,IRQ1 interrupt request on the base timer ch. 6" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[12] ,IRQ0 interrupt request on the base timer ch. 6" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[11] ,IRQ1 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[10] ,IRQ0 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[9] ,IRQ1 interrupt request on the base timer ch. 4" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[8] ,IRQ0 interrupt request on the base timer ch. 4" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[7] ,IRQ1 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[6] ,IRQ0 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[5] ,IRQ1 interrupt request on the base timer ch. 2" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[4] ,IRQ0 interrupt request on the base timer ch. 2" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[3] ,IRQ1 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[2] ,IRQ0 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[1] ,IRQ1 interrupt request on the base timer ch. 0" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[0] ,IRQ0 interrupt request on the base timer ch. 0" "Not requested,Requested" sif cpuis("MB9AF421?")||cpuis("MB9BF42*")||cpuis("MB9BF52*") sif cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF428S")||cpuis("MB9BF428T")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") rgroup.long 0x94++0x03 line.long 0x00 "IRQ32MON,IRQ32 Batch Read Register" bitfld.long 0x00 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" else rgroup.long 0x94++0x03 line.long 0x00 "IRQ32MON,IRQ32 Batch Read Register" bitfld.long 0x00 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" rgroup.long 0x98++0x03 line.long 0x00 "IRQ33MON,IRQ33 Batch Read Register" bitfld.long 0x00 0. " CAN1INT ,Interrupt request of CAN ch.1" "Not requested,Requested" endif endif sif cpuis("MB9BF32*")||cpuis("MB9BF52*") rgroup.long 0x9C++0x07 line.long 0x00 "IRQ34MON,IRQ34 Batch Read Register" bitfld.long 0x00 4. " USB0INT[4] ,Endpoint 5 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 3. " USB0INT[3] ,Endpoint 4 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 2. " USB0INT[2] ,Endpoint 3 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 1. " USB0INT[1] ,Endpoint 2 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB0INT[0] ,Endpoint 1 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" line.long 0x04 "IRQ35MON,IRQ35 Batch Read Register" bitfld.long 0x04 5. " USB0INT[5] ,Status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 4. " USB0INT[4] ,Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 3. " USB0INT[3] ,Status (SPK) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 2. " USB0INT[2] ,Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB0INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 0. " USB0INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch. 0" "Not requested,Requested" endif sif cpuis("MB9AF128?")||cpuis("MB9AF129?")||cpuis("MB9AF328?")||cpuis("MB9AF329?")||cpuis("MB9AF428?")||cpuis("MB9AF429?")||cpuis("MB9BF52*")||cpuis("MB9AF15*") rgroup.long 0xA4++0x07 line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" textline " " endif ; sif !cpuis("MB9BF121J")&&!cpuis("MB9AF421*")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") ; rgroup.long 0xA4++0x07 ; line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" ; bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" ; textline " " ; sif cpuis("MB9BF32*")||cpuis("MB9BF52*") ; bitfld.long 0x00 4. " USB1INT[4] ,Interrupt request of USB ch.1 Endpoint5 DRQ" "Not requested,Requested" ; bitfld.long 0x00 3. " USB1INT[3] ,Interrupt request of USB ch.1 Endpoint4 DRQ" "Not requested,Requested" ; textline " " ; bitfld.long 0x00 2. " USB1INT[2] ,Interrupt request of USB ch.1 Endpoint3 DRQ" "Not requested,Requested" ; bitfld.long 0x00 1. " USB1INT[1] ,Interrupt request of USB ch.1 Endpoint2 DRQ" "Not requested,Requested" ; textline " " ; bitfld.long 0x00 0. " USB1INT[0] ,Interrupt request of USB ch.1 Endpoint1 DRQ" "Not requested,Requested" ; endif ; line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" ; bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" ; textline " " ; sif cpuis("MB9BF32*")||cpuis("MB9BF52*") ; bitfld.long 0x04 5. " USB1INT[5] ,Interrupt request of USB ch.1 status (SOFIRQ, CMPIRQ)" "Not requested,Requested" ; bitfld.long 0x04 4. " USB1INT[4] ,Interrupt request of USB ch.1 status (DIRQ, URIRQ, RWKIRQ, CNNIRQ)" "Not requested,Requested" ; textline " " ; bitfld.long 0x04 3. " USB1INT[3] ,Interrupt request of USB ch.1 status (SPK)" "Not requested,Requested" ; bitfld.long 0x04 2. " USB1INT[2] ,Interrupt request of USB ch.1 status (SUSP, SOF, BRST, CONF, WKUP)" "Not requested,Requested" ; textline " " ; bitfld.long 0x04 1. " USB1INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch.1" "Not requested,Requested" ; bitfld.long 0x04 0. " USB1INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch.1" "Not requested,Requested" ; endif ; endif rgroup.long 0xAC++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" else line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" endif rgroup.long 0xB0++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" else line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" endif rgroup.long 0xB4++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" endif rgroup.long 0xB8++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" else line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" endif rgroup.long 0xBC++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ42MON,IRQ42 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 4" "Not requested,Requested" endif rgroup.long 0xC0++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" else line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" endif rgroup.long 0xC4++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ44MON,IRQ44 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 6" "Not requested,Requested" endif rgroup.long 0xC8++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ45MON,IRQ45 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 7" "Not requested,Requested" endif sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") rgroup.long 0xCC++0x03 line.long 0x00 "IRQ46MON,IRQ46 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[15] ,IRQ0 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[14] ,IRQ1 interrupt request of base timer ch.14" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[14] ,IRQ0 interrupt request of base timer ch.14" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[13] ,IRQ1 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[13] ,IRQ0 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[12] ,IRQ1 interrupt request of base timer ch.12" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[12] ,IRQ0 interrupt request of base timer ch.12" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[11] ,IRQ1 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[11] ,IRQ0 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[10] ,IRQ1 interrupt request of base timer ch.10" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[10] ,IRQ0 interrupt request of base timer ch.10" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[9] ,IRQ1 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[9] ,IRQ0 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[8] ,IRQ1 interrupt request of base timer ch.8" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[8] ,IRQ0 interrupt request of base timer ch.8" "Not requested,Requested" endif rgroup.long 0xD0++0x03 line.long 0x00 "IRQ47MON,IRQ47 Batch Read Register" bitfld.long 0x00 11. " FLASHINT ,RDY/HANG interrupt request for flash" "Not requested,Requested" sif cpuis("MB9BF32*")||cpuis("MB9BF52*") group.byte 0x20F++0x3 line.byte 0x00 "ODDPKS,USB ch.0 Odd Packet Size DMA Enable Register" bitfld.byte 0x00 4. " ODDPKS4 ,DMA USB.EP5DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 3. " ODDPKS3 ,DMA USB.EP4DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 2. " ODDPKS2 ,DMA USB.EP3DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 1. " ODDPKS1 ,DMA USB.EP2DT transfer bit width converted" "Not converted,Converted" textline " " bitfld.byte 0x00 0. " ODDPKS0 ,DMA USB.EP1DT transfer bit width converted" "Not converted,Converted" endif width 0x0b else width 10. group.long 0x0++0x03 line.long 0x0 "DRQSEL,DMA Request Selection Register" bitfld.long 0x0 31. " DRQSEL_[31] ,DMA Request for external interrupt ch.3" "CPU,DMAC" bitfld.long 0x0 30. " [30] ,DMA Request for external interrupt ch.2" "CPU,DMAC" bitfld.long 0x0 29. " [29] ,DMA Request for external interrupt ch.1" "CPU,DMAC" bitfld.long 0x0 28. " [28] ,DMA Request for external interrupt ch.0" "CPU,DMAC" bitfld.long 0x0 27. " [27] ,DMA Request for MFS ch.7 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 26. " [26] ,DMA Request for MFS ch.7 reception interrupt" "CPU,DMAC" bitfld.long 0x0 25. " [25] ,DMA Request for MFS ch.6 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 24. " [24] ,DMA Request for MFS ch.6 reception interrupt" "CPU,DMAC" textline " " bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 21. " [21] ,DMA Request for MFS ch.4 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 20. " [20] ,DMA Request for MFS ch.4 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" textline " " bitfld.long 0x0 15. " [15] ,DMA Request for MFS ch.1 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 14. " [14] ,DMA Request for MFS ch.1 reception interrupt" "CPU,DMAC" bitfld.long 0x0 13. " [13] ,DMA Request for MFS ch.0 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 12. " [12] ,DMA Request for MFS ch.0 reception interrupt" "CPU,DMAC" bitfld.long 0x0 11. " [11] ,DMA Request for base timer ch.6 interrupt" "CPU,DMAC" bitfld.long 0x0 10. " [10] ,DMA Request for base timer ch.4 interrupt" "CPU,DMAC" bitfld.long 0x0 9. " [9] ,DMA Request for base timer ch.2 interrupt" "CPU,DMAC" bitfld.long 0x0 8. " [8] ,DMA Request for base timer ch.0 interrupt" "CPU,DMAC" textline " " bitfld.long 0x0 7. " [7] ,DMA Request for ADC unit2 interrupt" "CPU,DMAC" bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" sif (!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x0 4. " [4] ,DMA Request for USB ch.0 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 3. " [3] ,DMA Request for USB ch.0 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 2. " [2] ,DMA Request for USB ch.0 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 1. " [1] ,DMA Request for USB ch.0 EP2 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 0. " [0] ,DMA Request for USB ch.0 EP1 DRQ interrupt" "CPU,DMAC" endif sif (cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF11?K")||cpuis("MB9AF31?K")||cpuis("MB9AF?4*")) group.long 0x08++0x03 line.long 0x00 "IRQCMODER,Interrupt Factor Vector Relocate Setting Register" bitfld.long 0x00 0. " IRQCMODER ,Relocate Exception and Interrupt Factor" "Not relocated,Relocated" endif sif (cpuis("MB9BFD16S")||cpuis("MB9BFD16T")||cpuis("MB9BFD17S")||cpuis("MB9BFD17T")||cpuis("MB9BFD18S")||cpuis("MB9BFD18T")||cpuis("MB9BF61?T")||cpuis("MB9BF51?T")||cpuis("MB9BF41?T")||cpuis("MB9BF31?T")||cpuis("MB9BF21?T")||cpuis("MB9BF11?T")||cpuis("MB9BF61?S")||cpuis("MB9BF51?S")||cpuis("MB9BF41?S")||cpuis("MB9BF31?S")||cpuis("MB9BF21?S")||cpuis("MB9BF11?S")) group.long 0x200++0x7 line.long 0x0 "DRQSEL1,DMA Request Select Register 1" bitfld.long 0x00 4. " DRQSEL1[4] ,DMA Request for USB ch.1 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x00 3. " [3] ,DMA Request for USB ch.1 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x00 2. " [2] ,DMA Request for USB ch.1 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x00 1. " [1] ,DMA Request for USB ch.1 EP2 DRQ interrupt" "CPU,DMAC" textline " " bitfld.long 0x00 0. " [0] ,DMA Request for USB ch.1 EP1 DRQ interrupt" "CPU,DMAC" line.long 0x4 "DQESEL,DMA Request Extended Selection Register" bitfld.long 0x04 28.--31. " ESEL31 ,IDREQ [31] DMA transfer request signal input source select" "External ch.3,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 24.--27. " ESEL30 ,IDREQ [30] DMA transfer request signal input source select" "External ch.2,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 20.--23. " ESEL27 ,IDREQ [27] DMA transfer request signal input source select" "External ch.1,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 16.--19. " ESEL26 ,IDREQ [26] DMA transfer request signal input source select" "MFS ch.7 receive,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." textline " " bitfld.long 0x04 12.--15. " ESEL25 ,IDREQ [25] DMA transfer request signal input source select" "MFS ch.7 send,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 8.--11. " ESEL24 ,IDREQ [24] DMA transfer request signal input source select" "MFS ch.6 receive,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 4.--7. " ESEL11 ,IDREQ [11] DMA transfer request signal input source select" "Base timer ch.6,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 0.--3. " ESEL10 ,IDREQ [10] DMA transfer request signal input source select" "Base timer ch.4,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." endif rgroup.long 0x10++0x67 line.long 0x0 "EXC02MON,EXC02 Batch Read Register" bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " NMI ,External NMIX pin interrupt request" "Not requested,Requested" line.long 0x4 "IRQ00MON,IRQ00 Batch Read Register" bitfld.long 0x04 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested" line.long 0x8 "IRQ01MON,IRQ01 Batch Read Register" bitfld.long 0x08 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested" line.long 0xC "IRQ02MON,IRQ02 Batch Read Register" bitfld.long 0x0C 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested" line.long 0x10 "IRQ03MON,IRQ03 Batch Read Register" sif (cpuis("MB9BFD16S")||cpuis("MB9BFD16T")||cpuis("MB9BFD17S")||cpuis("MB9BFD17T")||cpuis("MB9BFD18S")||cpuis("MB9BFD18T")) bitfld.long 0x10 11. " WAVE2INT[3] ,WFG timer 54 interrupt request in MFT unit 2" "Not requested,Requested" bitfld.long 0x10 10. " WAVE2INT[2] ,WFG timer 32 interrupt request in MFT unit 2" "Not requested,Requested" bitfld.long 0x10 9. " WAVE2INT[1] ,WFG timer 10 interrupt request in MFT unit 2" "Not requested,Requested" bitfld.long 0x10 8. " WAVE2INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 2" "Not requested,Requested" textline " " endif bitfld.long 0x10 7. " WAVE1INT[3] ,WFG timer 54 interrupt request in MFT unit 1" "Not requested,Requested" bitfld.long 0x10 6. " WAVE1INT[2] ,WFG timer 32 interrupt request in MFT unit 1" "Not requested,Requested" bitfld.long 0x10 5. " WAVE1INT[1] ,WFG timer 10 interrupt request in MFT unit 1" "Not requested,Requested" bitfld.long 0x10 4. " WAVE1INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 1" "Not requested,Requested" textline " " bitfld.long 0x10 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " WAVE0INT[2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " WAVE0INT[1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " WAVE0INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ04MON,IRQ04 Batch Read Register" sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x14 7. " EXTINT[7] ,Interrupt request on external interrupt ch. 7" "Not requested,Requested" textline " " endif bitfld.long 0x14 6. " EXTINT[6] ,Interrupt request on external interrupt ch. 6" "Not requested,Requested" sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) textline " " bitfld.long 0x14 5. " EXTINT[5] ,Interrupt request on external interrupt ch. 5" "Not requested,Requested" bitfld.long 0x14 4. " EXTINT[4] ,Interrupt request on external interrupt ch. 4" "Not requested,Requested" textline " " endif bitfld.long 0x14 3. " EXTINT[3] ,Interrupt request on external interrupt ch. 3" "Not requested,Requested" bitfld.long 0x14 2. " EXTINT[2] ,Interrupt request on external interrupt ch. 2" "Not requested,Requested" bitfld.long 0x14 1. " EXTINT[1] ,Interrupt request on external interrupt ch. 1" "Not requested,Requested" bitfld.long 0x14 0. " EXTINT[0] ,Interrupt request on external interrupt ch. 0" "Not requested,Requested" line.long 0x18 "IRQ05MON,IRQ05 Batch Read Register" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x18 23. " EXTINT[31] ,Interrupt request on external interrupt ch. 31" "Not requested,Requested" bitfld.long 0x18 22. " EXTINT[30] ,Interrupt request on external interrupt ch. 30" "Not requested,Requested" bitfld.long 0x18 21. " EXTINT[29] ,Interrupt request on external interrupt ch. 29" "Not requested,Requested" bitfld.long 0x18 20. " EXTINT[28] ,Interrupt request on external interrupt ch. 28" "Not requested,Requested" textline " " bitfld.long 0x18 19. " EXTINT[27] ,Interrupt request on external interrupt ch. 27" "Not requested,Requested" bitfld.long 0x18 18. " EXTINT[26] ,Interrupt request on external interrupt ch. 26" "Not requested,Requested" bitfld.long 0x18 17. " EXTINT[25] ,Interrupt request on external interrupt ch. 25" "Not requested,Requested" bitfld.long 0x18 16. " EXTINT[24] ,Interrupt request on external interrupt ch. 24" "Not requested,Requested" textline " " bitfld.long 0x18 15. " EXTINT[23] ,Interrupt request on external interrupt ch. 23" "Not requested,Requested" bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " bitfld.long 0x18 11. " EXTINT[19] ,Interrupt request on external interrupt ch. 19" "Not requested,Requested" bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " endif bitfld.long 0x18 7. " EXTINT[15] ,Interrupt request on external interrupt ch. 15" "Not requested,Requested" sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) textline " " bitfld.long 0x18 6. " EXTINT[14] ,Interrupt request on external interrupt ch. 14" "Not requested,Requested" textline " " endif sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " bitfld.long 0x18 3. " EXTINT[11] ,Interrupt request on external interrupt ch. 11" "Not requested,Requested" bitfld.long 0x18 2. " EXTINT[10] ,Interrupt request on external interrupt ch. 10" "Not requested,Requested" bitfld.long 0x18 1. " EXTINT[9] ,Interrupt request on external interrupt ch. 9" "Not requested,Requested" textline " " endif sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x18 0. " EXTINT[8] ,Interrupt request on external interrupt ch. 8" "Not requested,Requested" endif line.long 0x1C "IRQ06MON,IRQ06 Batch Read Register" sif (!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF14?L")&&!cpuis("MB9AF14?M")&&!cpuis("MB9AF14?N")&&!cpuis("MB9AF34?L")&&!cpuis("MB9AF34?M")&&!cpuis("MB9AF34?N")&&!cpuis("MB9AF14?M")&&!cpuis("MB9AF?4?L")&&!cpuis("MB9AF?4?M")&&!cpuis("MB9AF?4?N")) sif (cpuis("MB9B*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x1C 19. " QUD2INT[5] ,PC match & RC match interrupt request on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 18. " QUD2INT[4] ,Interrupt request detected RC out of range on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 17. " QUD2INT[3] ,PC counter direction change interrupt request on QPRC ch. 2" "Not requested,Requested" textline " " bitfld.long 0x1C 16. " QUD2INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 15. " QUD2INT[1] ,PC&RC match interrupt request on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 14. " QUD2INT[0] ,PC match interrupt request on QPRC ch. 2" "Not requested,Requested" textline " " endif sif (cpu()!="MB9AF111K"&&cpu()!="MB9AF112K"&&cpu()!="MB9AF132K"&&cpu()!="MB9AF311K"&&cpu()!="MB9AF312K") bitfld.long 0x1C 13. " QUD1INT[5] ,PC match & RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 12. " QUD1INT[4] ,Interrupt request detected RC out of range on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 11. " QUD1INT[3] ,PC counter direction change interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " bitfld.long 0x1C 10. " QUD1INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 9. " QUD1INT[1] ,PC&RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 8. " QUD1INT[0] ,PC match interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " endif bitfld.long 0x1C 7. " QUD0INT[5] ,PC match & RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 6. " QUD0INT[4] ,Interrupt request detected RC out of range on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 5. " QUD0INT[3] ,PC counter direction change interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " bitfld.long 0x1C 4. " QUD0INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 3. " QUD0INT[1] ,PC&RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 2. " QUD0INT[0] ,PC match interrupt request on QPRC ch. 0" "Not requested,Requested" endif textline " " bitfld.long 0x1C 1. " TIMINT[1] ,Dual timer TIMINT2 interrupt request" "Not requested,Requested" bitfld.long 0x1C 0. " TIMINT[0] ,Dual timer TIMINT1 interrupt request" "Not requested,Requested" line.long 0x20 "IRQ7MON,IRQ7 Batch Read Register" bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" line.long (0x20+0x4) "IRQ8MON,IRQ8 Batch Read Register" bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" line.long 0x28 "IRQ9MON,IRQ9 Batch Read Register" bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" line.long (0x28+0x4) "IRQ10MON,IRQ10 Batch Read Register" bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" line.long 0x30 "IRQ11MON,IRQ11 Batch Read Register" bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" line.long (0x30+0x4) "IRQ12MON,IRQ12 Batch Read Register" bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" line.long 0x38 "IRQ13MON,IRQ13 Batch Read Register" bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" line.long (0x38+0x4) "IRQ14MON,IRQ14 Batch Read Register" bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" line.long 0x40 "IRQ15MON,IRQ15 Batch Read Register" bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long 0x40 0. " MFSINT[0] ,Reception interrupt request on MFS channel 4" "Not requested,Requested" line.long (0x40+0x4) "IRQ16MON,IRQ16 Batch Read Register" bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 4" "Not requested,Requested" bitfld.long (0x40+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 4" "Not requested,Requested" line.long 0x48 "IRQ17MON,IRQ17 Batch Read Register" bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" line.long (0x48+0x4) "IRQ18MON,IRQ18 Batch Read Register" bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" line.long 0x50 "IRQ19MON,IRQ19 Batch Read Register" bitfld.long 0x50 1. " MFSINT[1] ,Reception interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long 0x50 0. " MFSINT[0] ,Reception interrupt request on MFS channel 6" "Not requested,Requested" line.long (0x50+0x4) "IRQ20MON,IRQ20 Batch Read Register" bitfld.long (0x50+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 6" "Not requested,Requested" bitfld.long (0x50+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 6" "Not requested,Requested" line.long 0x58 "IRQ21MON,IRQ21 Batch Read Register" bitfld.long 0x58 1. " MFSINT[1] ,Reception interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long 0x58 0. " MFSINT[0] ,Reception interrupt request on MFS channel 7" "Not requested,Requested" line.long (0x58+0x4) "IRQ22MON,IRQ22 Batch Read Register" bitfld.long (0x58+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 7" "Not requested,Requested" bitfld.long (0x58+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 7" "Not requested,Requested" line.long 0x60 "IRQ23MON,IRQ23 Batch Read Register" bitfld.long 0x60 8. " PPGINT[8] ,Interrupt request on PPG ch. 20" "Not requested,Requested" bitfld.long 0x60 7. " PPGINT[7] ,Interrupt request on PPG ch. 18" "Not requested,Requested" bitfld.long 0x60 6. " PPGINT[6] ,Interrupt request on PPG ch. 16" "Not requested,Requested" textline " " bitfld.long 0x60 5. " PPGINT[5] ,Interrupt request on PPG ch. 12" "Not requested,Requested" bitfld.long 0x60 4. " PPGINT[4] ,Interrupt request on PPG ch. 10" "Not requested,Requested" bitfld.long 0x60 3. " PPGINT[3] ,Interrupt request on PPG ch. 8" "Not requested,Requested" bitfld.long 0x60 2. " PPGINT[2] ,Interrupt request on PPG ch. 4" "Not requested,Requested" textline " " bitfld.long 0x60 1. " PPGINT[1] ,Interrupt request on PPG ch. 2" "Not requested,Requested" bitfld.long 0x60 0. " PPGINT[0] ,Interrupt request on PPG ch. 0" "Not requested,Requested" line.long 0x64 "IRQ24MON,IRQ24 Batch Read Register" sif (!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")&&!cpuis("MB9BFD16S")||!cpuis("MB9BFD16T")||!cpuis("MB9BFD17S")||!cpuis("MB9BFD17T")||!cpuis("MB9BFD18S")||!cpuis("MB9BFD18T")) bitfld.long 0x64 5. " RTCINT ,RTC interrupt request" "Not requested,Requested" textline " " endif bitfld.long 0x64 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested" bitfld.long 0x64 3. " UPLLINT ,Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation" "Not requested,Requested" bitfld.long 0x64 2. " MPLLINT ,Stabilization wait completion interrupt request for PLL oscillation" "Not requested,Requested" bitfld.long 0x64 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested" textline " " bitfld.long 0x64 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested" rgroup.long 0x78++0x03 line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit0 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit0 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit0 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit0 priority conversion interrupt request" "Not requested,Requested" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF14*")||cpuis("MB9AF3*")||cpuis("MB9AF?4*")||cpuis("MB9B*")) rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" endif rgroup.long 0x80++0x03 line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register" sif (cpuis("MB9AFA*")||cpuis("MB9AFB*")) bitfld.long 0x00 4. " LCDCINT ,LCDC interrupt request for LCD controller" "Not requested,Requested" textline " " endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF31*")||cpuis("MB9B*")) bitfld.long 0x00 3. " ADCINT[3] ,ADC unit2 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit2 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit2 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit2 priority conversion interrupt request" "Not requested,Requested" endif sif (!cpuis("MB9AF?4*")) rgroup.long 0x84++0x03 line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register" sif (cpuis("MB9BF*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x00 17. " FRT2INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 16. " FRT2INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 15. " FRT2INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " bitfld.long 0x00 14. " FRT2INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 13. " FRT2INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 12. " FRT2INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " endif sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) bitfld.long 0x00 11. " FRT1INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 10. " FRT1INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 9. " FRT1INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " bitfld.long 0x00 8. " FRT1INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 7. " FRT1INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 6. " FRT1INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " endif bitfld.long 0x00 5. " FRT0INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " FRT0INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 3. " FRT0INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " FRT0INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " FRT0INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " FRT0INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x88++0x03 line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register" sif (cpuis("MB9BF*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x00 11. " ICU2INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 10. " ICU2INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 9. " ICU2INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 8. " ICU2INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " endif sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) bitfld.long 0x00 7. " ICU1INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 6. " ICU1INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 5. " ICU1INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 4. " ICU1INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " endif bitfld.long 0x00 3. " ICU0INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " ICU0INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " ICU0INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " ICU0INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x8C++0x03 line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register" sif (cpuis("MB9BF*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x00 17. " OCU2INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 16. " OCU2INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 15. " OCU2INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 14. " OCU2INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 2" "Not requested,Requested" textline " " bitfld.long 0x00 13. " OCU2INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 12. " OCU2INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " endif sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) bitfld.long 0x00 11. " OCU1INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 10. " OCU1INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 9. " OCU1INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 8. " OCU1INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 1" "Not requested,Requested" textline " " bitfld.long 0x00 7. " OCU1INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 6. " OCU1INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " endif bitfld.long 0x00 5. " OCU0INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " OCU0INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 3. " OCU0INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " OCU0INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " OCU0INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " OCU0INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 0" "Not requested,Requested" endif rgroup.long 0x90++0x0B line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[14] ,IRQ0 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[13] ,IRQ1 interrupt request on the base timer ch. 6" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[12] ,IRQ0 interrupt request on the base timer ch. 6" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[11] ,IRQ1 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[10] ,IRQ0 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[9] ,IRQ1 interrupt request on the base timer ch. 4" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[8] ,IRQ0 interrupt request on the base timer ch. 4" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[7] ,IRQ1 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[6] ,IRQ0 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[5] ,IRQ1 interrupt request on the base timer ch. 2" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[4] ,IRQ0 interrupt request on the base timer ch. 2" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[3] ,IRQ1 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[2] ,IRQ0 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[1] ,IRQ1 interrupt request on the base timer ch. 0" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[0] ,IRQ0 interrupt request on the base timer ch. 0" "Not requested,Requested" line.long 0x04 "IRQ32MON,IRQ32 Batch Read Register" sif (cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BFD1")) bitfld.long 0x04 3. " MAC0LPI ,LPI interrupt request of Ethernet MAC ch.0" "Not requested,Requested" bitfld.long 0x04 2. " MAC0PMI ,PMI interrupt request of Ethernet MAC ch.0" "Not requested,Requested" bitfld.long 0x04 1. " MAC0SBD ,SBD interrupt request of Ethernet MAC ch.0" "Not requested,Requested" textline " " endif sif (cpuis("MB9BF4*")||cpuis("MB9BF5*")||cpuis("MB9BF6*")||cpuis("MB9BFD1*")) bitfld.long 0x04 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" endif line.long 0x08 "IRQ33MON,IRQ33 Batch Read Register" sif (cpuis("MB9BF61?S")||cpuis("MB9BF61?T"))||cpuis("MB9BFD1") bitfld.long 0x08 2. " MAC1PMI ,PMI interrupt request of Ethernet MAC ch.1" "Not requested,Requested" bitfld.long 0x08 1. " MAC1SBD ,SBD interrupt request of Ethernet MAC ch.1" "Not requested,Requested" textline " " endif sif (cpuis("MB9BF4*")||cpuis("MB9BF5*")||cpuis("MB9BF6*")||cpuis("MB9BFD1*")) bitfld.long 0x08 0. " CAN1INT ,Interrupt request of CAN ch.1" "Not requested,Requested" endif sif ((!cpuis("MB9BF102N"))&&(!cpuis("MB9BF102R"))&&(!cpuis("MB9AF105NA"))&&(!cpuis("MB9AF105RA"))&&(!cpuis("MB9AF11*"))&&(!cpuis("MB9AF13*"))&&(!cpuis("MB9AF14*"))&&(!cpuis("MB9AFA*"))&&(!cpuis("MB9BF11*"))&&(!cpuis("MB9B4*"))) rgroup.long 0x9C++0x07 line.long 0x00 "IRQ34MON,IRQ34 Batch Read Register" bitfld.long 0x00 4. " USB0INT[4] ,Endpoint 5 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 3. " USB0INT[3] ,Endpoint 4 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 2. " USB0INT[2] ,Endpoint 3 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 1. " USB0INT[1] ,Endpoint 2 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB0INT[0] ,Endpoint 1 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" line.long 0x04 "IRQ35MON,IRQ35 Batch Read Register" bitfld.long 0x04 5. " USB0INT[5] ,Status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 4. " USB0INT[4] ,Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 3. " USB0INT[3] ,Status (SPK) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 2. " USB0INT[2] ,Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB0INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 0. " USB0INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch. 0" "Not requested,Requested" endif rgroup.long 0xA4++0x07 line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" sif (cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF14?L")||cpuis("MB9AF14?M")||cpuis("MB9AF14?N")||cpuis("MB9AF34?L")||cpuis("MB9AF34?M")||cpuis("MB9AF34?N")||cpuis("MB9AF14?M")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AFA3??")) bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" textline " " endif sif (cpuis("MB9BFD1*")||cpuis("MB9BF2*")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF5*S")||cpuis("MB9BF5*T")||cpuis("MB9BF6*")) bitfld.long 0x00 4. " USB1INT[4] ,Interrupt request of USB ch.1 Endpoint5 DRQ" "Not requested,Requested" bitfld.long 0x00 3. " USB1INT[3] ,Interrupt request of USB ch.1 Endpoint4 DRQ" "Not requested,Requested" textline " " bitfld.long 0x00 2. " USB1INT[2] ,Interrupt request of USB ch.1 Endpoint3 DRQ" "Not requested,Requested" bitfld.long 0x00 1. " USB1INT[1] ,Interrupt request of USB ch.1 Endpoint2 DRQ" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB1INT[0] ,Interrupt request of USB ch.1 Endpoint1 DRQ" "Not requested,Requested" endif line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" sif (cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF14?L")||cpuis("MB9AF14?M")||cpuis("MB9AF14?N")||cpuis("MB9AF34?L")||cpuis("MB9AF34?M")||cpuis("MB9AF34?N")||cpuis("MB9AF14?M")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AFA3??")) bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" textline " " endif sif (cpuis("MB9BFD1*")||cpuis("MB9BF2*")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF5*S")||cpuis("MB9BF5*T")||cpuis("MB9BF6*")) bitfld.long 0x04 5. " USB1INT[5] ,Interrupt request of USB ch.1 status (SOFIRQ, CMPIRQ)" "Not requested,Requested" bitfld.long 0x04 4. " USB1INT[4] ,Interrupt request of USB ch.1 status (DIRQ, URIRQ, RWKIRQ, CNNIRQ)" "Not requested,Requested" textline " " bitfld.long 0x04 3. " USB1INT[3] ,Interrupt request of USB ch.1 status (SPK)" "Not requested,Requested" bitfld.long 0x04 2. " USB1INT[2] ,Interrupt request of USB ch.1 status (SUSP, SOF, BRST, CONF, WKUP)" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB1INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch.1" "Not requested,Requested" bitfld.long 0x04 0. " USB1INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch.1" "Not requested,Requested" endif rgroup.long 0xAC++0x03 line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" rgroup.long 0xB0++0x03 line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" rgroup.long 0xB4++0x03 line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" rgroup.long 0xB8++0x03 line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" rgroup.long 0xBC++0x03 line.long 0x00 "IRQ42MON,IRQ42 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 4" "Not requested,Requested" rgroup.long 0xC0++0x03 line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" rgroup.long 0xC4++0x03 line.long 0x00 "IRQ44MON,IRQ44 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 6" "Not requested,Requested" rgroup.long 0xC8++0x03 line.long 0x00 "IRQ45MON,IRQ45 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 7" "Not requested,Requested" sif (cpuis("MB9BF?1?S")||cpuis("MB9BF?1?T")) rgroup.long 0xCC++0x03 line.long 0x00 "IRQ46MON,IRQ46 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[15] ,IRQ0 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[14] ,IRQ1 interrupt request of base timer ch.14" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[14] ,IRQ0 interrupt request of base timer ch.14" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[13] ,IRQ1 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[13] ,IRQ0 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[12] ,IRQ1 interrupt request of base timer ch.12" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[12] ,IRQ0 interrupt request of base timer ch.12" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[11] ,IRQ1 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[11] ,IRQ0 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[10] ,IRQ1 interrupt request of base timer ch.10" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[10] ,IRQ0 interrupt request of base timer ch.10" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[9] ,IRQ1 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[9] ,IRQ0 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[8] ,IRQ1 interrupt request of base timer ch.8" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[8] ,IRQ0 interrupt request of base timer ch.8" "Not requested,Requested" endif rgroup.long 0xD0++0x03 line.long 0x00 "IRQ47MON,IRQ47 Batch Read Register" bitfld.long 0x00 11. " FLASHINT ,RDY/HANG interrupt request for flash" "Not requested,Requested" sif ((!cpuis("MB9BF102N"))&&(!cpuis("MB9BF102R"))&&(!cpuis("MB9AF105NA"))&&(!cpuis("MB9AF105RA"))&&(!cpuis("MB9AF11*"))&&(!cpuis("MB9AF13*"))&&(!cpuis("MB9AF14*"))&&(!cpuis("MB9AFA*"))&&(!cpuis("MB9BF11*"))&&(!cpuis("MB9B4*"))) group.byte 0x20F++0x3 line.byte 0x00 "ODDPKS,USB ch.0 Odd Packet Size DMA Enable Register" bitfld.byte 0x00 4. " ODDPKS4 ,DMA USB.EP5DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 3. " ODDPKS3 ,DMA USB.EP4DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 2. " ODDPKS2 ,DMA USB.EP3DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 1. " ODDPKS1 ,DMA USB.EP2DT transfer bit width converted" "Not converted,Converted" textline " " bitfld.byte 0x00 0. " ODDPKS0 ,DMA USB.EP1DT transfer bit width converted" "Not converted,Converted" endif width 12. endif else width 10. width 10. group.long 0x0++0x03 line.long 0x0 "DRQSEL,DMA Request Selection Register" bitfld.long 0x0 31. " DRQSEL_[31] ,DMA Request for external interrupt ch.3" "CPU,DMAC" bitfld.long 0x0 30. " [30] ,DMA Request for external interrupt ch.2" "CPU,DMAC" bitfld.long 0x0 29. " [29] ,DMA Request for external interrupt ch.1" "CPU,DMAC" bitfld.long 0x0 28. " [28] ,DMA Request for external interrupt ch.0" "CPU,DMAC" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF52?K") bitfld.long 0x0 27. " [27] ,DMA Request for MFS ch.7 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 26. " [26] ,DMA Request for MFS ch.7 reception interrupt" "CPU,DMAC" bitfld.long 0x0 25. " [25] ,DMA Request for MFS ch.6 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 24. " [24] ,DMA Request for MFS ch.6 reception interrupt" "CPU,DMAC" endif textline " " sif cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L") bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" elif cpuis("MB9BF121J") bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" else bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 21. " [21] ,DMA Request for MFS ch.4 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 20. " [20] ,DMA Request for MFS ch.4 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" endif textline " " bitfld.long 0x0 15. " [15] ,DMA Request for MFS ch.1 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 14. " [14] ,DMA Request for MFS ch.1 reception interrupt" "CPU,DMAC" bitfld.long 0x0 13. " [13] ,DMA Request for MFS ch.0 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 12. " [12] ,DMA Request for MFS ch.0 reception interrupt" "CPU,DMAC" bitfld.long 0x0 11. " [11] ,DMA Request for base timer ch.6 interrupt" "CPU,DMAC" bitfld.long 0x0 10. " [10] ,DMA Request for base timer ch.4 interrupt" "CPU,DMAC" bitfld.long 0x0 9. " [9] ,DMA Request for base timer ch.2 interrupt" "CPU,DMAC" bitfld.long 0x0 8. " [8] ,DMA Request for base timer ch.0 interrupt" "CPU,DMAC" textline " " sif cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF121J") bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" elif cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" else bitfld.long 0x0 7. " [7] ,DMA Request for ADC unit2 interrupt" "CPU,DMAC" bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" endif textline " " sif cpuis("MB9BF328?")||cpuis("MB9BF329?")||cpuis("MB9BF528?")||cpuis("MB9BF529?")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") bitfld.long 0x0 4. " [4] ,DMA Request for USB ch.0 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 3. " [3] ,DMA Request for USB ch.0 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 2. " [2] ,DMA Request for USB ch.0 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 1. " [1] ,DMA Request for USB ch.0 EP2 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 0. " [0] ,DMA Request for USB ch.0 EP1 DRQ interrupt" "CPU,DMAC" endif textline " " rgroup.long 0x10++0x67 line.long 0x0 "EXC02MON,EXC02 Batch Read Register" bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " NMI ,External NMIX pin interrupt request" "Not requested,Requested" line.long 0x4 "IRQ00MON,IRQ00 Batch Read Register" bitfld.long 0x04 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested" line.long 0x8 "IRQ01MON,IRQ01 Batch Read Register" bitfld.long 0x08 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested" line.long 0xC "IRQ02MON,IRQ02 Batch Read Register" bitfld.long 0x0C 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested" line.long 0x10 "IRQ03MON,IRQ03 Batch Read Register" bitfld.long 0x10 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " WAVE0INT[2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " WAVE0INT[1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " WAVE0INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ04MON,IRQ04 Batch Read Register" bitfld.long 0x14 7. " EXTINT[7] ,Interrupt request on external interrupt ch. 7" "Not requested,Requested" bitfld.long 0x14 6. " EXTINT[6] ,Interrupt request on external interrupt ch. 6" "Not requested,Requested" bitfld.long 0x14 5. " EXTINT[5] ,Interrupt request on external interrupt ch. 5" "Not requested,Requested" bitfld.long 0x14 4. " EXTINT[4] ,Interrupt request on external interrupt ch. 4" "Not requested,Requested" textline " " bitfld.long 0x14 3. " EXTINT[3] ,Interrupt request on external interrupt ch. 3" "Not requested,Requested" bitfld.long 0x14 2. " EXTINT[2] ,Interrupt request on external interrupt ch. 2" "Not requested,Requested" bitfld.long 0x14 1. " EXTINT[1] ,Interrupt request on external interrupt ch. 1" "Not requested,Requested" bitfld.long 0x14 0. " EXTINT[0] ,Interrupt request on external interrupt ch. 0" "Not requested,Requested" sif !cpuis("MB9BF121J") line.long 0x18 "IRQ05MON,IRQ05 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L") sif cpuis("MB9BF12?M")||cpuis("MB9BF32?M")||cpuis("MB9BF52?M") bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " else bitfld.long 0x18 23. " EXTINT[31] ,Interrupt request on external interrupt ch. 31" "Not requested,Requested" bitfld.long 0x18 22. " EXTINT[30] ,Interrupt request on external interrupt ch. 30" "Not requested,Requested" bitfld.long 0x18 21. " EXTINT[29] ,Interrupt request on external interrupt ch. 29" "Not requested,Requested" bitfld.long 0x18 20. " EXTINT[28] ,Interrupt request on external interrupt ch. 28" "Not requested,Requested" textline " " bitfld.long 0x18 19. " EXTINT[27] ,Interrupt request on external interrupt ch. 27" "Not requested,Requested" bitfld.long 0x18 18. " EXTINT[26] ,Interrupt request on external interrupt ch. 26" "Not requested,Requested" bitfld.long 0x18 17. " EXTINT[25] ,Interrupt request on external interrupt ch. 25" "Not requested,Requested" bitfld.long 0x18 16. " EXTINT[24] ,Interrupt request on external interrupt ch. 24" "Not requested,Requested" textline " " bitfld.long 0x18 15. " EXTINT[23] ,Interrupt request on external interrupt ch. 23" "Not requested,Requested" bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " endif endif sif !cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF52?K") sif cpuis("MB9BF12?L")||cpuis("MB9BF32?L")||cpuis("MB9BF52?L") bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " else bitfld.long 0x18 11. " EXTINT[19] ,Interrupt request on external interrupt ch. 19" "Not requested,Requested" bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " else bitfld.long 0x18 7. " EXTINT[15] ,Interrupt request on external interrupt ch. 15" "Not requested,Requested" bitfld.long 0x18 6. " EXTINT[14] ,Interrupt request on external interrupt ch. 14" "Not requested,Requested" bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " endif bitfld.long 0x18 3. " EXTINT[11] ,Interrupt request on external interrupt ch. 11" "Not requested,Requested" bitfld.long 0x18 2. " EXTINT[10] ,Interrupt request on external interrupt ch. 10" "Not requested,Requested" bitfld.long 0x18 1. " EXTINT[9] ,Interrupt request on external interrupt ch. 9" "Not requested,Requested" bitfld.long 0x18 0. " EXTINT[8] ,Interrupt request on external interrupt ch. 8" "Not requested,Requested" endif line.long 0x1C "IRQ06MON,IRQ06 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?") sif cpuis("MB9BF129?")||cpuis("MB9BF329?")||cpuis("MB9BF429?")||cpuis("MB9BF529?")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") bitfld.long 0x1C 13. " QUD1INT[5] ,PC match & RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 12. " QUD1INT[4] ,Interrupt request detected RC out of range on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 11. " QUD1INT[3] ,PC counter direction change interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " bitfld.long 0x1C 10. " QUD1INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 9. " QUD1INT[1] ,PC&RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 8. " QUD1INT[0] ,PC match interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " endif bitfld.long 0x1C 7. " QUD0INT[5] ,PC match & RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 6. " QUD0INT[4] ,Interrupt request detected RC out of range on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 5. " QUD0INT[3] ,PC counter direction change interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " bitfld.long 0x1C 4. " QUD0INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 3. " QUD0INT[1] ,PC&RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 2. " QUD0INT[0] ,PC match interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " endif bitfld.long 0x1C 1. " TIMINT[1] ,Dual timer TIMINT2 interrupt request" "Not requested,Requested" bitfld.long 0x1C 0. " TIMINT[0] ,Dual timer TIMINT1 interrupt request" "Not requested,Requested" line.long 0x20 "IRQ7MON,IRQ7 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" else bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" endif line.long (0x20+0x4) "IRQ8MON,IRQ8 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" else bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" endif line.long 0x28 "IRQ9MON,IRQ9 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" else bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" endif line.long (0x28+0x4) "IRQ10MON,IRQ10 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" else bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" endif line.long 0x30 "IRQ11MON,IRQ11 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " else bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" endif line.long (0x30+0x4) "IRQ12MON,IRQ12 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " else bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" endif line.long 0x38 "IRQ13MON,IRQ13 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " else bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" else bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" endif line.long (0x38+0x4) "IRQ14MON,IRQ14 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " else bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" else bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" endif line.long 0x40 "IRQ15MON,IRQ15 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x40 0. " MFSINT[0] ,Reception interrupt request on MFS channel 4" "Not requested,Requested" endif line.long (0x40+0x4) "IRQ16MON,IRQ16 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x40+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 4" "Not requested,Requested" bitfld.long (0x40+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 4" "Not requested,Requested" endif line.long 0x48 "IRQ17MON,IRQ17 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" else bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" endif line.long (0x48+0x4) "IRQ18MON,IRQ18 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" else bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" endif line.long 0x50 "IRQ19MON,IRQ19 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long 0x50 1. " MFSINT[1] ,Reception interrupt request on MFS channel 14" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x50 0. " MFSINT[0] ,Reception interrupt request on MFS channel 6" "Not requested,Requested" endif line.long (0x50+0x4) "IRQ20MON,IRQ20 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long (0x50+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 14" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x50+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 6" "Not requested,Requested" bitfld.long (0x50+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 6" "Not requested,Requested" endif line.long 0x58 "IRQ21MON,IRQ21 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long 0x58 1. " MFSINT[1] ,Reception interrupt request on MFS channel 15" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x58 0. " MFSINT[0] ,Reception interrupt request on MFS channel 7" "Not requested,Requested" endif line.long (0x58+0x4) "IRQ22MON,IRQ22 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long (0x58+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 15" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x58+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 7" "Not requested,Requested" bitfld.long (0x58+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 7" "Not requested,Requested" endif line.long 0x60 "IRQ23MON,IRQ23 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M")&&!cpuis("MB9AF15?M")&&!cpuis("MB9AF15?N")&&!cpuis("MB9AF15?R") bitfld.long 0x60 5. " PPGINT[5] ,Interrupt request on PPG ch. 12" "Not requested,Requested" bitfld.long 0x60 4. " PPGINT[4] ,Interrupt request on PPG ch. 10" "Not requested,Requested" bitfld.long 0x60 3. " PPGINT[3] ,Interrupt request on PPG ch. 8" "Not requested,Requested" bitfld.long 0x60 2. " PPGINT[2] ,Interrupt request on PPG ch. 4" "Not requested,Requested" textline " " endif bitfld.long 0x60 1. " PPGINT[1] ,Interrupt request on PPG ch. 2" "Not requested,Requested" bitfld.long 0x60 0. " PPGINT[0] ,Interrupt request on PPG ch. 0" "Not requested,Requested" line.long 0x64 "IRQ24MON,IRQ24 Batch Read Register" bitfld.long 0x64 5. " RTCINT ,RTC interrupt request" "Not requested,Requested" bitfld.long 0x64 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested" textline " " sif cpuis("MB9BF32*")||cpuis("MB9BF52*") bitfld.long 0x64 3. " UPLLINT ,Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation" "Not requested,Requested" textline " " endif bitfld.long 0x64 2. " MPLLINT ,Stabilization wait completion interrupt request for PLL oscillation" "Not requested,Requested" bitfld.long 0x64 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested" textline " " bitfld.long 0x64 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested" rgroup.long 0x78++0x03 line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit0 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit0 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit0 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit0 priority conversion interrupt request" "Not requested,Requested" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J") sif cpuis("MB9BF?28?")||cpuis("MB9BF?29?")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" else rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" rgroup.long 0x80++0x03 line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit2 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit2 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit2 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit2 priority conversion interrupt request" "Not requested,Requested" endif endif rgroup.long 0x84++0x03 line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register" bitfld.long 0x00 5. " FRT0INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " FRT0INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 3. " FRT0INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " FRT0INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " FRT0INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " FRT0INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x88++0x03 line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register" bitfld.long 0x00 3. " ICU0INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " ICU0INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " ICU0INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " ICU0INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x8C++0x03 line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register" bitfld.long 0x00 5. " OCU0INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " OCU0INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 3. " OCU0INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " OCU0INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " OCU0INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " OCU0INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x90++0x03 line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[14] ,IRQ0 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[13] ,IRQ1 interrupt request on the base timer ch. 6" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[12] ,IRQ0 interrupt request on the base timer ch. 6" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[11] ,IRQ1 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[10] ,IRQ0 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[9] ,IRQ1 interrupt request on the base timer ch. 4" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[8] ,IRQ0 interrupt request on the base timer ch. 4" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[7] ,IRQ1 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[6] ,IRQ0 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[5] ,IRQ1 interrupt request on the base timer ch. 2" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[4] ,IRQ0 interrupt request on the base timer ch. 2" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[3] ,IRQ1 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[2] ,IRQ0 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[1] ,IRQ1 interrupt request on the base timer ch. 0" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[0] ,IRQ0 interrupt request on the base timer ch. 0" "Not requested,Requested" sif cpuis("MB9AF421?")||cpuis("MB9BF42*")||cpuis("MB9BF52*") sif cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF428S")||cpuis("MB9BF428T")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") rgroup.long 0x94++0x03 line.long 0x00 "IRQ32MON,IRQ32 Batch Read Register" bitfld.long 0x00 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" else rgroup.long 0x94++0x03 line.long 0x00 "IRQ32MON,IRQ32 Batch Read Register" bitfld.long 0x00 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" rgroup.long 0x98++0x03 line.long 0x00 "IRQ33MON,IRQ33 Batch Read Register" bitfld.long 0x00 0. " CAN1INT ,Interrupt request of CAN ch.1" "Not requested,Requested" endif endif sif cpuis("MB9BF32*")||cpuis("MB9BF52*") rgroup.long 0x9C++0x07 line.long 0x00 "IRQ34MON,IRQ34 Batch Read Register" bitfld.long 0x00 4. " USB0INT[4] ,Endpoint 5 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 3. " USB0INT[3] ,Endpoint 4 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 2. " USB0INT[2] ,Endpoint 3 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 1. " USB0INT[1] ,Endpoint 2 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB0INT[0] ,Endpoint 1 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" line.long 0x04 "IRQ35MON,IRQ35 Batch Read Register" bitfld.long 0x04 5. " USB0INT[5] ,Status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 4. " USB0INT[4] ,Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 3. " USB0INT[3] ,Status (SPK) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 2. " USB0INT[2] ,Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB0INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 0. " USB0INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch. 0" "Not requested,Requested" endif sif cpuis("MB9AF128?")||cpuis("MB9AF129?")||cpuis("MB9AF328?")||cpuis("MB9AF329?")||cpuis("MB9AF428?")||cpuis("MB9AF429?")||cpuis("MB9BF52*")||cpuis("MB9AF15*") rgroup.long 0xA4++0x07 line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" textline " " endif ; sif !cpuis("MB9BF121J")&&!cpuis("MB9AF421*")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") ; rgroup.long 0xA4++0x07 ; line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" ; bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" ; textline " " ; sif cpuis("MB9BF32*")||cpuis("MB9BF52*") ; bitfld.long 0x00 4. " USB1INT[4] ,Interrupt request of USB ch.1 Endpoint5 DRQ" "Not requested,Requested" ; bitfld.long 0x00 3. " USB1INT[3] ,Interrupt request of USB ch.1 Endpoint4 DRQ" "Not requested,Requested" ; textline " " ; bitfld.long 0x00 2. " USB1INT[2] ,Interrupt request of USB ch.1 Endpoint3 DRQ" "Not requested,Requested" ; bitfld.long 0x00 1. " USB1INT[1] ,Interrupt request of USB ch.1 Endpoint2 DRQ" "Not requested,Requested" ; textline " " ; bitfld.long 0x00 0. " USB1INT[0] ,Interrupt request of USB ch.1 Endpoint1 DRQ" "Not requested,Requested" ; endif ; line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" ; bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" ; textline " " ; sif cpuis("MB9BF32*")||cpuis("MB9BF52*") ; bitfld.long 0x04 5. " USB1INT[5] ,Interrupt request of USB ch.1 status (SOFIRQ, CMPIRQ)" "Not requested,Requested" ; bitfld.long 0x04 4. " USB1INT[4] ,Interrupt request of USB ch.1 status (DIRQ, URIRQ, RWKIRQ, CNNIRQ)" "Not requested,Requested" ; textline " " ; bitfld.long 0x04 3. " USB1INT[3] ,Interrupt request of USB ch.1 status (SPK)" "Not requested,Requested" ; bitfld.long 0x04 2. " USB1INT[2] ,Interrupt request of USB ch.1 status (SUSP, SOF, BRST, CONF, WKUP)" "Not requested,Requested" ; textline " " ; bitfld.long 0x04 1. " USB1INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch.1" "Not requested,Requested" ; bitfld.long 0x04 0. " USB1INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch.1" "Not requested,Requested" ; endif ; endif rgroup.long 0xAC++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" else line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" endif rgroup.long 0xB0++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" else line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" endif rgroup.long 0xB4++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" endif rgroup.long 0xB8++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" else line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" endif rgroup.long 0xBC++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ42MON,IRQ42 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 4" "Not requested,Requested" endif rgroup.long 0xC0++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" else line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" endif rgroup.long 0xC4++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ44MON,IRQ44 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 6" "Not requested,Requested" endif rgroup.long 0xC8++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ45MON,IRQ45 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 7" "Not requested,Requested" endif sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") rgroup.long 0xCC++0x03 line.long 0x00 "IRQ46MON,IRQ46 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[15] ,IRQ0 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[14] ,IRQ1 interrupt request of base timer ch.14" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[14] ,IRQ0 interrupt request of base timer ch.14" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[13] ,IRQ1 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[13] ,IRQ0 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[12] ,IRQ1 interrupt request of base timer ch.12" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[12] ,IRQ0 interrupt request of base timer ch.12" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[11] ,IRQ1 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[11] ,IRQ0 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[10] ,IRQ1 interrupt request of base timer ch.10" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[10] ,IRQ0 interrupt request of base timer ch.10" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[9] ,IRQ1 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[9] ,IRQ0 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[8] ,IRQ1 interrupt request of base timer ch.8" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[8] ,IRQ0 interrupt request of base timer ch.8" "Not requested,Requested" endif rgroup.long 0xD0++0x03 line.long 0x00 "IRQ47MON,IRQ47 Batch Read Register" bitfld.long 0x00 11. " FLASHINT ,RDY/HANG interrupt request for flash" "Not requested,Requested" sif cpuis("MB9BF32*")||cpuis("MB9BF52*") group.byte 0x20F++0x3 line.byte 0x00 "ODDPKS,USB ch.0 Odd Packet Size DMA Enable Register" bitfld.byte 0x00 4. " ODDPKS4 ,DMA USB.EP5DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 3. " ODDPKS3 ,DMA USB.EP4DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 2. " ODDPKS2 ,DMA USB.EP3DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 1. " ODDPKS1 ,DMA USB.EP2DT transfer bit width converted" "Not converted,Converted" textline " " bitfld.byte 0x00 0. " ODDPKS0 ,DMA USB.EP1DT transfer bit width converted" "Not converted,Converted" endif rgroup.long 0x210++0x07 line.long 0x00 "RCINTSEL0,Interrupt Factor Selection Register0" hexmask.long.byte 0x00 24.--31. 1. " INTSEL3 ,Selects interrupt factor of the interrupt vector No.22" hexmask.long.byte 0x00 16.--23. 1. " INTSEL2 ,Selects interrupt factor of the interrupt vector No.21" hexmask.long.byte 0x00 8.--15. 1. " INTSEL1 ,Selects interrupt factor of the interrupt vector No.20" hexmask.long.byte 0x00 0.--7. 1. " INTSEL0 ,Selects interrupt factor of the interrupt vector No.19" line.long 0x04 "RCINTSEL0,Interrupt Factor Selection Register0" hexmask.long.byte 0x04 24.--31. 1. " INTSEL7 ,Selects interrupt factor of the interrupt vector No.26" hexmask.long.byte 0x04 16.--23. 1. " INTSEL6 ,Selects interrupt factor of the interrupt vector No.25" hexmask.long.byte 0x04 8.--15. 1. " INTSEL5 ,Selects interrupt factor of the interrupt vector No.24" hexmask.long.byte 0x04 0.--7. 1. " INTSEL4 ,Selects interrupt factor of the interrupt vector No.23" width 12. endif elif (cpuis("MB9BF?28?")||cpuis("MB9BF?29?")||cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF121J")||cpuis("MB9BF1?1K")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) width 10. group.long 0x0++0x03 line.long 0x0 "DRQSEL,DMA Request Selection Register" bitfld.long 0x0 31. " DRQSEL_[31] ,DMA Request for external interrupt ch.3" "CPU,DMAC" bitfld.long 0x0 30. " [30] ,DMA Request for external interrupt ch.2" "CPU,DMAC" bitfld.long 0x0 29. " [29] ,DMA Request for external interrupt ch.1" "CPU,DMAC" bitfld.long 0x0 28. " [28] ,DMA Request for external interrupt ch.0" "CPU,DMAC" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF52?K") bitfld.long 0x0 27. " [27] ,DMA Request for MFS ch.7 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 26. " [26] ,DMA Request for MFS ch.7 reception interrupt" "CPU,DMAC" bitfld.long 0x0 25. " [25] ,DMA Request for MFS ch.6 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 24. " [24] ,DMA Request for MFS ch.6 reception interrupt" "CPU,DMAC" endif textline " " sif cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L") bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" elif cpuis("MB9BF121J") bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" else bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 21. " [21] ,DMA Request for MFS ch.4 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 20. " [20] ,DMA Request for MFS ch.4 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" endif textline " " bitfld.long 0x0 15. " [15] ,DMA Request for MFS ch.1 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 14. " [14] ,DMA Request for MFS ch.1 reception interrupt" "CPU,DMAC" bitfld.long 0x0 13. " [13] ,DMA Request for MFS ch.0 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 12. " [12] ,DMA Request for MFS ch.0 reception interrupt" "CPU,DMAC" bitfld.long 0x0 11. " [11] ,DMA Request for base timer ch.6 interrupt" "CPU,DMAC" bitfld.long 0x0 10. " [10] ,DMA Request for base timer ch.4 interrupt" "CPU,DMAC" bitfld.long 0x0 9. " [9] ,DMA Request for base timer ch.2 interrupt" "CPU,DMAC" bitfld.long 0x0 8. " [8] ,DMA Request for base timer ch.0 interrupt" "CPU,DMAC" textline " " sif cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF121J") bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" elif cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" else bitfld.long 0x0 7. " [7] ,DMA Request for ADC unit2 interrupt" "CPU,DMAC" bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" endif textline " " sif cpuis("MB9BF328?")||cpuis("MB9BF329?")||cpuis("MB9BF528?")||cpuis("MB9BF529?")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") bitfld.long 0x0 4. " [4] ,DMA Request for USB ch.0 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 3. " [3] ,DMA Request for USB ch.0 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 2. " [2] ,DMA Request for USB ch.0 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 1. " [1] ,DMA Request for USB ch.0 EP2 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 0. " [0] ,DMA Request for USB ch.0 EP1 DRQ interrupt" "CPU,DMAC" endif textline " " rgroup.long 0x10++0x67 line.long 0x0 "EXC02MON,EXC02 Batch Read Register" bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " NMI ,External NMIX pin interrupt request" "Not requested,Requested" line.long 0x4 "IRQ00MON,IRQ00 Batch Read Register" bitfld.long 0x04 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested" line.long 0x8 "IRQ01MON,IRQ01 Batch Read Register" bitfld.long 0x08 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested" line.long 0xC "IRQ02MON,IRQ02 Batch Read Register" bitfld.long 0x0C 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested" line.long 0x10 "IRQ03MON,IRQ03 Batch Read Register" bitfld.long 0x10 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " WAVE0INT[2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " WAVE0INT[1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " WAVE0INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ04MON,IRQ04 Batch Read Register" bitfld.long 0x14 7. " EXTINT[7] ,Interrupt request on external interrupt ch. 7" "Not requested,Requested" bitfld.long 0x14 6. " EXTINT[6] ,Interrupt request on external interrupt ch. 6" "Not requested,Requested" bitfld.long 0x14 5. " EXTINT[5] ,Interrupt request on external interrupt ch. 5" "Not requested,Requested" bitfld.long 0x14 4. " EXTINT[4] ,Interrupt request on external interrupt ch. 4" "Not requested,Requested" textline " " bitfld.long 0x14 3. " EXTINT[3] ,Interrupt request on external interrupt ch. 3" "Not requested,Requested" bitfld.long 0x14 2. " EXTINT[2] ,Interrupt request on external interrupt ch. 2" "Not requested,Requested" bitfld.long 0x14 1. " EXTINT[1] ,Interrupt request on external interrupt ch. 1" "Not requested,Requested" bitfld.long 0x14 0. " EXTINT[0] ,Interrupt request on external interrupt ch. 0" "Not requested,Requested" sif !cpuis("MB9BF121J") line.long 0x18 "IRQ05MON,IRQ05 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L") sif cpuis("MB9BF12?M")||cpuis("MB9BF32?M")||cpuis("MB9BF52?M") bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " else bitfld.long 0x18 23. " EXTINT[31] ,Interrupt request on external interrupt ch. 31" "Not requested,Requested" bitfld.long 0x18 22. " EXTINT[30] ,Interrupt request on external interrupt ch. 30" "Not requested,Requested" bitfld.long 0x18 21. " EXTINT[29] ,Interrupt request on external interrupt ch. 29" "Not requested,Requested" bitfld.long 0x18 20. " EXTINT[28] ,Interrupt request on external interrupt ch. 28" "Not requested,Requested" textline " " bitfld.long 0x18 19. " EXTINT[27] ,Interrupt request on external interrupt ch. 27" "Not requested,Requested" bitfld.long 0x18 18. " EXTINT[26] ,Interrupt request on external interrupt ch. 26" "Not requested,Requested" bitfld.long 0x18 17. " EXTINT[25] ,Interrupt request on external interrupt ch. 25" "Not requested,Requested" bitfld.long 0x18 16. " EXTINT[24] ,Interrupt request on external interrupt ch. 24" "Not requested,Requested" textline " " bitfld.long 0x18 15. " EXTINT[23] ,Interrupt request on external interrupt ch. 23" "Not requested,Requested" bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " endif endif sif !cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF52?K") sif cpuis("MB9BF12?L")||cpuis("MB9BF32?L")||cpuis("MB9BF52?L") bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " else bitfld.long 0x18 11. " EXTINT[19] ,Interrupt request on external interrupt ch. 19" "Not requested,Requested" bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " else bitfld.long 0x18 7. " EXTINT[15] ,Interrupt request on external interrupt ch. 15" "Not requested,Requested" bitfld.long 0x18 6. " EXTINT[14] ,Interrupt request on external interrupt ch. 14" "Not requested,Requested" bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " endif bitfld.long 0x18 3. " EXTINT[11] ,Interrupt request on external interrupt ch. 11" "Not requested,Requested" bitfld.long 0x18 2. " EXTINT[10] ,Interrupt request on external interrupt ch. 10" "Not requested,Requested" bitfld.long 0x18 1. " EXTINT[9] ,Interrupt request on external interrupt ch. 9" "Not requested,Requested" bitfld.long 0x18 0. " EXTINT[8] ,Interrupt request on external interrupt ch. 8" "Not requested,Requested" endif line.long 0x1C "IRQ06MON,IRQ06 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?") sif cpuis("MB9BF129?")||cpuis("MB9BF329?")||cpuis("MB9BF429?")||cpuis("MB9BF529?")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") bitfld.long 0x1C 13. " QUD1INT[5] ,PC match & RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 12. " QUD1INT[4] ,Interrupt request detected RC out of range on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 11. " QUD1INT[3] ,PC counter direction change interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " bitfld.long 0x1C 10. " QUD1INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 9. " QUD1INT[1] ,PC&RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 8. " QUD1INT[0] ,PC match interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " endif bitfld.long 0x1C 7. " QUD0INT[5] ,PC match & RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 6. " QUD0INT[4] ,Interrupt request detected RC out of range on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 5. " QUD0INT[3] ,PC counter direction change interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " bitfld.long 0x1C 4. " QUD0INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 3. " QUD0INT[1] ,PC&RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 2. " QUD0INT[0] ,PC match interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " endif bitfld.long 0x1C 1. " TIMINT[1] ,Dual timer TIMINT2 interrupt request" "Not requested,Requested" bitfld.long 0x1C 0. " TIMINT[0] ,Dual timer TIMINT1 interrupt request" "Not requested,Requested" line.long 0x20 "IRQ7MON,IRQ7 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" else bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" endif line.long (0x20+0x4) "IRQ8MON,IRQ8 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" else bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" endif line.long 0x28 "IRQ9MON,IRQ9 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" else bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" endif line.long (0x28+0x4) "IRQ10MON,IRQ10 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" else bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" endif line.long 0x30 "IRQ11MON,IRQ11 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " else bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" endif line.long (0x30+0x4) "IRQ12MON,IRQ12 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " else bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" endif line.long 0x38 "IRQ13MON,IRQ13 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " else bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" else bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" endif line.long (0x38+0x4) "IRQ14MON,IRQ14 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " else bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" else bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" endif line.long 0x40 "IRQ15MON,IRQ15 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x40 0. " MFSINT[0] ,Reception interrupt request on MFS channel 4" "Not requested,Requested" endif line.long (0x40+0x4) "IRQ16MON,IRQ16 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x40+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 4" "Not requested,Requested" bitfld.long (0x40+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 4" "Not requested,Requested" endif line.long 0x48 "IRQ17MON,IRQ17 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" else bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" endif line.long (0x48+0x4) "IRQ18MON,IRQ18 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" textline " " elif cpuis("MB9AF15?M") else bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" else bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" endif line.long 0x50 "IRQ19MON,IRQ19 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long 0x50 1. " MFSINT[1] ,Reception interrupt request on MFS channel 14" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x50 0. " MFSINT[0] ,Reception interrupt request on MFS channel 6" "Not requested,Requested" endif line.long (0x50+0x4) "IRQ20MON,IRQ20 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long (0x50+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 14" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x50+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 6" "Not requested,Requested" bitfld.long (0x50+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 6" "Not requested,Requested" endif line.long 0x58 "IRQ21MON,IRQ21 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long 0x58 1. " MFSINT[1] ,Reception interrupt request on MFS channel 15" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long 0x58 0. " MFSINT[0] ,Reception interrupt request on MFS channel 7" "Not requested,Requested" endif line.long (0x58+0x4) "IRQ22MON,IRQ22 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") sif cpuis("MB9AF15?N") elif cpuis("MB9AF15?M") else bitfld.long (0x58+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 15" "Not requested,Requested" textline " " endif endif sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else bitfld.long (0x58+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 7" "Not requested,Requested" bitfld.long (0x58+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 7" "Not requested,Requested" endif line.long 0x60 "IRQ23MON,IRQ23 Batch Read Register" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M")&&!cpuis("MB9AF15?M")&&!cpuis("MB9AF15?N")&&!cpuis("MB9AF15?R") bitfld.long 0x60 5. " PPGINT[5] ,Interrupt request on PPG ch. 12" "Not requested,Requested" bitfld.long 0x60 4. " PPGINT[4] ,Interrupt request on PPG ch. 10" "Not requested,Requested" bitfld.long 0x60 3. " PPGINT[3] ,Interrupt request on PPG ch. 8" "Not requested,Requested" bitfld.long 0x60 2. " PPGINT[2] ,Interrupt request on PPG ch. 4" "Not requested,Requested" textline " " endif bitfld.long 0x60 1. " PPGINT[1] ,Interrupt request on PPG ch. 2" "Not requested,Requested" bitfld.long 0x60 0. " PPGINT[0] ,Interrupt request on PPG ch. 0" "Not requested,Requested" line.long 0x64 "IRQ24MON,IRQ24 Batch Read Register" bitfld.long 0x64 5. " RTCINT ,RTC interrupt request" "Not requested,Requested" bitfld.long 0x64 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested" textline " " sif cpuis("MB9BF32*")||cpuis("MB9BF52*") bitfld.long 0x64 3. " UPLLINT ,Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation" "Not requested,Requested" textline " " endif bitfld.long 0x64 2. " MPLLINT ,Stabilization wait completion interrupt request for PLL oscillation" "Not requested,Requested" bitfld.long 0x64 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested" textline " " bitfld.long 0x64 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested" rgroup.long 0x78++0x03 line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit0 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit0 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit0 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit0 priority conversion interrupt request" "Not requested,Requested" sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J") sif cpuis("MB9BF?28?")||cpuis("MB9BF?29?")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R") rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" else rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" rgroup.long 0x80++0x03 line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit2 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit2 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit2 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit2 priority conversion interrupt request" "Not requested,Requested" endif endif rgroup.long 0x84++0x03 line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register" bitfld.long 0x00 5. " FRT0INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " FRT0INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 3. " FRT0INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " FRT0INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " FRT0INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " FRT0INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x88++0x03 line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register" bitfld.long 0x00 3. " ICU0INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " ICU0INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " ICU0INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " ICU0INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x8C++0x03 line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register" bitfld.long 0x00 5. " OCU0INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " OCU0INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 3. " OCU0INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " OCU0INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " OCU0INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " OCU0INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x90++0x03 line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[14] ,IRQ0 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[13] ,IRQ1 interrupt request on the base timer ch. 6" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[12] ,IRQ0 interrupt request on the base timer ch. 6" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[11] ,IRQ1 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[10] ,IRQ0 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[9] ,IRQ1 interrupt request on the base timer ch. 4" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[8] ,IRQ0 interrupt request on the base timer ch. 4" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[7] ,IRQ1 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[6] ,IRQ0 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[5] ,IRQ1 interrupt request on the base timer ch. 2" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[4] ,IRQ0 interrupt request on the base timer ch. 2" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[3] ,IRQ1 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[2] ,IRQ0 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[1] ,IRQ1 interrupt request on the base timer ch. 0" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[0] ,IRQ0 interrupt request on the base timer ch. 0" "Not requested,Requested" sif cpuis("MB9AF421?")||cpuis("MB9BF42*")||cpuis("MB9BF52*") sif cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9BF428S")||cpuis("MB9BF428T")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") rgroup.long 0x94++0x03 line.long 0x00 "IRQ32MON,IRQ32 Batch Read Register" bitfld.long 0x00 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" else rgroup.long 0x94++0x03 line.long 0x00 "IRQ32MON,IRQ32 Batch Read Register" bitfld.long 0x00 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" rgroup.long 0x98++0x03 line.long 0x00 "IRQ33MON,IRQ33 Batch Read Register" bitfld.long 0x00 0. " CAN1INT ,Interrupt request of CAN ch.1" "Not requested,Requested" endif endif sif cpuis("MB9BF32*")||cpuis("MB9BF52*") rgroup.long 0x9C++0x07 line.long 0x00 "IRQ34MON,IRQ34 Batch Read Register" bitfld.long 0x00 4. " USB0INT[4] ,Endpoint 5 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 3. " USB0INT[3] ,Endpoint 4 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 2. " USB0INT[2] ,Endpoint 3 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 1. " USB0INT[1] ,Endpoint 2 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB0INT[0] ,Endpoint 1 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" line.long 0x04 "IRQ35MON,IRQ35 Batch Read Register" bitfld.long 0x04 5. " USB0INT[5] ,Status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 4. " USB0INT[4] ,Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 3. " USB0INT[3] ,Status (SPK) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 2. " USB0INT[2] ,Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB0INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 0. " USB0INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch. 0" "Not requested,Requested" endif sif cpuis("MB9AF128?")||cpuis("MB9AF129?")||cpuis("MB9AF328?")||cpuis("MB9AF329?")||cpuis("MB9AF428?")||cpuis("MB9AF429?")||cpuis("MB9BF52*")||cpuis("MB9AF15*") rgroup.long 0xA4++0x07 line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" textline " " endif ; sif !cpuis("MB9BF121J")&&!cpuis("MB9AF421*")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") ; rgroup.long 0xA4++0x07 ; line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" ; bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" ; textline " " ; sif cpuis("MB9BF32*")||cpuis("MB9BF52*") ; bitfld.long 0x00 4. " USB1INT[4] ,Interrupt request of USB ch.1 Endpoint5 DRQ" "Not requested,Requested" ; bitfld.long 0x00 3. " USB1INT[3] ,Interrupt request of USB ch.1 Endpoint4 DRQ" "Not requested,Requested" ; textline " " ; bitfld.long 0x00 2. " USB1INT[2] ,Interrupt request of USB ch.1 Endpoint3 DRQ" "Not requested,Requested" ; bitfld.long 0x00 1. " USB1INT[1] ,Interrupt request of USB ch.1 Endpoint2 DRQ" "Not requested,Requested" ; textline " " ; bitfld.long 0x00 0. " USB1INT[0] ,Interrupt request of USB ch.1 Endpoint1 DRQ" "Not requested,Requested" ; endif ; line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" ; bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" ; textline " " ; sif cpuis("MB9BF32*")||cpuis("MB9BF52*") ; bitfld.long 0x04 5. " USB1INT[5] ,Interrupt request of USB ch.1 status (SOFIRQ, CMPIRQ)" "Not requested,Requested" ; bitfld.long 0x04 4. " USB1INT[4] ,Interrupt request of USB ch.1 status (DIRQ, URIRQ, RWKIRQ, CNNIRQ)" "Not requested,Requested" ; textline " " ; bitfld.long 0x04 3. " USB1INT[3] ,Interrupt request of USB ch.1 status (SPK)" "Not requested,Requested" ; bitfld.long 0x04 2. " USB1INT[2] ,Interrupt request of USB ch.1 status (SUSP, SOF, BRST, CONF, WKUP)" "Not requested,Requested" ; textline " " ; bitfld.long 0x04 1. " USB1INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch.1" "Not requested,Requested" ; bitfld.long 0x04 0. " USB1INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch.1" "Not requested,Requested" ; endif ; endif rgroup.long 0xAC++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" else line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" endif rgroup.long 0xB0++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" else line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" endif rgroup.long 0xB4++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" endif rgroup.long 0xB8++0x03 sif cpuis("MB9BF121J") line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" else line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" endif rgroup.long 0xBC++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ42MON,IRQ42 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 4" "Not requested,Requested" endif rgroup.long 0xC0++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" else line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" endif rgroup.long 0xC4++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ44MON,IRQ44 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 6" "Not requested,Requested" endif rgroup.long 0xC8++0x03 sif cpuis("MB9BF121J") elif cpuis("MB9BF12?K")||cpuis("MB9BF32?K")||cpuis("MB9BF52?K") else line.long 0x00 "IRQ45MON,IRQ45 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 7" "Not requested,Requested" endif sif !cpuis("MB9AF421?")&&!cpuis("MB9AF121?")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF12?L")&&!cpuis("MB9BF12?M")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF32?L")&&!cpuis("MB9BF32?M")&&!cpuis("MB9BF52?K")&&!cpuis("MB9BF52?L")&&!cpuis("MB9BF52?M") rgroup.long 0xCC++0x03 line.long 0x00 "IRQ46MON,IRQ46 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[15] ,IRQ0 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[14] ,IRQ1 interrupt request of base timer ch.14" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[14] ,IRQ0 interrupt request of base timer ch.14" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[13] ,IRQ1 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[13] ,IRQ0 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[12] ,IRQ1 interrupt request of base timer ch.12" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[12] ,IRQ0 interrupt request of base timer ch.12" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[11] ,IRQ1 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[11] ,IRQ0 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[10] ,IRQ1 interrupt request of base timer ch.10" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[10] ,IRQ0 interrupt request of base timer ch.10" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[9] ,IRQ1 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[9] ,IRQ0 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[8] ,IRQ1 interrupt request of base timer ch.8" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[8] ,IRQ0 interrupt request of base timer ch.8" "Not requested,Requested" endif rgroup.long 0xD0++0x03 line.long 0x00 "IRQ47MON,IRQ47 Batch Read Register" bitfld.long 0x00 11. " FLASHINT ,RDY/HANG interrupt request for flash" "Not requested,Requested" sif cpuis("MB9BF32*")||cpuis("MB9BF52*") group.byte 0x20F++0x3 line.byte 0x00 "ODDPKS,USB ch.0 Odd Packet Size DMA Enable Register" bitfld.byte 0x00 4. " ODDPKS4 ,DMA USB.EP5DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 3. " ODDPKS3 ,DMA USB.EP4DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 2. " ODDPKS2 ,DMA USB.EP3DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 1. " ODDPKS1 ,DMA USB.EP2DT transfer bit width converted" "Not converted,Converted" textline " " bitfld.byte 0x00 0. " ODDPKS0 ,DMA USB.EP1DT transfer bit width converted" "Not converted,Converted" endif width 0x0b else width 10. group.long 0x0++0x03 line.long 0x0 "DRQSEL,DMA Request Selection Register" bitfld.long 0x0 31. " DRQSEL_[31] ,DMA Request for external interrupt ch.3" "CPU,DMAC" bitfld.long 0x0 30. " [30] ,DMA Request for external interrupt ch.2" "CPU,DMAC" bitfld.long 0x0 29. " [29] ,DMA Request for external interrupt ch.1" "CPU,DMAC" bitfld.long 0x0 28. " [28] ,DMA Request for external interrupt ch.0" "CPU,DMAC" bitfld.long 0x0 27. " [27] ,DMA Request for MFS ch.7 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 26. " [26] ,DMA Request for MFS ch.7 reception interrupt" "CPU,DMAC" bitfld.long 0x0 25. " [25] ,DMA Request for MFS ch.6 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 24. " [24] ,DMA Request for MFS ch.6 reception interrupt" "CPU,DMAC" textline " " bitfld.long 0x0 23. " [23] ,DMA Request for MFS ch.5 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 22. " [22] ,DMA Request for MFS ch.5 reception interrupt" "CPU,DMAC" bitfld.long 0x0 21. " [21] ,DMA Request for MFS ch.4 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 20. " [20] ,DMA Request for MFS ch.4 reception interrupt" "CPU,DMAC" bitfld.long 0x0 19. " [19] ,DMA Request for MFS ch.3 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 18. " [18] ,DMA Request for MFS ch.3 reception interrupt" "CPU,DMAC" bitfld.long 0x0 17. " [17] ,DMA Request for MFS ch.2 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 16. " [16] ,DMA Request for MFS ch.2 reception interrupt" "CPU,DMAC" textline " " bitfld.long 0x0 15. " [15] ,DMA Request for MFS ch.1 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 14. " [14] ,DMA Request for MFS ch.1 reception interrupt" "CPU,DMAC" bitfld.long 0x0 13. " [13] ,DMA Request for MFS ch.0 transmission interrupt" "CPU,DMAC" bitfld.long 0x0 12. " [12] ,DMA Request for MFS ch.0 reception interrupt" "CPU,DMAC" bitfld.long 0x0 11. " [11] ,DMA Request for base timer ch.6 interrupt" "CPU,DMAC" bitfld.long 0x0 10. " [10] ,DMA Request for base timer ch.4 interrupt" "CPU,DMAC" bitfld.long 0x0 9. " [9] ,DMA Request for base timer ch.2 interrupt" "CPU,DMAC" bitfld.long 0x0 8. " [8] ,DMA Request for base timer ch.0 interrupt" "CPU,DMAC" textline " " bitfld.long 0x0 7. " [7] ,DMA Request for ADC unit2 interrupt" "CPU,DMAC" bitfld.long 0x0 6. " [6] ,DMA Request for ADC unit1 interrupt" "CPU,DMAC" bitfld.long 0x0 5. " [5] ,DMA Request for ADC unit0 interrupt" "CPU,DMAC" sif (!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x0 4. " [4] ,DMA Request for USB ch.0 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 3. " [3] ,DMA Request for USB ch.0 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 2. " [2] ,DMA Request for USB ch.0 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 1. " [1] ,DMA Request for USB ch.0 EP2 DRQ interrupt" "CPU,DMAC" bitfld.long 0x0 0. " [0] ,DMA Request for USB ch.0 EP1 DRQ interrupt" "CPU,DMAC" endif sif (cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF11?K")||cpuis("MB9AF31?K")||cpuis("MB9AF?4*")) group.long 0x08++0x03 line.long 0x00 "IRQCMODER,Interrupt Factor Vector Relocate Setting Register" bitfld.long 0x00 0. " IRQCMODER ,Relocate Exception and Interrupt Factor" "Not relocated,Relocated" endif sif (cpuis("MB9BFD16S")||cpuis("MB9BFD16T")||cpuis("MB9BFD17S")||cpuis("MB9BFD17T")||cpuis("MB9BFD18S")||cpuis("MB9BFD18T")||cpuis("MB9BF61?T")||cpuis("MB9BF51?T")||cpuis("MB9BF41?T")||cpuis("MB9BF31?T")||cpuis("MB9BF21?T")||cpuis("MB9BF11?T")||cpuis("MB9BF61?S")||cpuis("MB9BF51?S")||cpuis("MB9BF41?S")||cpuis("MB9BF31?S")||cpuis("MB9BF21?S")||cpuis("MB9BF11?S")) group.long 0x200++0x7 line.long 0x0 "DRQSEL1,DMA Request Select Register 1" bitfld.long 0x00 4. " DRQSEL1[4] ,DMA Request for USB ch.1 EP5 DRQ interrupt" "CPU,DMAC" bitfld.long 0x00 3. " [3] ,DMA Request for USB ch.1 EP4 DRQ interrupt" "CPU,DMAC" bitfld.long 0x00 2. " [2] ,DMA Request for USB ch.1 EP3 DRQ interrupt" "CPU,DMAC" bitfld.long 0x00 1. " [1] ,DMA Request for USB ch.1 EP2 DRQ interrupt" "CPU,DMAC" textline " " bitfld.long 0x00 0. " [0] ,DMA Request for USB ch.1 EP1 DRQ interrupt" "CPU,DMAC" line.long 0x4 "DQESEL,DMA Request Extended Selection Register" bitfld.long 0x04 28.--31. " ESEL31 ,IDREQ [31] DMA transfer request signal input source select" "External ch.3,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 24.--27. " ESEL30 ,IDREQ [30] DMA transfer request signal input source select" "External ch.2,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 20.--23. " ESEL27 ,IDREQ [27] DMA transfer request signal input source select" "External ch.1,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 16.--19. " ESEL26 ,IDREQ [26] DMA transfer request signal input source select" "MFS ch.7 receive,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." textline " " bitfld.long 0x04 12.--15. " ESEL25 ,IDREQ [25] DMA transfer request signal input source select" "MFS ch.7 send,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 8.--11. " ESEL24 ,IDREQ [24] DMA transfer request signal input source select" "MFS ch.6 receive,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 4.--7. " ESEL11 ,IDREQ [11] DMA transfer request signal input source select" "Base timer ch.6,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." bitfld.long 0x04 0.--3. " ESEL10 ,IDREQ [10] DMA transfer request signal input source select" "Base timer ch.4,USB ch.1 EP1,USB ch.1 EP2,USB ch.1 EP3,USB ch.1 EP4,USB ch.1 EP5,?..." endif rgroup.long 0x10++0x67 line.long 0x0 "EXC02MON,EXC02 Batch Read Register" bitfld.long 0x00 1. " HWINT ,Hardware watchdog timer interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " NMI ,External NMIX pin interrupt request" "Not requested,Requested" line.long 0x4 "IRQ00MON,IRQ00 Batch Read Register" bitfld.long 0x04 0. " FCSINT ,Anomalous frequency detection by CSV interrupt request" "Not requested,Requested" line.long 0x8 "IRQ01MON,IRQ01 Batch Read Register" bitfld.long 0x08 0. " SWWDTINT ,Software watchdog timer interrupt request" "Not requested,Requested" line.long 0xC "IRQ02MON,IRQ02 Batch Read Register" bitfld.long 0x0C 0. " LVDINT ,Low voltage detection (LVD) interrupt request" "Not requested,Requested" line.long 0x10 "IRQ03MON,IRQ03 Batch Read Register" sif (cpuis("MB9BFD16S")||cpuis("MB9BFD16T")||cpuis("MB9BFD17S")||cpuis("MB9BFD17T")||cpuis("MB9BFD18S")||cpuis("MB9BFD18T")) bitfld.long 0x10 11. " WAVE2INT[3] ,WFG timer 54 interrupt request in MFT unit 2" "Not requested,Requested" bitfld.long 0x10 10. " WAVE2INT[2] ,WFG timer 32 interrupt request in MFT unit 2" "Not requested,Requested" bitfld.long 0x10 9. " WAVE2INT[1] ,WFG timer 10 interrupt request in MFT unit 2" "Not requested,Requested" bitfld.long 0x10 8. " WAVE2INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 2" "Not requested,Requested" textline " " endif bitfld.long 0x10 7. " WAVE1INT[3] ,WFG timer 54 interrupt request in MFT unit 1" "Not requested,Requested" bitfld.long 0x10 6. " WAVE1INT[2] ,WFG timer 32 interrupt request in MFT unit 1" "Not requested,Requested" bitfld.long 0x10 5. " WAVE1INT[1] ,WFG timer 10 interrupt request in MFT unit 1" "Not requested,Requested" bitfld.long 0x10 4. " WAVE1INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 1" "Not requested,Requested" textline " " bitfld.long 0x10 3. " WAVE0INT[3] ,WFG timer 54 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 2. " WAVE0INT[2] ,WFG timer 32 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 1. " WAVE0INT[1] ,WFG timer 10 interrupt request in MFT unit 0" "Not requested,Requested" bitfld.long 0x10 0. " WAVE0INT[0] ,DTIF (motor emergency stop) interrupt request in MFT unit 0" "Not requested,Requested" line.long 0x14 "IRQ04MON,IRQ04 Batch Read Register" sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x14 7. " EXTINT[7] ,Interrupt request on external interrupt ch. 7" "Not requested,Requested" textline " " endif bitfld.long 0x14 6. " EXTINT[6] ,Interrupt request on external interrupt ch. 6" "Not requested,Requested" sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) textline " " bitfld.long 0x14 5. " EXTINT[5] ,Interrupt request on external interrupt ch. 5" "Not requested,Requested" bitfld.long 0x14 4. " EXTINT[4] ,Interrupt request on external interrupt ch. 4" "Not requested,Requested" textline " " endif bitfld.long 0x14 3. " EXTINT[3] ,Interrupt request on external interrupt ch. 3" "Not requested,Requested" bitfld.long 0x14 2. " EXTINT[2] ,Interrupt request on external interrupt ch. 2" "Not requested,Requested" bitfld.long 0x14 1. " EXTINT[1] ,Interrupt request on external interrupt ch. 1" "Not requested,Requested" bitfld.long 0x14 0. " EXTINT[0] ,Interrupt request on external interrupt ch. 0" "Not requested,Requested" line.long 0x18 "IRQ05MON,IRQ05 Batch Read Register" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x18 23. " EXTINT[31] ,Interrupt request on external interrupt ch. 31" "Not requested,Requested" bitfld.long 0x18 22. " EXTINT[30] ,Interrupt request on external interrupt ch. 30" "Not requested,Requested" bitfld.long 0x18 21. " EXTINT[29] ,Interrupt request on external interrupt ch. 29" "Not requested,Requested" bitfld.long 0x18 20. " EXTINT[28] ,Interrupt request on external interrupt ch. 28" "Not requested,Requested" textline " " bitfld.long 0x18 19. " EXTINT[27] ,Interrupt request on external interrupt ch. 27" "Not requested,Requested" bitfld.long 0x18 18. " EXTINT[26] ,Interrupt request on external interrupt ch. 26" "Not requested,Requested" bitfld.long 0x18 17. " EXTINT[25] ,Interrupt request on external interrupt ch. 25" "Not requested,Requested" bitfld.long 0x18 16. " EXTINT[24] ,Interrupt request on external interrupt ch. 24" "Not requested,Requested" textline " " bitfld.long 0x18 15. " EXTINT[23] ,Interrupt request on external interrupt ch. 23" "Not requested,Requested" bitfld.long 0x18 14. " EXTINT[22] ,Interrupt request on external interrupt ch. 22" "Not requested,Requested" bitfld.long 0x18 13. " EXTINT[21] ,Interrupt request on external interrupt ch. 21" "Not requested,Requested" bitfld.long 0x18 12. " EXTINT[20] ,Interrupt request on external interrupt ch. 20" "Not requested,Requested" textline " " bitfld.long 0x18 11. " EXTINT[19] ,Interrupt request on external interrupt ch. 19" "Not requested,Requested" bitfld.long 0x18 10. " EXTINT[18] ,Interrupt request on external interrupt ch. 18" "Not requested,Requested" bitfld.long 0x18 9. " EXTINT[17] ,Interrupt request on external interrupt ch. 17" "Not requested,Requested" bitfld.long 0x18 8. " EXTINT[16] ,Interrupt request on external interrupt ch. 16" "Not requested,Requested" textline " " endif bitfld.long 0x18 7. " EXTINT[15] ,Interrupt request on external interrupt ch. 15" "Not requested,Requested" sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) textline " " bitfld.long 0x18 6. " EXTINT[14] ,Interrupt request on external interrupt ch. 14" "Not requested,Requested" textline " " endif sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x18 5. " EXTINT[13] ,Interrupt request on external interrupt ch. 13" "Not requested,Requested" bitfld.long 0x18 4. " EXTINT[12] ,Interrupt request on external interrupt ch. 12" "Not requested,Requested" textline " " bitfld.long 0x18 3. " EXTINT[11] ,Interrupt request on external interrupt ch. 11" "Not requested,Requested" bitfld.long 0x18 2. " EXTINT[10] ,Interrupt request on external interrupt ch. 10" "Not requested,Requested" bitfld.long 0x18 1. " EXTINT[9] ,Interrupt request on external interrupt ch. 9" "Not requested,Requested" textline " " endif sif (cpuis("MB9*N")||cpuis("MB9*R")||cpuis("MB9*NA")||cpuis("MB9*RA")||cpuis("MB9*M")||cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x18 0. " EXTINT[8] ,Interrupt request on external interrupt ch. 8" "Not requested,Requested" endif line.long 0x1C "IRQ06MON,IRQ06 Batch Read Register" sif (!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF14?L")&&!cpuis("MB9AF14?M")&&!cpuis("MB9AF14?N")&&!cpuis("MB9AF34?L")&&!cpuis("MB9AF34?M")&&!cpuis("MB9AF34?N")&&!cpuis("MB9AF14?M")&&!cpuis("MB9AF?4?L")&&!cpuis("MB9AF?4?M")&&!cpuis("MB9AF?4?N")) sif (cpuis("MB9B*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x1C 19. " QUD2INT[5] ,PC match & RC match interrupt request on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 18. " QUD2INT[4] ,Interrupt request detected RC out of range on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 17. " QUD2INT[3] ,PC counter direction change interrupt request on QPRC ch. 2" "Not requested,Requested" textline " " bitfld.long 0x1C 16. " QUD2INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 15. " QUD2INT[1] ,PC&RC match interrupt request on QPRC ch. 2" "Not requested,Requested" bitfld.long 0x1C 14. " QUD2INT[0] ,PC match interrupt request on QPRC ch. 2" "Not requested,Requested" textline " " endif sif (cpu()!="MB9AF111K"&&cpu()!="MB9AF112K"&&cpu()!="MB9AF132K"&&cpu()!="MB9AF311K"&&cpu()!="MB9AF312K") bitfld.long 0x1C 13. " QUD1INT[5] ,PC match & RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 12. " QUD1INT[4] ,Interrupt request detected RC out of range on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 11. " QUD1INT[3] ,PC counter direction change interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " bitfld.long 0x1C 10. " QUD1INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 9. " QUD1INT[1] ,PC&RC match interrupt request on QPRC ch. 1" "Not requested,Requested" bitfld.long 0x1C 8. " QUD1INT[0] ,PC match interrupt request on QPRC ch. 1" "Not requested,Requested" textline " " endif bitfld.long 0x1C 7. " QUD0INT[5] ,PC match & RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 6. " QUD0INT[4] ,Interrupt request detected RC out of range on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 5. " QUD0INT[3] ,PC counter direction change interrupt request on QPRC ch. 0" "Not requested,Requested" textline " " bitfld.long 0x1C 4. " QUD0INT[2] ,Overflow/underflow/zero index interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 3. " QUD0INT[1] ,PC&RC match interrupt request on QPRC ch. 0" "Not requested,Requested" bitfld.long 0x1C 2. " QUD0INT[0] ,PC match interrupt request on QPRC ch. 0" "Not requested,Requested" endif textline " " bitfld.long 0x1C 1. " TIMINT[1] ,Dual timer TIMINT2 interrupt request" "Not requested,Requested" bitfld.long 0x1C 0. " TIMINT[0] ,Dual timer TIMINT1 interrupt request" "Not requested,Requested" line.long 0x20 "IRQ7MON,IRQ7 Batch Read Register" bitfld.long 0x20 1. " MFSINT[1] ,Reception interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long 0x20 0. " MFSINT[0] ,Reception interrupt request on MFS channel 0" "Not requested,Requested" line.long (0x20+0x4) "IRQ8MON,IRQ8 Batch Read Register" bitfld.long (0x20+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 8" "Not requested,Requested" bitfld.long (0x20+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 0" "Not requested,Requested" bitfld.long (0x20+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 0" "Not requested,Requested" line.long 0x28 "IRQ9MON,IRQ9 Batch Read Register" bitfld.long 0x28 1. " MFSINT[1] ,Reception interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long 0x28 0. " MFSINT[0] ,Reception interrupt request on MFS channel 1" "Not requested,Requested" line.long (0x28+0x4) "IRQ10MON,IRQ10 Batch Read Register" bitfld.long (0x28+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 9" "Not requested,Requested" bitfld.long (0x28+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 1" "Not requested,Requested" bitfld.long (0x28+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 1" "Not requested,Requested" line.long 0x30 "IRQ11MON,IRQ11 Batch Read Register" bitfld.long 0x30 1. " MFSINT[1] ,Reception interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long 0x30 0. " MFSINT[0] ,Reception interrupt request on MFS channel 2" "Not requested,Requested" line.long (0x30+0x4) "IRQ12MON,IRQ12 Batch Read Register" bitfld.long (0x30+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 10" "Not requested,Requested" bitfld.long (0x30+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 2" "Not requested,Requested" bitfld.long (0x30+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 2" "Not requested,Requested" line.long 0x38 "IRQ13MON,IRQ13 Batch Read Register" bitfld.long 0x38 1. " MFSINT[1] ,Reception interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long 0x38 0. " MFSINT[0] ,Reception interrupt request on MFS channel 3" "Not requested,Requested" line.long (0x38+0x4) "IRQ14MON,IRQ14 Batch Read Register" bitfld.long (0x38+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 11" "Not requested,Requested" bitfld.long (0x38+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 3" "Not requested,Requested" bitfld.long (0x38+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 3" "Not requested,Requested" line.long 0x40 "IRQ15MON,IRQ15 Batch Read Register" bitfld.long 0x40 1. " MFSINT[1] ,Reception interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long 0x40 0. " MFSINT[0] ,Reception interrupt request on MFS channel 4" "Not requested,Requested" line.long (0x40+0x4) "IRQ16MON,IRQ16 Batch Read Register" bitfld.long (0x40+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 12" "Not requested,Requested" bitfld.long (0x40+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 4" "Not requested,Requested" bitfld.long (0x40+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 4" "Not requested,Requested" line.long 0x48 "IRQ17MON,IRQ17 Batch Read Register" bitfld.long 0x48 1. " MFSINT[1] ,Reception interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long 0x48 0. " MFSINT[0] ,Reception interrupt request on MFS channel 5" "Not requested,Requested" line.long (0x48+0x4) "IRQ18MON,IRQ18 Batch Read Register" bitfld.long (0x48+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 13" "Not requested,Requested" bitfld.long (0x48+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 5" "Not requested,Requested" bitfld.long (0x48+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 5" "Not requested,Requested" line.long 0x50 "IRQ19MON,IRQ19 Batch Read Register" bitfld.long 0x50 1. " MFSINT[1] ,Reception interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long 0x50 0. " MFSINT[0] ,Reception interrupt request on MFS channel 6" "Not requested,Requested" line.long (0x50+0x4) "IRQ20MON,IRQ20 Batch Read Register" bitfld.long (0x50+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 14" "Not requested,Requested" bitfld.long (0x50+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 6" "Not requested,Requested" bitfld.long (0x50+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 6" "Not requested,Requested" line.long 0x58 "IRQ21MON,IRQ21 Batch Read Register" bitfld.long 0x58 1. " MFSINT[1] ,Reception interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long 0x58 0. " MFSINT[0] ,Reception interrupt request on MFS channel 7" "Not requested,Requested" line.long (0x58+0x4) "IRQ22MON,IRQ22 Batch Read Register" bitfld.long (0x58+0x4) 3. " MFSINT[3] ,Status interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 2. " MFSINT[2] ,Transmission interrupt request on MFS channel 15" "Not requested,Requested" bitfld.long (0x58+0x4) 1. " MFSINT[1] ,Status interrupt request on MFS channel 7" "Not requested,Requested" bitfld.long (0x58+0x4) 0. " MFSINT[0] ,Transmission interrupt request on MFS channel 7" "Not requested,Requested" line.long 0x60 "IRQ23MON,IRQ23 Batch Read Register" bitfld.long 0x60 8. " PPGINT[8] ,Interrupt request on PPG ch. 20" "Not requested,Requested" bitfld.long 0x60 7. " PPGINT[7] ,Interrupt request on PPG ch. 18" "Not requested,Requested" bitfld.long 0x60 6. " PPGINT[6] ,Interrupt request on PPG ch. 16" "Not requested,Requested" textline " " bitfld.long 0x60 5. " PPGINT[5] ,Interrupt request on PPG ch. 12" "Not requested,Requested" bitfld.long 0x60 4. " PPGINT[4] ,Interrupt request on PPG ch. 10" "Not requested,Requested" bitfld.long 0x60 3. " PPGINT[3] ,Interrupt request on PPG ch. 8" "Not requested,Requested" bitfld.long 0x60 2. " PPGINT[2] ,Interrupt request on PPG ch. 4" "Not requested,Requested" textline " " bitfld.long 0x60 1. " PPGINT[1] ,Interrupt request on PPG ch. 2" "Not requested,Requested" bitfld.long 0x60 0. " PPGINT[0] ,Interrupt request on PPG ch. 0" "Not requested,Requested" line.long 0x64 "IRQ24MON,IRQ24 Batch Read Register" sif (!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")&&!cpuis("MB9BFD16S")||!cpuis("MB9BFD16T")||!cpuis("MB9BFD17S")||!cpuis("MB9BFD17T")||!cpuis("MB9BFD18S")||!cpuis("MB9BFD18T")) bitfld.long 0x64 5. " RTCINT ,RTC interrupt request" "Not requested,Requested" textline " " endif bitfld.long 0x64 4. " WCINT ,Watch counter interrupt request" "Not requested,Requested" bitfld.long 0x64 3. " UPLLINT ,Stabilization wait completion interrupt request for USB or USB/Ethernet PLL oscillation" "Not requested,Requested" bitfld.long 0x64 2. " MPLLINT ,Stabilization wait completion interrupt request for PLL oscillation" "Not requested,Requested" bitfld.long 0x64 1. " SOSCINT ,Stabilization wait completion interrupt request for sub-clock oscillation" "Not requested,Requested" textline " " bitfld.long 0x64 0. " MOSCINT ,Stabilization wait completion interrupt request for main clock oscillation" "Not requested,Requested" rgroup.long 0x78++0x03 line.long 0x00 "IRQ25MON,IRQ25 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit0 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit0 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit0 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit0 priority conversion interrupt request" "Not requested,Requested" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF14*")||cpuis("MB9AF3*")||cpuis("MB9AF?4*")||cpuis("MB9B*")) rgroup.long 0x7C++0x03 line.long 0x00 "IRQ26MON,IRQ26 Batch Read Register" bitfld.long 0x00 3. " ADCINT[3] ,ADC unit1 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit1 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit1 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit1 priority conversion interrupt request" "Not requested,Requested" endif rgroup.long 0x80++0x03 line.long 0x00 "IRQ27MON,IRQ27 Batch Read Register" sif (cpuis("MB9AFA*")||cpuis("MB9AFB*")) bitfld.long 0x00 4. " LCDCINT ,LCDC interrupt request for LCD controller" "Not requested,Requested" textline " " endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF31*")||cpuis("MB9B*")) bitfld.long 0x00 3. " ADCINT[3] ,ADC unit2 conversion result comparison interrupt request" "Not requested,Requested" bitfld.long 0x00 2. " ADCINT[2] ,ADC unit2 FIFO overrun interrupt request" "Not requested,Requested" bitfld.long 0x00 1. " ADCINT[1] ,ADC unit2 scan conversion interrupt request" "Not requested,Requested" bitfld.long 0x00 0. " ADCINT[0] ,ADC unit2 priority conversion interrupt request" "Not requested,Requested" endif sif (!cpuis("MB9AF?4*")) rgroup.long 0x84++0x03 line.long 0x00 "IRQ28MON,IRQ28 Batch Read Register" sif (cpuis("MB9BF*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x00 17. " FRT2INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 16. " FRT2INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 15. " FRT2INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " bitfld.long 0x00 14. " FRT2INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 13. " FRT2INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 12. " FRT2INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " endif sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) bitfld.long 0x00 11. " FRT1INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 10. " FRT1INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 9. " FRT1INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " bitfld.long 0x00 8. " FRT1INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 7. " FRT1INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 6. " FRT1INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " endif bitfld.long 0x00 5. " FRT0INT[5] ,Zero detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " FRT0INT[4] ,Zero detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 3. " FRT0INT[3] ,Zero detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 2. " FRT0INT[2] ,Peak value detection interrupt request on the free run timer ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " FRT0INT[1] ,Peak value detection interrupt request on the free run timer ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " FRT0INT[0] ,Peak value detection interrupt request on the free run timer ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x88++0x03 line.long 0x00 "IRQ29MON,IRQ29 Batch Read Register" sif (cpuis("MB9BF*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x00 11. " ICU2INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 10. " ICU2INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 9. " ICU2INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 8. " ICU2INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " endif sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) bitfld.long 0x00 7. " ICU1INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 6. " ICU1INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 5. " ICU1INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 4. " ICU1INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " endif bitfld.long 0x00 3. " ICU0INT[3] ,Interrupt request on the input capture ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " ICU0INT[2] ,Interrupt request on the input capture ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " ICU0INT[1] ,Interrupt request on the input capture ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " ICU0INT[0] ,Interrupt request on the input capture ch. 0 in the MFT unit 0" "Not requested,Requested" rgroup.long 0x8C++0x03 line.long 0x00 "IRQ30MON,IRQ30 Batch Read Register" sif (cpuis("MB9BF*")&&!cpuis("MB9BF102N")&&!cpuis("MB9BF102R")) bitfld.long 0x00 17. " OCU2INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 16. " OCU2INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 15. " OCU2INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 14. " OCU2INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 2" "Not requested,Requested" textline " " bitfld.long 0x00 13. " OCU2INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 2" "Not requested,Requested" bitfld.long 0x00 12. " OCU2INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 2" "Not requested,Requested" textline " " endif sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) bitfld.long 0x00 11. " OCU1INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 10. " OCU1INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 9. " OCU1INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 8. " OCU1INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 1" "Not requested,Requested" textline " " bitfld.long 0x00 7. " OCU1INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 1" "Not requested,Requested" bitfld.long 0x00 6. " OCU1INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 1" "Not requested,Requested" textline " " endif bitfld.long 0x00 5. " OCU0INT[5] ,Interrupt request on the output compare ch. 5 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 4. " OCU0INT[4] ,Interrupt request on the output compare ch. 4 in the MFT unit 0" "Not requested,Requested" textline " " bitfld.long 0x00 3. " OCU0INT[3] ,Interrupt request on the output compare ch. 3 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 2. " OCU0INT[2] ,Interrupt request on the output compare ch. 2 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 1. " OCU0INT[1] ,Interrupt request on the output compare ch. 1 in the MFT unit 0" "Not requested,Requested" bitfld.long 0x00 0. " OCU0INT[0] ,Interrupt request on the output compare ch. 0 in the MFT unit 0" "Not requested,Requested" endif rgroup.long 0x90++0x0B line.long 0x00 "IRQ31MON,IRQ31 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[14] ,IRQ0 interrupt request on the base timer ch. 7" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[13] ,IRQ1 interrupt request on the base timer ch. 6" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[12] ,IRQ0 interrupt request on the base timer ch. 6" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[11] ,IRQ1 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[10] ,IRQ0 interrupt request on the base timer ch. 5" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[9] ,IRQ1 interrupt request on the base timer ch. 4" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[8] ,IRQ0 interrupt request on the base timer ch. 4" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[7] ,IRQ1 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[6] ,IRQ0 interrupt request on the base timer ch. 3" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[5] ,IRQ1 interrupt request on the base timer ch. 2" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[4] ,IRQ0 interrupt request on the base timer ch. 2" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[3] ,IRQ1 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[2] ,IRQ0 interrupt request on the base timer ch. 1" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[1] ,IRQ1 interrupt request on the base timer ch. 0" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[0] ,IRQ0 interrupt request on the base timer ch. 0" "Not requested,Requested" line.long 0x04 "IRQ32MON,IRQ32 Batch Read Register" sif (cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BFD1")) bitfld.long 0x04 3. " MAC0LPI ,LPI interrupt request of Ethernet MAC ch.0" "Not requested,Requested" bitfld.long 0x04 2. " MAC0PMI ,PMI interrupt request of Ethernet MAC ch.0" "Not requested,Requested" bitfld.long 0x04 1. " MAC0SBD ,SBD interrupt request of Ethernet MAC ch.0" "Not requested,Requested" textline " " endif sif (cpuis("MB9BF4*")||cpuis("MB9BF5*")||cpuis("MB9BF6*")||cpuis("MB9BFD1*")) bitfld.long 0x04 0. " CAN0INT ,Interrupt request of CAN ch.0" "Not requested,Requested" endif line.long 0x08 "IRQ33MON,IRQ33 Batch Read Register" sif (cpuis("MB9BF61?S")||cpuis("MB9BF61?T"))||cpuis("MB9BFD1") bitfld.long 0x08 2. " MAC1PMI ,PMI interrupt request of Ethernet MAC ch.1" "Not requested,Requested" bitfld.long 0x08 1. " MAC1SBD ,SBD interrupt request of Ethernet MAC ch.1" "Not requested,Requested" textline " " endif sif (cpuis("MB9BF4*")||cpuis("MB9BF5*")||cpuis("MB9BF6*")||cpuis("MB9BFD1*")) bitfld.long 0x08 0. " CAN1INT ,Interrupt request of CAN ch.1" "Not requested,Requested" endif sif ((!cpuis("MB9BF102N"))&&(!cpuis("MB9BF102R"))&&(!cpuis("MB9AF105NA"))&&(!cpuis("MB9AF105RA"))&&(!cpuis("MB9AF11*"))&&(!cpuis("MB9AF13*"))&&(!cpuis("MB9AF14*"))&&(!cpuis("MB9AFA*"))&&(!cpuis("MB9BF11*"))&&(!cpuis("MB9B4*"))) rgroup.long 0x9C++0x07 line.long 0x00 "IRQ34MON,IRQ34 Batch Read Register" bitfld.long 0x00 4. " USB0INT[4] ,Endpoint 5 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 3. " USB0INT[3] ,Endpoint 4 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 2. " USB0INT[2] ,Endpoint 3 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x00 1. " USB0INT[1] ,Endpoint 2 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB0INT[0] ,Endpoint 1 DRQ interrupt request on the USB ch. 0" "Not requested,Requested" line.long 0x04 "IRQ35MON,IRQ35 Batch Read Register" bitfld.long 0x04 5. " USB0INT[5] ,Status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 4. " USB0INT[4] ,Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 3. " USB0INT[3] ,Status (SPK) interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 2. " USB0INT[2] ,Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the USB ch. 0" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB0INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch. 0" "Not requested,Requested" bitfld.long 0x04 0. " USB0INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch. 0" "Not requested,Requested" endif rgroup.long 0xA4++0x07 line.long 0x00 "IRQ36MON,IRQ36 Batch Read Register" sif (cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF14?L")||cpuis("MB9AF14?M")||cpuis("MB9AF14?N")||cpuis("MB9AF34?L")||cpuis("MB9AF34?M")||cpuis("MB9AF34?N")||cpuis("MB9AF14?M")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AFA3??")) bitfld.long 0x00 5. " RCEC0INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.0" "Not requested,Requested" textline " " endif sif (cpuis("MB9BFD1*")||cpuis("MB9BF2*")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF5*S")||cpuis("MB9BF5*T")||cpuis("MB9BF6*")) bitfld.long 0x00 4. " USB1INT[4] ,Interrupt request of USB ch.1 Endpoint5 DRQ" "Not requested,Requested" bitfld.long 0x00 3. " USB1INT[3] ,Interrupt request of USB ch.1 Endpoint4 DRQ" "Not requested,Requested" textline " " bitfld.long 0x00 2. " USB1INT[2] ,Interrupt request of USB ch.1 Endpoint3 DRQ" "Not requested,Requested" bitfld.long 0x00 1. " USB1INT[1] ,Interrupt request of USB ch.1 Endpoint2 DRQ" "Not requested,Requested" textline " " bitfld.long 0x00 0. " USB1INT[0] ,Interrupt request of USB ch.1 Endpoint1 DRQ" "Not requested,Requested" endif line.long 0x04 "IRQ37MON,IRQ37 Batch Read Register" sif (cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF14?L")||cpuis("MB9AF14?M")||cpuis("MB9AF14?N")||cpuis("MB9AF34?L")||cpuis("MB9AF34?M")||cpuis("MB9AF34?N")||cpuis("MB9AF14?M")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AFA3??")) bitfld.long 0x04 6. " RCEC1INT ,Interrupt request for HDMI-CEC/Remote Control Reception ch.1" "Not requested,Requested" textline " " endif sif (cpuis("MB9BFD1*")||cpuis("MB9BF2*")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF5*S")||cpuis("MB9BF5*T")||cpuis("MB9BF6*")) bitfld.long 0x04 5. " USB1INT[5] ,Interrupt request of USB ch.1 status (SOFIRQ, CMPIRQ)" "Not requested,Requested" bitfld.long 0x04 4. " USB1INT[4] ,Interrupt request of USB ch.1 status (DIRQ, URIRQ, RWKIRQ, CNNIRQ)" "Not requested,Requested" textline " " bitfld.long 0x04 3. " USB1INT[3] ,Interrupt request of USB ch.1 status (SPK)" "Not requested,Requested" bitfld.long 0x04 2. " USB1INT[2] ,Interrupt request of USB ch.1 status (SUSP, SOF, BRST, CONF, WKUP)" "Not requested,Requested" textline " " bitfld.long 0x04 1. " USB1INT[1] ,Endpoint 0 DRQO interrupt request on the USB ch.1" "Not requested,Requested" bitfld.long 0x04 0. " USB1INT[0] ,Endpoint 0 DRQI interrupt request on the USB ch.1" "Not requested,Requested" endif rgroup.long 0xAC++0x03 line.long 0x00 "IRQ38MON,IRQ38 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 0" "Not requested,Requested" rgroup.long 0xB0++0x03 line.long 0x00 "IRQ39MON,IRQ39 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 1" "Not requested,Requested" rgroup.long 0xB4++0x03 line.long 0x00 "IRQ40MON,IRQ40 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 2" "Not requested,Requested" rgroup.long 0xB8++0x03 line.long 0x00 "IRQ41MON,IRQ41 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 3" "Not requested,Requested" rgroup.long 0xBC++0x03 line.long 0x00 "IRQ42MON,IRQ42 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 4" "Not requested,Requested" rgroup.long 0xC0++0x03 line.long 0x00 "IRQ43MON,IRQ43 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 5" "Not requested,Requested" rgroup.long 0xC4++0x03 line.long 0x00 "IRQ44MON,IRQ44 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 6" "Not requested,Requested" rgroup.long 0xC8++0x03 line.long 0x00 "IRQ45MON,IRQ45 Batch Read Register" bitfld.long 0x00 0. " DMAINT ,Interrupt request on DMA controller channel 7" "Not requested,Requested" sif (cpuis("MB9BF?1?S")||cpuis("MB9BF?1?T")) rgroup.long 0xCC++0x03 line.long 0x00 "IRQ46MON,IRQ46 Batch Read Register" bitfld.long 0x00 15. " BTINT[15] ,IRQ1 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 14. " BTINT[15] ,IRQ0 interrupt request of base timer ch.15" "Not requested,Requested" bitfld.long 0x00 13. " BTINT[14] ,IRQ1 interrupt request of base timer ch.14" "Not requested,Requested" bitfld.long 0x00 12. " BTINT[14] ,IRQ0 interrupt request of base timer ch.14" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BTINT[13] ,IRQ1 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 10. " BTINT[13] ,IRQ0 interrupt request of base timer ch.13" "Not requested,Requested" bitfld.long 0x00 9. " BTINT[12] ,IRQ1 interrupt request of base timer ch.12" "Not requested,Requested" bitfld.long 0x00 8. " BTINT[12] ,IRQ0 interrupt request of base timer ch.12" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BTINT[11] ,IRQ1 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 6. " BTINT[11] ,IRQ0 interrupt request of base timer ch.11" "Not requested,Requested" bitfld.long 0x00 5. " BTINT[10] ,IRQ1 interrupt request of base timer ch.10" "Not requested,Requested" bitfld.long 0x00 4. " BTINT[10] ,IRQ0 interrupt request of base timer ch.10" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BTINT[9] ,IRQ1 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 2. " BTINT[9] ,IRQ0 interrupt request of base timer ch.9" "Not requested,Requested" bitfld.long 0x00 1. " BTINT[8] ,IRQ1 interrupt request of base timer ch.8" "Not requested,Requested" bitfld.long 0x00 0. " BTINT[8] ,IRQ0 interrupt request of base timer ch.8" "Not requested,Requested" endif rgroup.long 0xD0++0x03 line.long 0x00 "IRQ47MON,IRQ47 Batch Read Register" bitfld.long 0x00 11. " FLASHINT ,RDY/HANG interrupt request for flash" "Not requested,Requested" sif ((!cpuis("MB9BF102N"))&&(!cpuis("MB9BF102R"))&&(!cpuis("MB9AF105NA"))&&(!cpuis("MB9AF105RA"))&&(!cpuis("MB9AF11*"))&&(!cpuis("MB9AF13*"))&&(!cpuis("MB9AF14*"))&&(!cpuis("MB9AFA*"))&&(!cpuis("MB9BF11*"))&&(!cpuis("MB9B4*"))) group.byte 0x20F++0x3 line.byte 0x00 "ODDPKS,USB ch.0 Odd Packet Size DMA Enable Register" bitfld.byte 0x00 4. " ODDPKS4 ,DMA USB.EP5DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 3. " ODDPKS3 ,DMA USB.EP4DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 2. " ODDPKS2 ,DMA USB.EP3DT transfer bit width converted" "Not converted,Converted" bitfld.byte 0x00 1. " ODDPKS1 ,DMA USB.EP2DT transfer bit width converted" "Not converted,Converted" textline " " bitfld.byte 0x00 0. " ODDPKS0 ,DMA USB.EP1DT transfer bit width converted" "Not converted,Converted" endif width 12. endif tree.end tree "External Interrupt and NMI Control Sections" base ad:0x40030000 sif ((cpu()=="MB9AF105NA")||(cpu()=="MB9AF105RA")||(cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")||(cpu()=="MB9AF111L")||(cpu()=="MB9AF111M")||(cpu()=="MB9AF111N")||(cpu()=="MB9AF112L")||(cpu()=="MB9AF112M")||(cpu()=="MB9AF112N")||(cpu()=="MB9AF114L")||(cpu()=="MB9AF114M")||(cpu()=="MB9AF114N")||(cpu()=="MB9AF115M")||(cpu()=="MB9AF115N")||(cpu()=="MB9AF116M")||(cpu()=="MB9AF116N")||(cpu()=="MB9AF311L")||(cpu()=="MB9AF311M")||(cpu()=="MB9AF311N")||(cpu()=="MB9AF312L")||(cpu()=="MB9AF312M")||(cpu()=="MB9AF312N")||(cpu()=="MB9AF314L")||(cpu()=="MB9AF314M")||(cpu()=="MB9AF314N")||(cpu()=="MB9AF315M")||(cpu()=="MB9AF315N")||(cpu()=="MB9AF316M")||(cpu()=="MB9AF316N")||(cpu()=="MB9AF141L")||(cpu()=="MB9AF141M")||(cpu()=="MB9AF141N")||(cpu()=="MB9AF142L")||(cpu()=="MB9AF142M")||(cpu()=="MB9AF142N")||(cpu()=="MB9AF144L")||(cpu()=="MB9AF144M")||(cpu()=="MB9AF144N")||(cpu()=="MB9AF341L")||(cpu()=="MB9AF341M")||(cpu()=="MB9AF341N")||(cpu()=="MB9AF342L")||(cpu()=="MB9AF342M")||(cpu()=="MB9AF342N")||(cpu()=="MB9AF344L")||(cpu()=="MB9AF344M")||(cpu()=="MB9AF344N")||(cpu()=="MB9AFA41L")||(cpu()=="MB9AFA41M")||(cpu()=="MB9AFA41N")||(cpu()=="MB9AFA42L")||(cpu()=="MB9AFA42M")||(cpu()=="MB9AFA42N")||(cpu()=="MB9AFA44L")||(cpu()=="MB9AFA44M")||(cpu()=="MB9AFA44N")||(cpu()=="MB9AFB41L")||(cpu()=="MB9AFB41M")||(cpu()=="MB9AFB41N")||(cpu()=="MB9AFB42L")||(cpu()=="MB9AFB42M")||(cpu()=="MB9AFB42N")||(cpu()=="MB9AFB44L")||(cpu()=="MB9AFB44M")||(cpu()=="MB9AFB44N")||(cpu()=="MB9AF131L")||(cpu()=="MB9AF132L")||(cpu()=="MB9AF131N")||(cpu()=="MB9AF131M")||(cpu()=="MB9AF132N")||(cpu()=="MB9AF132M")||(cpu()=="MB9AFA31L")||(cpu()=="MB9AFA31M")||(cpu()=="MB9AFA31N")||(cpu()=="MB9AFA32L")||(cpu()=="MB9AFA32M")||(cpu()=="MB9AFA32N")||(cpu()=="MB9BF112N")||(cpu()=="MB9BF112R")||(cpu()=="MB9BF114N")||(cpu()=="MB9BF114R")||(cpu()=="MB9BF115N")||(cpu()=="MB9BF115R")||(cpu()=="MB9BF116N")||(cpu()=="MB9BF116R")||(cpu()=="MB9BF116S")||(cpu()=="MB9BF116T")||(cpu()=="MB9BF117S")||(cpu()=="MB9BF117T")||(cpu()=="MB9BF118S")||(cpu()=="MB9BF118T")||(cpu()=="MB9BF216S")||(cpu()=="MB9BF216T")||(cpu()=="MB9BF217S")||(cpu()=="MB9BF217T")||(cpu()=="MB9BF218S")||(cpu()=="MB9BF218T")||(cpu()=="MB9BF312N")||(cpu()=="MB9BF312R")||(cpu()=="MB9BF314N")||(cpu()=="MB9BF314R")||(cpu()=="MB9BF315N")||(cpu()=="MB9BF315R")||(cpu()=="MB9BF316N")||(cpu()=="MB9BF316R")||(cpu()=="MB9BF316S")||(cpu()=="MB9BF316T")||(cpu()=="MB9BF317S")||(cpu()=="MB9BF317T")||(cpu()=="MB9BF318S")||(cpu()=="MB9BF318T")||(cpu()=="MB9BF412N")||(cpu()=="MB9BF412R")||(cpu()=="MB9BF414N")||(cpu()=="MB9BF414R")||(cpu()=="MB9BF415N")||(cpu()=="MB9BF415R")||(cpu()=="MB9BF416N")||(cpu()=="MB9BF416R")||(cpu()=="MB9BF416S")||(cpu()=="MB9BF416T")||(cpu()=="MB9BF417S")||(cpu()=="MB9BF417T")||(cpu()=="MB9BF418S")||(cpu()=="MB9BF418T")||(cpu()=="MB9BF512N")||(cpu()=="MB9BF512R")||(cpu()=="MB9BF514N")||(cpu()=="MB9BF514R")||(cpu()=="MB9BF515N")||(cpu()=="MB9BF515R")||(cpu()=="MB9BF516N")||(cpu()=="MB9BF516R")||(cpu()=="MB9BF516S")||(cpu()=="MB9BF516T")||(cpu()=="MB9BF517S")||(cpu()=="MB9BF517T")||(cpu()=="MB9BF518S")||(cpu()=="MB9BF518T")||(cpu()=="MB9BF616S")||(cpu()=="MB9BF616T")||(cpu()=="MB9BF617S")||(cpu()=="MB9BF617T")||(cpu()=="MB9BF618S")||(cpu()=="MB9BF618T")) width 7. group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x00 31. " EN31 ,External interrupt enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " EN30 ,External interrupt enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " EN29 ,External interrupt enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " EN28 ,External interrupt enable bit 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " EN27 ,External interrupt enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " EN26 ,External interrupt enable bit 26" "Disabled,Enabled" bitfld.long 0x00 25. " EN25 ,External interrupt enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " EN24 ,External interrupt enable bit 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " EN23 ,External interrupt enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " EN22 ,External interrupt enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " EN21 ,External interrupt enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " EN20 ,External interrupt enable bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " EN17 ,External interrupt enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " EN16 ,External interrupt enable bit 16" "Disabled,Enabled" textline " " endif bitfld.long 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")) bitfld.long 0x00 13. " EN13 ,External interrupt enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " EN12 ,External interrupt enable bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " EN11 ,External interrupt enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " EN10 ,External interrupt enable bit 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EN9 ,External interrupt enable bit 9" "Disabled,Enabled" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x00 8. " EN8 ,External interrupt enable bit 8" "Disabled,Enabled" bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" textline " " endif bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")||cpuis("MB9AF*L")) bitfld.long 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" textline " " endif bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x00 31. " ER31 ,External interrupt request detection bit 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " ER30 ,External interrupt request detection bit 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " ER29 ,External interrupt request detection bit 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " ER28 ,External interrupt request detection bit 28" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " ER27 ,External interrupt request detection bit 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " ER26 ,External interrupt request detection bit 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " ER25 ,External interrupt request detection bit 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " ER24 ,External interrupt request detection bit 24" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " ER23 ,External interrupt request detection bit 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " ER22 ,External interrupt request detection bit 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " ER21 ,External interrupt request detection bit 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ER20 ,External interrupt request detection bit 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ER17 ,External interrupt request detection bit 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " ER16 ,External interrupt request detection bit 16" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")) bitfld.long 0x00 13. " ER13 ,External interrupt request detection bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " ER12 ,External interrupt request detection bit 12" "No interrupt,Interrupt" bitfld.long 0x00 11. " ER11 ,External interrupt request detection bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " ER10 ,External interrupt request detection bit 10" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " ER9 ,External interrupt request detection bit 9" "No interrupt,Interrupt" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x00 8. " ER8 ,External interrupt request detection bit 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")||cpuis("MB9AF*L")) bitfld.long 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) bitfld.long 0x00 31. " ECL31 ,External interrupt factor clear bit 31" "Cleared,No effect" bitfld.long 0x00 30. " ECL30 ,External interrupt factor clear bit 30" "Cleared,No effect" bitfld.long 0x00 29. " ECL29 ,External interrupt factor clear bit 29" "Cleared,No effect" bitfld.long 0x00 28. " ECL28 ,External interrupt factor clear bit 28" "Cleared,No effect" textline " " bitfld.long 0x00 27. " ECL27 ,External interrupt factor clear bit 27" "Cleared,No effect" bitfld.long 0x00 26. " ECL26 ,External interrupt factor clear bit 26" "Cleared,No effect" bitfld.long 0x00 25. " ECL25 ,External interrupt factor clear bit 25" "Cleared,No effect" bitfld.long 0x00 24. " ECL24 ,External interrupt factor clear bit 24" "Cleared,No effect" textline " " bitfld.long 0x00 23. " ECL23 ,External interrupt factor clear bit 23" "Cleared,No effect" bitfld.long 0x00 22. " ECL22 ,External interrupt factor clear bit 22" "Cleared,No effect" bitfld.long 0x00 21. " ECL21 ,External interrupt factor clear bit 21" "Cleared,No effect" bitfld.long 0x00 20. " ECL20 ,External interrupt factor clear bit 20" "Cleared,No effect" textline " " bitfld.long 0x00 19. " ECL19 ,External interrupt factor clear bit 19" "Cleared,No effect" bitfld.long 0x00 18. " ECL18 ,External interrupt factor clear bit 18" "Cleared,No effect" bitfld.long 0x00 17. " ECL17 ,External interrupt factor clear bit 17" "Cleared,No effect" bitfld.long 0x00 16. " ECL16 ,External interrupt factor clear bit 16" "Cleared,No effect" textline " " endif bitfld.long 0x00 15. " ECL15 ,External interrupt factor clear bit 15" "Cleared,No effect" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x00 14. " ECL14 ,External interrupt factor clear bit 14" "Cleared,No effect" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")) bitfld.long 0x00 13. " ECL13 ,External interrupt factor clear bit 13" "Cleared,No effect" bitfld.long 0x00 12. " ECL12 ,External interrupt factor clear bit 12" "Cleared,No effect" bitfld.long 0x00 11. " ECL11 ,External interrupt factor clear bit 11" "Cleared,No effect" bitfld.long 0x00 10. " ECL10 ,External interrupt factor clear bit 10" "Cleared,No effect" textline " " bitfld.long 0x00 9. " ECL9 ,External interrupt factor clear bit 9" "Cleared,No effect" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x00 8. " ECL8 ,External interrupt factor clear bit 8" "Cleared,No effect" bitfld.long 0x00 7. " ECL7 ,External interrupt factor clear bit 7" "Cleared,No effect" textline " " endif bitfld.long 0x00 6. " ECL6 ,External interrupt factor clear bit 6" "Cleared,No effect" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")||cpuis("MB9AF*L")) bitfld.long 0x00 5. " ECL5 ,External interrupt factor clear bit 5" "Cleared,No effect" bitfld.long 0x00 4. " ECL4 ,External interrupt factor clear bit 4" "Cleared,No effect" textline " " endif bitfld.long 0x00 3. " ECL3 ,External interrupt factor clear bit 3" "Cleared,No effect" bitfld.long 0x00 2. " ECL2 ,External interrupt factor clear bit 2" "Cleared,No effect" bitfld.long 0x00 1. " ECL1 ,External interrupt factor clear bit 1" "Cleared,No effect" bitfld.long 0x00 0. " ECL0 ,External interrupt factor clear bit 0" "Cleared,No effect" group.long 0xC++0x7 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")) bitfld.long 0x0 26.--27. " LA/B13 ,External interrupt request detection level selection bit 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B12 ,External interrupt request detection level selection bit 12" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 22.--23. " LA/B11 ,External interrupt request detection level selection bit 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B10 ,External interrupt request detection level selection bit 10" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 18.--19. " LA/B9 ,External interrupt request detection level selection bit 9" "Low level,High level,Rising edge,Falling edge" textline " " endif sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")) bitfld.long 0x0 16.--17. " LA/B8 ,External interrupt request detection level selection bit 8" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" textline " " endif bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" textline " " sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9?F*N")||cpuis("MB9?F*N?")||cpuis("MB9?F*R")||cpuis("MB9?F*R?")||cpuis("MB9AF*M")||cpuis("MB9AF*L")) bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " endif bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B31 ,External interrupt request detection level selection bit 31" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B30 ,External interrupt request detection level selection bit 30" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B29 ,External interrupt request detection level selection bit 29" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B28 ,External interrupt request detection level selection bit 28" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 22.--23. " LA/B27 ,External interrupt request detection level selection bit 27" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B26 ,External interrupt request detection level selection bit 26" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 18.--19. " LA/B25 ,External interrupt request detection level selection bit 25" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B24 ,External interrupt request detection level selection bit 24" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B23 ,External interrupt request detection level selection bit 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B22 ,External interrupt request detection level selection bit 22" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B21 ,External interrupt request detection level selection bit 21" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B20 ,External interrupt request detection level selection bit 20" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B17 ,External interrupt request detection level selection bit 17" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B16 ,External interrupt request detection level selection bit 16" "Low level,High level,Rising edge,Falling edge" endif rgroup.byte 0x34++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x38++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" width 12. else width 7. sif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" bitfld.long 0x00 31. " EN31 ,External interrupt enable bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " EN30 ,External interrupt enable bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " EN29 ,External interrupt enable bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " EN28 ,External interrupt enable bit 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " EN27 ,External interrupt enable bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " EN26 ,External interrupt enable bit 26" "Disabled,Enabled" bitfld.long 0x00 25. " EN25 ,External interrupt enable bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " EN24 ,External interrupt enable bit 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " EN23 ,External interrupt enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " EN22 ,External interrupt enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " EN21 ,External interrupt enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " EN20 ,External interrupt enable bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " EN17 ,External interrupt enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " EN16 ,External interrupt enable bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " EN13 ,External interrupt enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " EN12 ,External interrupt enable bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " EN11 ,External interrupt enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " EN10 ,External interrupt enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " EN9 ,External interrupt enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " EN8 ,External interrupt enable bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" bitfld.long 0x00 31. " ER31 ,External interrupt request detection bit 31" "No interrupt,Interrupt" bitfld.long 0x00 30. " ER30 ,External interrupt request detection bit 30" "No interrupt,Interrupt" bitfld.long 0x00 29. " ER29 ,External interrupt request detection bit 29" "No interrupt,Interrupt" bitfld.long 0x00 28. " ER28 ,External interrupt request detection bit 28" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " ER27 ,External interrupt request detection bit 27" "No interrupt,Interrupt" bitfld.long 0x00 26. " ER26 ,External interrupt request detection bit 26" "No interrupt,Interrupt" bitfld.long 0x00 25. " ER25 ,External interrupt request detection bit 25" "No interrupt,Interrupt" bitfld.long 0x00 24. " ER24 ,External interrupt request detection bit 24" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " ER23 ,External interrupt request detection bit 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " ER22 ,External interrupt request detection bit 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " ER21 ,External interrupt request detection bit 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ER20 ,External interrupt request detection bit 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ER17 ,External interrupt request detection bit 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " ER16 ,External interrupt request detection bit 16" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " ER13 ,External interrupt request detection bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " ER12 ,External interrupt request detection bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " ER11 ,External interrupt request detection bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " ER10 ,External interrupt request detection bit 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " ER9 ,External interrupt request detection bit 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " ER8 ,External interrupt request detection bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" bitfld.long 0x00 31. " ECL31 ,External interrupt cause clear bit 31" "Clear,No effect" bitfld.long 0x00 30. " ECL30 ,External interrupt cause clear bit 30" "Clear,No effect" bitfld.long 0x00 29. " ECL29 ,External interrupt cause clear bit 29" "Clear,No effect" bitfld.long 0x00 28. " ECL28 ,External interrupt cause clear bit 28" "Clear,No effect" textline " " bitfld.long 0x00 27. " ECL27 ,External interrupt cause clear bit 27" "Clear,No effect" bitfld.long 0x00 26. " ECL26 ,External interrupt cause clear bit 26" "Clear,No effect" bitfld.long 0x00 25. " ECL25 ,External interrupt cause clear bit 25" "Clear,No effect" bitfld.long 0x00 24. " ECL24 ,External interrupt cause clear bit 24" "Clear,No effect" textline " " bitfld.long 0x00 23. " ECL23 ,External interrupt cause clear bit 23" "Clear,No effect" bitfld.long 0x00 22. " ECL22 ,External interrupt cause clear bit 22" "Clear,No effect" bitfld.long 0x00 21. " ECL21 ,External interrupt cause clear bit 21" "Clear,No effect" bitfld.long 0x00 20. " ECL20 ,External interrupt cause clear bit 20" "Clear,No effect" textline " " bitfld.long 0x00 19. " ECL19 ,External interrupt cause clear bit 19" "Clear,No effect" bitfld.long 0x00 18. " ECL18 ,External interrupt cause clear bit 18" "Clear,No effect" bitfld.long 0x00 17. " ECL17 ,External interrupt cause clear bit 17" "Clear,No effect" bitfld.long 0x00 16. " ECL16 ,External interrupt cause clear bit 16" "Clear,No effect" textline " " bitfld.long 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.long 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.long 0x00 13. " ECL13 ,External interrupt cause clear bit 13" "Clear,No effect" bitfld.long 0x00 12. " ECL12 ,External interrupt cause clear bit 12" "Clear,No effect" textline " " bitfld.long 0x00 11. " ECL11 ,External interrupt cause clear bit 11" "Clear,No effect" bitfld.long 0x00 10. " ECL10 ,External interrupt cause clear bit 10" "Clear,No effect" bitfld.long 0x00 9. " ECL9 ,External interrupt cause clear bit 9" "Clear,No effect" bitfld.long 0x00 8. " ECL8 ,External interrupt cause clear bit 8" "Clear,No effect" textline " " bitfld.long 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" bitfld.long 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.long 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.long 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" textline " " bitfld.long 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.long 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.long 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.long 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B13 ,External interrupt request detection level selection bit 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B12 ,External interrupt request detection level selection bit 12" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 22.--23. " LA/B11 ,External interrupt request detection level selection bit 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B10 ,External interrupt request detection level selection bit 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 18.--19. " LA/B9 ,External interrupt request detection level selection bit 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B8 ,External interrupt request detection level selection bit 8" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register 1" bitfld.long 0x0 30.--31. " LA/B31 ,External interrupt request detection level selection bit 31" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B30 ,External interrupt request detection level selection bit 30" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B29 ,External interrupt request detection level selection bit 29" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B28 ,External interrupt request detection level selection bit 28" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 22.--23. " LA/B27 ,External interrupt request detection level selection bit 27" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B26 ,External interrupt request detection level selection bit 26" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 18.--19. " LA/B25 ,External interrupt request detection level selection bit 25" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B24 ,External interrupt request detection level selection bit 24" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B23 ,External interrupt request detection level selection bit 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B22 ,External interrupt request detection level selection bit 22" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B21 ,External interrupt request detection level selection bit 21" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B20 ,External interrupt request detection level selection bit 20" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B17 ,External interrupt request detection level selection bit 17" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B16 ,External interrupt request detection level selection bit 16" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9AF121K")||cpuis("MB9AF421K")||cpuis("MB9BF12?K")||cpuis("MB9BF52?K")||cpuis("MB9BF32?K")) group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" bitfld.long 0x00 21. " EN21 ,External interrupt enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " EN20 ,External interrupt enable bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " EN17 ,External interrupt enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " EN16 ,External interrupt enable bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" bitfld.long 0x00 21. " ER21 ,External interrupt request detection bit 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ER20 ,External interrupt request detection bit 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ER17 ,External interrupt request detection bit 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " ER16 ,External interrupt request detection bit 16" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" bitfld.long 0x00 21. " ECL21 ,External interrupt cause clear bit 21" "Clear,No effect" bitfld.long 0x00 20. " ECL20 ,External interrupt cause clear bit 20" "Clear,No effect" textline " " bitfld.long 0x00 19. " ECL19 ,External interrupt cause clear bit 19" "Clear,No effect" bitfld.long 0x00 18. " ECL18 ,External interrupt cause clear bit 18" "Clear,No effect" bitfld.long 0x00 17. " ECL17 ,External interrupt cause clear bit 17" "Clear,No effect" bitfld.long 0x00 16. " ECL16 ,External interrupt cause clear bit 16" "Clear,No effect" textline " " bitfld.long 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.long 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.long 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" bitfld.long 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" textline " " bitfld.long 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.long 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.long 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.long 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register 1" bitfld.long 0x0 10.--11. " LA/B21 ,External interrupt request detection level selection bit 21" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B20 ,External interrupt request detection level selection bit 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 2.--3. " LA/B17 ,External interrupt request detection level selection bit 17" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B16 ,External interrupt request detection level selection bit 16" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9AF121L")||cpuis("MB9AF421L")||cpuis("MB9BF12?L")||cpuis("MB9BF52?L")||cpuis("MB9BF32?L")) group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" bitfld.long 0x00 22. " EN22 ,External interrupt enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " EN21 ,External interrupt enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " EN20 ,External interrupt enable bit 20" "Disabled,Enabled" bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " EN17 ,External interrupt enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " EN16 ,External interrupt enable bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " EN13 ,External interrupt enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " EN12 ,External interrupt enable bit 12" "Disabled,Enabled" bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" bitfld.long 0x00 22. " ER22 ,External interrupt request detection bit 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " ER21 ,External interrupt request detection bit 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ER20 ,External interrupt request detection bit 20" "No interrupt,Interrupt" bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ER17 ,External interrupt request detection bit 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " ER16 ,External interrupt request detection bit 16" "No interrupt,Interrupt" bitfld.long 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " ER13 ,External interrupt request detection bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " ER12 ,External interrupt request detection bit 12" "No interrupt,Interrupt" bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" bitfld.long 0x00 22. " ECL22 ,External interrupt cause clear bit 22" "Clear,No effect" bitfld.long 0x00 21. " ECL21 ,External interrupt cause clear bit 21" "Clear,No effect" bitfld.long 0x00 20. " ECL20 ,External interrupt cause clear bit 20" "Clear,No effect" bitfld.long 0x00 19. " ECL19 ,External interrupt cause clear bit 19" "Clear,No effect" textline " " bitfld.long 0x00 18. " ECL18 ,External interrupt cause clear bit 18" "Clear,No effect" bitfld.long 0x00 17. " ECL17 ,External interrupt cause clear bit 17" "Clear,No effect" bitfld.long 0x00 16. " ECL16 ,External interrupt cause clear bit 16" "Clear,No effect" bitfld.long 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" textline " " bitfld.long 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.long 0x00 13. " ECL13 ,External interrupt cause clear bit 13" "Clear,No effect" bitfld.long 0x00 12. " ECL12 ,External interrupt cause clear bit 12" "Clear,No effect" bitfld.long 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" textline " " bitfld.long 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.long 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.long 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" bitfld.long 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" textline " " bitfld.long 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.long 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.long 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B13 ,External interrupt request detection level selection bit 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B12 ,External interrupt request detection level selection bit 12" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register 1" bitfld.long 0x0 12.--13. " LA/B22 ,External interrupt request detection level selection bit 22" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B21 ,External interrupt request detection level selection bit 21" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B20 ,External interrupt request detection level selection bit 20" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B17 ,External interrupt request detection level selection bit 17" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B16 ,External interrupt request detection level selection bit 16" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9BF121J")) group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" bitfld.long 0x00 19. " ECL19 ,External interrupt cause clear bit 19" "Clear,No effect" bitfld.long 0x00 18. " ECL18 ,External interrupt cause clear bit 18" "Clear,No effect" bitfld.long 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.long 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" textline " " bitfld.long 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.long 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.long 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register 1" bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9BF12?M")||cpuis("MB9BF52?M")||cpuis("MB9BF32?M")||cpuis("MB9AF15?M")) group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" bitfld.long 0x00 23. " EN23 ,External interrupt enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " EN22 ,External interrupt enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " EN21 ,External interrupt enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " EN20 ,External interrupt enable bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " EN17 ,External interrupt enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " EN16 ,External interrupt enable bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " EN13 ,External interrupt enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " EN12 ,External interrupt enable bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " EN11 ,External interrupt enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " EN10 ,External interrupt enable bit 10" "Disabled,Enabled" bitfld.long 0x00 8. " EN8 ,External interrupt enable bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" bitfld.long 0x00 23. " ER23 ,External interrupt request detection bit 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " ER22 ,External interrupt request detection bit 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " ER21 ,External interrupt request detection bit 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ER20 ,External interrupt request detection bit 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ER17 ,External interrupt request detection bit 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " ER16 ,External interrupt request detection bit 16" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " ER13 ,External interrupt request detection bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " ER12 ,External interrupt request detection bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " ER11 ,External interrupt request detection bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " ER10 ,External interrupt request detection bit 10" "No interrupt,Interrupt" bitfld.long 0x00 8. " ER8 ,External interrupt request detection bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" bitfld.long 0x00 23. " ECL23 ,External interrupt cause clear bit 23" "Clear,No effect" bitfld.long 0x00 22. " ECL22 ,External interrupt cause clear bit 22" "Clear,No effect" bitfld.long 0x00 21. " ECL21 ,External interrupt cause clear bit 21" "Clear,No effect" bitfld.long 0x00 20. " ECL20 ,External interrupt cause clear bit 20" "Clear,No effect" textline " " bitfld.long 0x00 19. " ECL19 ,External interrupt cause clear bit 19" "Clear,No effect" bitfld.long 0x00 18. " ECL18 ,External interrupt cause clear bit 18" "Clear,No effect" bitfld.long 0x00 17. " ECL17 ,External interrupt cause clear bit 17" "Clear,No effect" bitfld.long 0x00 16. " ECL16 ,External interrupt cause clear bit 16" "Clear,No effect" textline " " bitfld.long 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.long 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.long 0x00 13. " ECL13 ,External interrupt cause clear bit 13" "Clear,No effect" bitfld.long 0x00 12. " ECL12 ,External interrupt cause clear bit 12" "Clear,No effect" textline " " bitfld.long 0x00 11. " ECL11 ,External interrupt cause clear bit 11" "Clear,No effect" bitfld.long 0x00 10. " ECL10 ,External interrupt cause clear bit 10" "Clear,No effect" bitfld.long 0x00 8. " ECL8 ,External interrupt cause clear bit 8" "Clear,No effect" textline " " bitfld.long 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" bitfld.long 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.long 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.long 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" textline " " bitfld.long 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.long 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.long 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.long 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B13 ,External interrupt request detection level selection bit 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B12 ,External interrupt request detection level selection bit 12" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 22.--23. " LA/B11 ,External interrupt request detection level selection bit 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B10 ,External interrupt request detection level selection bit 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B8 ,External interrupt request detection level selection bit 8" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register 1" bitfld.long 0x0 14.--15. " LA/B23 ,External interrupt request detection level selection bit 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B22 ,External interrupt request detection level selection bit 22" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B21 ,External interrupt request detection level selection bit 21" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B20 ,External interrupt request detection level selection bit 20" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B17 ,External interrupt request detection level selection bit 17" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B16 ,External interrupt request detection level selection bit 16" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) group.long 0x0++0x3 line.long 0x0 "ENIR,Enable Interrupt Request Register" bitfld.long 0x00 23. " EN23 ,External interrupt enable bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " EN22 ,External interrupt enable bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " EN21 ,External interrupt enable bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " EN20 ,External interrupt enable bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " EN19 ,External interrupt enable bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " EN18 ,External interrupt enable bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " EN17 ,External interrupt enable bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " EN16 ,External interrupt enable bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.long 0x00 13. " EN13 ,External interrupt enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " EN12 ,External interrupt enable bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " EN11 ,External interrupt enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " EN10 ,External interrupt enable bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " EN9 ,External interrupt enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " EN8 ,External interrupt enable bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.long 0x4++0x3 line.long 0x0 "EIRR,External Interrupt Request Register" bitfld.long 0x00 23. " ER23 ,External interrupt request detection bit 23" "No interrupt,Interrupt" bitfld.long 0x00 22. " ER22 ,External interrupt request detection bit 22" "No interrupt,Interrupt" bitfld.long 0x00 21. " ER21 ,External interrupt request detection bit 21" "No interrupt,Interrupt" bitfld.long 0x00 20. " ER20 ,External interrupt request detection bit 20" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " ER19 ,External interrupt request detection bit 19" "No interrupt,Interrupt" bitfld.long 0x00 18. " ER18 ,External interrupt request detection bit 18" "No interrupt,Interrupt" bitfld.long 0x00 17. " ER17 ,External interrupt request detection bit 17" "No interrupt,Interrupt" bitfld.long 0x00 16. " ER16 ,External interrupt request detection bit 16" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.long 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.long 0x00 13. " ER13 ,External interrupt request detection bit 13" "No interrupt,Interrupt" bitfld.long 0x00 12. " ER12 ,External interrupt request detection bit 12" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " ER11 ,External interrupt request detection bit 11" "No interrupt,Interrupt" bitfld.long 0x00 10. " ER10 ,External interrupt request detection bit 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " ER9 ,External interrupt request detection bit 9" "No interrupt,Interrupt" bitfld.long 0x00 8. " ER8 ,External interrupt request detection bit 8" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" bitfld.long 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.long 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.long 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.long 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.long 0x8++0x3 line.long 0x0 "EICL,External Interrupt Clear Register" bitfld.long 0x00 23. " ECL23 ,External interrupt cause clear bit 23" "Clear,No effect" bitfld.long 0x00 22. " ECL22 ,External interrupt cause clear bit 22" "Clear,No effect" bitfld.long 0x00 21. " ECL21 ,External interrupt cause clear bit 21" "Clear,No effect" bitfld.long 0x00 20. " ECL20 ,External interrupt cause clear bit 20" "Clear,No effect" textline " " bitfld.long 0x00 19. " ECL19 ,External interrupt cause clear bit 19" "Clear,No effect" bitfld.long 0x00 18. " ECL18 ,External interrupt cause clear bit 18" "Clear,No effect" bitfld.long 0x00 17. " ECL17 ,External interrupt cause clear bit 17" "Clear,No effect" bitfld.long 0x00 16. " ECL16 ,External interrupt cause clear bit 16" "Clear,No effect" textline " " bitfld.long 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.long 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.long 0x00 13. " ECL13 ,External interrupt cause clear bit 13" "Clear,No effect" bitfld.long 0x00 12. " ECL12 ,External interrupt cause clear bit 12" "Clear,No effect" textline " " bitfld.long 0x00 11. " ECL11 ,External interrupt cause clear bit 11" "Clear,No effect" bitfld.long 0x00 10. " ECL10 ,External interrupt cause clear bit 10" "Clear,No effect" bitfld.long 0x00 9. " ECL9 ,External interrupt cause clear bit 9" "Clear,No effect" bitfld.long 0x00 8. " ECL8 ,External interrupt cause clear bit 8" "Clear,No effect" textline " " bitfld.long 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" bitfld.long 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.long 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.long 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" textline " " bitfld.long 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.long 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.long 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.long 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B13 ,External interrupt request detection level selection bit 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B12 ,External interrupt request detection level selection bit 12" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 22.--23. " LA/B11 ,External interrupt request detection level selection bit 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B10 ,External interrupt request detection level selection bit 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 18.--19. " LA/B9 ,External interrupt request detection level selection bit 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B8 ,External interrupt request detection level selection bit 8" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" group.long 0x10++0x3 line.long 0x0 "ELVR1,External Interrupt Level Register 1" bitfld.long 0x0 14.--15. " LA/B23 ,External interrupt request detection level selection bit 23" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B22 ,External interrupt request detection level selection bit 22" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B21 ,External interrupt request detection level selection bit 21" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B20 ,External interrupt request detection level selection bit 20" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B19 ,External interrupt request detection level selection bit 19" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B18 ,External interrupt request detection level selection bit 18" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B17 ,External interrupt request detection level selection bit 17" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B16 ,External interrupt request detection level selection bit 16" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9AFAA?L")||cpuis("MB9AF1A?L")) group.word 0x0++0x1 line.word 0x0 "ENIR,Enable Interrupt Request Register" bitfld.word 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.word 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.word 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.word 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.word 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.word 0x4++0x1 line.word 0x0 "EIRR,External Interrupt Request Register" bitfld.word 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.word 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.word 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.word 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" textline " " bitfld.word 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.word 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.word 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.word 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.word 0x8++0x1 line.word 0x0 "EICL,External Interrupt Clear Register" bitfld.word 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.word 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.word 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.word 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" textline " " bitfld.word 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.word 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.word 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.word 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9AFAA?M")||cpuis("MB9AF1A?M")) group.word 0x0++0x1 line.word 0x0 "ENIR,Enable Interrupt Request Register" bitfld.word 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.word 0x00 8. " EN8 ,External interrupt enable bit 8" "Disabled,Enabled" bitfld.word 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.word 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" bitfld.word 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.word 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.word 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.word 0x4++0x1 line.word 0x0 "EIRR,External Interrupt Request Register" bitfld.word 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.word 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.word 0x00 8. " ER8 ,External interrupt request detection bit 8" "No interrupt,Interrupt" bitfld.word 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" textline " " bitfld.word 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.word 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.word 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" bitfld.word 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" textline " " bitfld.word 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.word 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.word 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.word 0x8++0x1 line.word 0x0 "EICL,External Interrupt Clear Register" bitfld.word 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.word 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.word 0x00 8. " ECL8 ,External interrupt cause clear bit 8" "Clear,No effect" bitfld.word 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" textline " " bitfld.word 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.word 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.word 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" bitfld.word 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" textline " " bitfld.word 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.word 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.word 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B8 ,External interrupt request detection level selection bit 8" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" elif (cpuis("MB9AF13?K")) group.word 0x0++0x1 line.word 0x0 "ENIR,Enable Interrupt Request Register" bitfld.word 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.word 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.word 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.word 0x4++0x1 line.word 0x0 "EIRR,External Interrupt Request Register" bitfld.word 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.word 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.word 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.word 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.word 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.word 0x8++0x1 line.word 0x0 "EICL,External Interrupt Clear Register" bitfld.word 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.word 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.word 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.word 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" textline " " bitfld.word 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.word 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" else group.word 0x0++0x1 line.word 0x0 "ENIR,Enable Interrupt Request Register" bitfld.word 0x00 15. " EN15 ,External interrupt enable bit 15" "Disabled,Enabled" bitfld.word 0x00 14. " EN14 ,External interrupt enable bit 14" "Disabled,Enabled" bitfld.word 0x00 13. " EN13 ,External interrupt enable bit 13" "Disabled,Enabled" bitfld.word 0x00 12. " EN12 ,External interrupt enable bit 12" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " EN11 ,External interrupt enable bit 11" "Disabled,Enabled" bitfld.word 0x00 10. " EN10 ,External interrupt enable bit 10" "Disabled,Enabled" bitfld.word 0x00 9. " EN9 ,External interrupt enable bit 9" "Disabled,Enabled" bitfld.word 0x00 8. " EN8 ,External interrupt enable bit 8" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " EN7 ,External interrupt enable bit 7" "Disabled,Enabled" bitfld.word 0x00 6. " EN6 ,External interrupt enable bit 6" "Disabled,Enabled" bitfld.word 0x00 5. " EN5 ,External interrupt enable bit 5" "Disabled,Enabled" bitfld.word 0x00 4. " EN4 ,External interrupt enable bit 4" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " EN3 ,External interrupt enable bit 3" "Disabled,Enabled" bitfld.word 0x00 2. " EN2 ,External interrupt enable bit 2" "Disabled,Enabled" bitfld.word 0x00 1. " EN1 ,External interrupt enable bit 1" "Disabled,Enabled" bitfld.word 0x00 0. " EN0 ,External interrupt enable bit 0" "Disabled,Enabled" rgroup.word 0x4++0x1 line.word 0x0 "EIRR,External Interrupt Request Register" bitfld.word 0x00 15. " ER15 ,External interrupt request detection bit 15" "No interrupt,Interrupt" bitfld.word 0x00 14. " ER14 ,External interrupt request detection bit 14" "No interrupt,Interrupt" bitfld.word 0x00 13. " ER13 ,External interrupt request detection bit 13" "No interrupt,Interrupt" bitfld.word 0x00 12. " ER12 ,External interrupt request detection bit 12" "No interrupt,Interrupt" textline " " bitfld.word 0x00 11. " ER11 ,External interrupt request detection bit 11" "No interrupt,Interrupt" bitfld.word 0x00 10. " ER10 ,External interrupt request detection bit 10" "No interrupt,Interrupt" bitfld.word 0x00 9. " ER9 ,External interrupt request detection bit 9" "No interrupt,Interrupt" bitfld.word 0x00 8. " ER8 ,External interrupt request detection bit 8" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " ER7 ,External interrupt request detection bit 7" "No interrupt,Interrupt" bitfld.word 0x00 6. " ER6 ,External interrupt request detection bit 6" "No interrupt,Interrupt" bitfld.word 0x00 5. " ER5 ,External interrupt request detection bit 5" "No interrupt,Interrupt" bitfld.word 0x00 4. " ER4 ,External interrupt request detection bit 4" "No interrupt,Interrupt" textline " " bitfld.word 0x00 3. " ER3 ,External interrupt request detection bit 3" "No interrupt,Interrupt" bitfld.word 0x00 2. " ER2 ,External interrupt request detection bit 2" "No interrupt,Interrupt" bitfld.word 0x00 1. " ER1 ,External interrupt request detection bit 1" "No interrupt,Interrupt" bitfld.word 0x00 0. " ER0 ,External interrupt request detection bit 0" "No interrupt,Interrupt" wgroup.word 0x8++0x1 line.word 0x0 "EICL,External Interrupt Clear Register" bitfld.word 0x00 15. " ECL15 ,External interrupt cause clear bit 15" "Clear,No effect" bitfld.word 0x00 14. " ECL14 ,External interrupt cause clear bit 14" "Clear,No effect" bitfld.word 0x00 13. " ECL13 ,External interrupt cause clear bit 13" "Clear,No effect" bitfld.word 0x00 12. " ECL12 ,External interrupt cause clear bit 12" "Clear,No effect" textline " " bitfld.word 0x00 11. " ECL11 ,External interrupt cause clear bit 11" "Clear,No effect" bitfld.word 0x00 10. " ECL10 ,External interrupt cause clear bit 10" "Clear,No effect" bitfld.word 0x00 9. " ECL9 ,External interrupt cause clear bit 9" "Clear,No effect" bitfld.word 0x00 8. " ECL8 ,External interrupt cause clear bit 8" "Clear,No effect" textline " " bitfld.word 0x00 7. " ECL7 ,External interrupt cause clear bit 7" "Clear,No effect" bitfld.word 0x00 6. " ECL6 ,External interrupt cause clear bit 6" "Clear,No effect" bitfld.word 0x00 5. " ECL5 ,External interrupt cause clear bit 5" "Clear,No effect" bitfld.word 0x00 4. " ECL4 ,External interrupt cause clear bit 4" "Clear,No effect" textline " " bitfld.word 0x00 3. " ECL3 ,External interrupt cause clear bit 3" "Clear,No effect" bitfld.word 0x00 2. " ECL2 ,External interrupt cause clear bit 2" "Clear,No effect" bitfld.word 0x00 1. " ECL1 ,External interrupt cause clear bit 1" "Clear,No effect" bitfld.word 0x00 0. " ECL0 ,External interrupt cause clear bit 0" "Clear,No effect" group.long 0xC++0x3 line.long 0x0 "ELVR,External Interrupt Level Register" bitfld.long 0x0 30.--31. " LA/B15 ,External interrupt request detection level selection bit 15" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 28.--29. " LA/B14 ,External interrupt request detection level selection bit 14" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 26.--27. " LA/B13 ,External interrupt request detection level selection bit 13" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 24.--25. " LA/B12 ,External interrupt request detection level selection bit 12" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 22.--23. " LA/B11 ,External interrupt request detection level selection bit 11" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 20.--21. " LA/B10 ,External interrupt request detection level selection bit 10" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 18.--19. " LA/B9 ,External interrupt request detection level selection bit 9" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 16.--17. " LA/B8 ,External interrupt request detection level selection bit 8" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 14.--15. " LA/B7 ,External interrupt request detection level selection bit 7" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 12.--13. " LA/B6 ,External interrupt request detection level selection bit 6" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 10.--11. " LA/B5 ,External interrupt request detection level selection bit 5" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 8.--9. " LA/B4 ,External interrupt request detection level selection bit 4" "Low level,High level,Rising edge,Falling edge" textline " " bitfld.long 0x0 6.--7. " LA/B3 ,External interrupt request detection level selection bit 3" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 4.--5. " LA/B2 ,External interrupt request detection level selection bit 2" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 2.--3. " LA/B1 ,External interrupt request detection level selection bit 1" "Low level,High level,Rising edge,Falling edge" bitfld.long 0x0 0.--1. " LA/B0 ,External interrupt request detection level selection bit 0" "Low level,High level,Rising edge,Falling edge" rgroup.byte 0x14++0x0 line.byte 0x0 "NMIRR,Non Maskable Interrupt Request Register" bitfld.byte 0x0 0. " NR ,NMI request detection bit" "Not requested,Requested" group.byte 0x18++0x0 line.byte 0x0 "NMICL,Non Maskable Interrupt Clear Register" bitfld.byte 0x0 0. " NCL ,NMI interrupt cause clear bit" "Cleared,Not cleared" endif width 0xb endif tree.end sif (!cpuis("MB9AFAA1L")&&!cpuis("MB9AFAA1M")&&!cpuis("MB9AFAA1N")&&!cpuis("MB9AFAA2L")&&!cpuis("MB9AFAA2M")&&!cpuis("MB9AFAA2N")&&!cpuis("MB9AF131K")&&!cpuis("MB9AF131L")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF132L")&&!cpuis("MB9AF1A1L")&&!cpuis("MB9AF1A1M")&&!cpuis("MB9AF1A1N")&&!cpuis("MB9AF1A2L")&&!cpuis("MB9AF1A2M")&&!cpuis("MB9AF1A2N")&&!cpuis("MB9AF121K")&&!cpuis("MB9AF121L")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")) tree "DMAC" base ad:0x40060000 width 9. group.long 0x0++0x3 line.long 0x0 "DMACR,Entire DMAC Configuration Register" bitfld.long 0x00 31. " DE ,DMA Enable (all-channel operation enable bit)" "Disabled,Enabled" bitfld.long 0x00 30. " DS ,DMA Stop" "Not stopped,Stopped" bitfld.long 0x00 28. " PR ,Priority Rotation" "Fixed order,Rotation method" bitfld.long 0x00 24.--27. " DH ,DMA Halt (All-channel pause bit)" "Not paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused,Paused" tree "Configuration A Registers" sif (cpuis("MB9BF121J")) group.long 0x10++0x3 line.long 0x0 "DMACA0,Configuration A Register 0" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x20++0x3 line.long 0x0 "DMACA1,Configuration A Register 1" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x30++0x3 line.long 0x0 "DMACA2,Configuration A Register 2" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x40++0x3 line.long 0x0 "DMACA3,Configuration A Register 3" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" else group.long 0x10++0x3 line.long 0x0 "DMACA0,Configuration A Register 0" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x20++0x3 line.long 0x0 "DMACA1,Configuration A Register 1" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x30++0x3 line.long 0x0 "DMACA2,Configuration A Register 2" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x40++0x3 line.long 0x0 "DMACA3,Configuration A Register 3" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x50++0x3 line.long 0x0 "DMACA4,Configuration A Register 4" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x60++0x3 line.long 0x0 "DMACA5,Configuration A Register 5" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x70++0x3 line.long 0x0 "DMACA6,Configuration A Register 6" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" group.long 0x80++0x3 line.long 0x0 "DMACA7,Configuration A Register 7" bitfld.long 0x00 31. " EB ,Enable Bit" "Disabled,Enabled" bitfld.long 0x00 30. " PB ,Pause Bit" "Not paused,Paused" bitfld.long 0x00 29. " ST ,Software Trigger" "Hardware,Software" bitfld.long 0x00 23.--28. " IS ,Input Select" "Software,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,EP1 DRQ,EP2 DRQ,EP3 DRQ,EP4 DRQ,EP5 DRQ,ADC unit0,ADC unit1,ADC unit2,IRQ0 ch.0,IRQ0 ch.2,IRQ0 ch.4,IRQ0 ch.6,Receive MFS ch.0,Send MFS ch.0,Receive MFS ch.1,Send MFS ch.1,Receive MFS ch.2,Send MFS ch.2,Receive MFS ch.3,Send MFS ch.3,Receive MFS ch.4,Send MFS ch.4,Receive MFS ch.5,Send MFS ch.5,Receive MFS ch.6,Send MFS ch.6,Receive MFS ch.7,Send MFS ch.7,Ext. int. unit0,Ext. int. unit1,Ext. int. unit2,Ext. int. unit3" textline " " bitfld.long 0x00 16.--19. " BC ,Block Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. " TC ,Transfer Count" endif tree.end tree "Configuration B Registers" sif (cpuis("MB9BF121J")) group.long 0x14++0x3 line.long 0x0 "DMACB0,Configuration B Register 0" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x24++0x3 line.long 0x0 "DMACB1,Configuration B Register 1" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x34++0x3 line.long 0x0 "DMACB2,Configuration B Register 2" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x44++0x3 line.long 0x0 "DMACB3,Configuration B Register 3" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" else group.long 0x14++0x3 line.long 0x0 "DMACB0,Configuration B Register 0" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x24++0x3 line.long 0x0 "DMACB1,Configuration B Register 1" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x34++0x3 line.long 0x0 "DMACB2,Configuration B Register 2" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x44++0x3 line.long 0x0 "DMACB3,Configuration B Register 3" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "DMACB4,Configuration B Register 4" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x64++0x3 line.long 0x0 "DMACB5,Configuration B Register 5" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x74++0x3 line.long 0x0 "DMACB6,Configuration B Register 6" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" group.long 0x84++0x3 line.long 0x0 "DMACB7,Configuration B Register 7" bitfld.long 0x00 28.--29. " MS ,Mode Select" "Block transfer,Burst transfer,Demand transfer,?..." bitfld.long 0x00 26.--27. " TW ,Transfer Width" "Byte,Half-word,Word,?..." bitfld.long 0x00 25. " FS ,Fixed Source" "Not fixed,Fixed" bitfld.long 0x00 24. " FD ,Fixed Destination" "Not fixed,Fixed" textline " " bitfld.long 0x00 23. " RC ,Reload Count (BC/TC reload)" "Disabled,Enabled" bitfld.long 0x00 22. " RS ,Reload Source" "Disabled,Enabled" bitfld.long 0x00 21. " RD ,Reload Destination" "Disabled,Enabled" bitfld.long 0x00 20. " EI ,Error Interrupt (unsuccessful transfer completion interrupt enable)" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CI ,Completion Interrupt (successful transfer completion interrupt enable)" "Disabled,Enabled" bitfld.long 0x00 16.--18. " SS ,Stop Status (stop status notification)" "Initial value,Address overflow,Transfer stop request,Source access error,Destination access error,Transfer completed,,Transfer paused" bitfld.long 0x00 0. " EM ,Enable bit Mask (EB bit clear mask)" "Disabled,Enabled" endif tree.end tree "Transfer Source Address Registers" sif (cpuis("MB9BF121J")) group.long 0x18++0x3 line.long 0x0 "DMACSA0,Transfer Source Address Register0" group.long 0x28++0x3 line.long 0x0 "DMACSA1,Transfer Source Address Register1" group.long 0x38++0x3 line.long 0x0 "DMACSA2,Transfer Source Address Register2" group.long 0x48++0x3 line.long 0x0 "DMACSA3,Transfer Source Address Register3" else group.long 0x18++0x3 line.long 0x0 "DMACSA0,Transfer Source Address Register0" group.long 0x28++0x3 line.long 0x0 "DMACSA1,Transfer Source Address Register1" group.long 0x38++0x3 line.long 0x0 "DMACSA2,Transfer Source Address Register2" group.long 0x48++0x3 line.long 0x0 "DMACSA3,Transfer Source Address Register3" group.long 0x58++0x3 line.long 0x0 "DMACSA4,Transfer Source Address Register4" group.long 0x68++0x3 line.long 0x0 "DMACSA5,Transfer Source Address Register5" group.long 0x78++0x3 line.long 0x0 "DMACSA6,Transfer Source Address Register6" group.long 0x88++0x3 line.long 0x0 "DMACSA7,Transfer Source Address Register7" endif tree.end tree "Transfer Destination Address Registers" sif (cpuis("MB9BF121J")) group.long 0x1C++0x3 line.long 0x0 "DMACDA0,Transfer Destination Address Register0" group.long 0x2C++0x3 line.long 0x0 "DMACDA1,Transfer Destination Address Register1" group.long 0x3C++0x3 line.long 0x0 "DMACDA2,Transfer Destination Address Register2" group.long 0x4C++0x3 line.long 0x0 "DMACDA3,Transfer Destination Address Register3" else group.long 0x1C++0x3 line.long 0x0 "DMACDA0,Transfer Destination Address Register0" group.long 0x2C++0x3 line.long 0x0 "DMACDA1,Transfer Destination Address Register1" group.long 0x3C++0x3 line.long 0x0 "DMACDA2,Transfer Destination Address Register2" group.long 0x4C++0x3 line.long 0x0 "DMACDA3,Transfer Destination Address Register3" group.long 0x5C++0x3 line.long 0x0 "DMACDA4,Transfer Destination Address Register4" group.long 0x6C++0x3 line.long 0x0 "DMACDA5,Transfer Destination Address Register5" group.long 0x7C++0x3 line.long 0x0 "DMACDA6,Transfer Destination Address Register6" group.long 0x8C++0x3 line.long 0x0 "DMACDA7,Transfer Destination Address Register7" endif tree.end width 12. tree.end endif tree "I/O Ports" base ad:0x40033000 sif (cpuis("MB9AF???L")||cpuis("MB9AF???K")) width 8. tree "Port Function Setting Registers" group.long 0x0++0x3 line.long 0x00 "PFR0,Port Function Setting Register 0" bitfld.long 0x00 15. " P0F ,Pin 0F" "GPIO,Input/Output" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) textline " " bitfld.long 0x00 12. " P0C ,Pin 0C" "GPIO,Input/Output" bitfld.long 0x00 11. " P0B ,Pin 0B" "GPIO,Input/Output" bitfld.long 0x00 10. " P0A ,Pin 0A" "GPIO,Input/Output" endif textline " " bitfld.long 0x00 4. " P04 ,Pin 04" "GPIO,Input/Output" bitfld.long 0x00 3. " P03 ,Pin 03" "GPIO,Input/Output" bitfld.long 0x00 2. " P02 ,Pin 02" "GPIO,Input/Output" textline " " bitfld.long 0x00 1. " P01 ,Pin 01" "GPIO,Input/Output" bitfld.long 0x00 0. " P00 ,Pin 00" "GPIO,Input/Output" group.long 0x4++0x3 line.long 0x00 "PFR1,Port Function Setting Register 1" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x00 9. " P19 ,Pin 19" "GPIO,Input/Output" bitfld.long 0x00 8. " P18 ,Pin 18" "GPIO,Input/Output" bitfld.long 0x00 7. " P17 ,Pin 17" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 5. " P15 ,Pin 15" "GPIO,Input/Output" bitfld.long 0x00 4. " P14 ,Pin 14" "GPIO,Input/Output" bitfld.long 0x00 3. " P13 ,Pin 13" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P12 ,Pin 12" "GPIO,Input/Output" bitfld.long 0x00 1. " P11 ,Pin 11" "GPIO,Input/Output" bitfld.long 0x00 0. " P10 ,Pin 10" "GPIO,Input/Output" group.long 0x8++0x3 line.long 0x00 "PFR2,Port Function Setting Register 2" bitfld.long 0x00 3. " P23 ,Pin 23" "GPIO,Input/Output" bitfld.long 0x00 2. " P22 ,Pin 22" "GPIO,Input/Output" bitfld.long 0x00 1. " P21 ,Pin 21" "GPIO,Input/Output" group.long 0xC++0x3 line.long 0x00 "PFR3,Port Function Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "GPIO,Input/Output" bitfld.long 0x00 14. " P3E ,Pin 3E" "GPIO,Input/Output" bitfld.long 0x00 13. " P3D ,Pin 3D" "GPIO,Input/Output" textline " " bitfld.long 0x00 12. " P3C ,Pin 3C" "GPIO,Input/Output" bitfld.long 0x00 11. " P3B ,Pin 3B" "GPIO,Input/Output" bitfld.long 0x00 10. " P3A ,Pin 3A" "GPIO,Input/Output" textline " " bitfld.long 0x00 9. " P39 ,Pin 39" "GPIO,Input/Output" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) textline " " bitfld.long 0x00 3. " P33 ,Pin 33" "GPIO,Input/Output" bitfld.long 0x00 2. " P32 ,Pin 32" "GPIO,Input/Output" bitfld.long 0x00 1. " P31 ,Pin 31" "GPIO,Input/Output" textline " " bitfld.long 0x00 0. " P30 ,Pin 30" "GPIO,Input/Output" endif group.long 0x10++0x3 line.long 0x00 "PFR4,Port Function Setting Register 4" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x00 14. " P4E ,Pin 4E" "GPIO,Input/Output" bitfld.long 0x00 13. " P4D ,Pin 4D" "GPIO,Input/Output" bitfld.long 0x00 12. " P4C ,Pin 4C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P4B ,Pin 4B" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 10. " P4A ,Pin 4A" "GPIO,Input/Output" bitfld.long 0x00 9. " P49 ,Pin 49" "GPIO,Input/Output" bitfld.long 0x00 7. " P47 ,Pin 47" "GPIO,Input/Output" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "GPIO,Input/Output" group.long 0x14++0x3 line.long 0x00 "PFR5,Port Function Setting Register 5" bitfld.long 0x00 2. " P52 ,Pin 52" "GPIO,Input/Output" bitfld.long 0x00 1. " P51 ,Pin 51" "GPIO,Input/Output" bitfld.long 0x00 0. " P50 ,Pin 50" "GPIO,Input/Output" group.long 0x18++0x3 line.long 0x00 "PFR6,Port Function Setting Register 6" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x00 2. " P62 ,Pin 62" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 1. " P61 ,Pin 61" "GPIO,Input/Output" bitfld.long 0x00 0. " P60 ,Pin 60" "GPIO,Input/Output" group.long 0x20++0x3 line.long 0x00 "PFR8,Port Function Setting Register 8" sif cpuis("MB9AFA32L")||cpuis("MB9AFA31L")||cpuis("MB9AF421K")||cpuis("MB9AF121K")||cpuis("MB9AF421L")||cpuis("MB9AF121L") bitfld.long 0x00 2. " P82 ,Pin 82" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 1. " P81 ,Pin 81" "GPIO,Input/Output" bitfld.long 0x00 0. " P80 ,Pin 80" "GPIO,Input/Output" group.long 0x38++0x3 line.long 0x00 "PFRE,Port Function Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "GPIO,Input/Output" bitfld.long 0x00 2. " PE2 ,Pin E2" "GPIO,Input/Output" bitfld.long 0x00 0. " PE0 ,Pin E0" "GPIO,Input/Output" tree.end tree "Pull-up Setting Registers" group.long 0x100++0x3 line.long 0x0 "PCR0,Pull-up Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Disconnected,Connected" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 12. " P0C ,Pin 0C" "Disconnected,Connected" bitfld.long 0x0 11. " P0B ,Pin 0B" "Disconnected,Connected" bitfld.long 0x0 10. " P0A ,Pin 0A" "Disconnected,Connected" endif textline " " bitfld.long 0x0 4. " P04 ,Pin 04" "Disconnected,Connected" bitfld.long 0x0 3. " P03 ,Pin 03" "Disconnected,Connected" bitfld.long 0x0 2. " P02 ,Pin 02" "Disconnected,Connected" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Disconnected,Connected" bitfld.long 0x0 0. " P00 ,Pin 00" "Disconnected,Connected" group.long 0x104++0x3 line.long 0x0 "PCR1,Pull-up Setting Register 1" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 9. " P19 ,Pin 19" "Disconnected,Connected" bitfld.long 0x0 8. " P18 ,Pin 18" "Disconnected,Connected" bitfld.long 0x0 7. " P17 ,Pin 17" "Disconnected,Connected" textline " " endif bitfld.long 0x0 5. " P15 ,Pin 15" "Disconnected,Connected" bitfld.long 0x0 4. " P14 ,Pin 14" "Disconnected,Connected" bitfld.long 0x0 3. " P13 ,Pin 13" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P12 ,Pin 12" "Disconnected,Connected" bitfld.long 0x0 1. " P11 ,Pin 11" "Disconnected,Connected" bitfld.long 0x0 0. " P10 ,Pin 10" "Disconnected,Connected" group.long 0x108++0x3 line.long 0x0 "PCR2,Pull-up Setting Register 2" bitfld.long 0x0 3. " P23 ,Pin 23" "Disconnected,Connected" bitfld.long 0x0 2. " P22 ,Pin 22" "Disconnected,Connected" bitfld.long 0x0 1. " P21 ,Pin 21" "Disconnected,Connected" group.long 0x10C++0x3 line.long 0x0 "PCR3,Pull-up Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Disconnected,Connected" bitfld.long 0x0 14. " P3E ,Pin 3E" "Disconnected,Connected" bitfld.long 0x0 13. " P3D ,Pin 3D" "Disconnected,Connected" textline " " bitfld.long 0x0 12. " P3C ,Pin 3C" "Disconnected,Connected" bitfld.long 0x0 11. " P3B ,Pin 3B" "Disconnected,Connected" bitfld.long 0x0 10. " P3A ,Pin 3A" "Disconnected,Connected" textline " " bitfld.long 0x0 9. " P39 ,Pin 39" "Disconnected,Connected" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Disconnected,Connected" bitfld.long 0x0 2. " P32 ,Pin 32" "Disconnected,Connected" bitfld.long 0x0 1. " P31 ,Pin 31" "Disconnected,Connected" textline " " bitfld.long 0x0 0. " P30 ,Pin 30" "Disconnected,Connected" endif group.long 0x110++0x3 line.long 0x0 "PCR4,Pull-up Setting Register 4" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 14. " P4E ,Pin 4E" "Disconnected,Connected" bitfld.long 0x0 13. " P4D ,Pin 4D" "Disconnected,Connected" bitfld.long 0x0 12. " P4C ,Pin 4C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P4B ,Pin 4B" "Disconnected,Connected" textline " " endif bitfld.long 0x0 10. " P4A ,Pin 4A" "Disconnected,Connected" bitfld.long 0x0 9. " P49 ,Pin 49" "Disconnected,Connected" bitfld.long 0x0 7. " P47 ,Pin 47" "Disconnected,Connected" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Disconnected,Connected" group.long 0x114++0x3 line.long 0x0 "PCR5,Pull-up Setting Register 5" bitfld.long 0x0 2. " P52 ,Pin 52" "Disconnected,Connected" bitfld.long 0x0 1. " P51 ,Pin 51" "Disconnected,Connected" bitfld.long 0x0 0. " P50 ,Pin 50" "Disconnected,Connected" group.long 0x118++0x3 line.long 0x0 "PCR6,Pull-up Setting Register 6" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 2. " P62 ,Pin 62" "Disconnected,Connected" textline " " endif bitfld.long 0x0 1. " P61 ,Pin 61" "Disconnected,Connected" bitfld.long 0x0 0. " P60 ,Pin 60" "Disconnected,Connected" group.long 0x138++0x3 line.long 0x00 "PCRE,Pull-up Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Disconnected,Connected" bitfld.long 0x0 2. " PE2 ,Pin E2" "Disconnected,Connected" bitfld.long 0x0 0. " PE0 ,Pin E0" "Disconnected,Connected" tree.end tree "Port Input/output Direction Setting Registers" group.long 0x200++0x3 line.long 0x0 "DDR0,Port input/output Direction Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Input,Output" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 12. " P0C ,Pin 0C" "Input,Output" bitfld.long 0x0 11. " P0B ,Pin 0B" "Input,Output" bitfld.long 0x0 10. " P0A ,Pin 0A" "Input,Output" endif textline " " bitfld.long 0x0 4. " P04 ,Pin 04" "Input,Output" bitfld.long 0x0 3. " P03 ,Pin 03" "Input,Output" bitfld.long 0x0 2. " P02 ,Pin 02" "Input,Output" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Input,Output" bitfld.long 0x0 0. " P00 ,Pin 00" "Input,Output" group.long 0x204++0x3 line.long 0x0 "DDR1,Port input/output Direction Setting Register 1" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 9. " P19 ,Pin 19" "Input,Output" bitfld.long 0x0 8. " P18 ,Pin 18" "Input,Output" bitfld.long 0x0 7. " P17 ,Pin 17" "Input,Output" textline " " endif bitfld.long 0x0 5. " P15 ,Pin 15" "Input,Output" bitfld.long 0x0 4. " P14 ,Pin 14" "Input,Output" bitfld.long 0x0 3. " P13 ,Pin 13" "Input,Output" textline " " bitfld.long 0x0 2. " P12 ,Pin 12" "Input,Output" bitfld.long 0x0 1. " P11 ,Pin 11" "Input,Output" bitfld.long 0x0 0. " P10 ,Pin 10" "Input,Output" group.long 0x208++0x3 line.long 0x0 "DDR2,Port input/output Direction Setting Register 2" bitfld.long 0x0 3. " P23 ,Pin 23" "Input,Output" bitfld.long 0x0 2. " P22 ,Pin 22" "Input,Output" bitfld.long 0x0 1. " P21 ,Pin 21" "Input,Output" group.long 0x20C++0x3 line.long 0x0 "DDR3,Port input/output Direction Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Input,Output" bitfld.long 0x0 14. " P3E ,Pin 3E" "Input,Output" bitfld.long 0x0 13. " P3D ,Pin 3D" "Input,Output" textline " " bitfld.long 0x0 12. " P3C ,Pin 3C" "Input,Output" bitfld.long 0x0 11. " P3B ,Pin 3B" "Input,Output" bitfld.long 0x0 10. " P3A ,Pin 3A" "Input,Output" textline " " bitfld.long 0x0 9. " P39 ,Pin 39" "Input,Output" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Input,Output" bitfld.long 0x0 2. " P32 ,Pin 32" "Input,Output" bitfld.long 0x0 1. " P31 ,Pin 31" "Input,Output" textline " " bitfld.long 0x0 0. " P30 ,Pin 30" "Input,Output" endif group.long 0x210++0x3 line.long 0x0 "DDR4,Port input/output Direction Setting Register 4" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 14. " P4E ,Pin 4E" "Input,Output" bitfld.long 0x0 13. " P4D ,Pin 4D" "Input,Output" bitfld.long 0x0 12. " P4C ,Pin 4C" "Input,Output" textline " " bitfld.long 0x0 11. " P4B ,Pin 4B" "Input,Output" textline " " endif bitfld.long 0x0 10. " P4A ,Pin 4A" "Input,Output" bitfld.long 0x0 9. " P49 ,Pin 49" "Input,Output" bitfld.long 0x0 7. " P47 ,Pin 47" "Input,Output" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Input,Output" group.long 0x214++0x3 line.long 0x0 "DDR5,Port input/output Direction Setting Register 5" bitfld.long 0x0 2. " P52 ,Pin 52" "Input,Output" bitfld.long 0x0 1. " P51 ,Pin 51" "Input,Output" bitfld.long 0x0 0. " P50 ,Pin 50" "Input,Output" group.long 0x218++0x3 line.long 0x0 "DDR6,Port input/output Direction Setting Register 6" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 2. " P62 ,Pin 62" "Input,Output" textline " " endif bitfld.long 0x0 1. " P61 ,Pin 61" "Input,Output" bitfld.long 0x0 0. " P60 ,Pin 60" "Input,Output" group.long 0x220++0x3 line.long 0x0 "DDR8,Port input/output Direction Setting Register 8" sif cpuis("MB9AFA32L")||cpuis("MB9AFA31L")||cpuis("MB9AF421K")||cpuis("MB9AF121K")||cpuis("MB9AF421L")||cpuis("MB9AF121L") bitfld.long 0x00 2. " P82 ,Pin 82" "Input,Output" textline " " endif bitfld.long 0x0 1. " P81 ,Pin 81" "Input,Output" bitfld.long 0x0 0. " P80 ,Pin 80" "Input,Output" group.long 0x238++0x3 line.long 0x0 "DDRE,Port input/output Direction Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Input,Output" bitfld.long 0x0 2. " PE2 ,Pin E2" "Input,Output" bitfld.long 0x0 0. " PE0 ,Pin E0" "Input,Output" tree.end tree "Port Input Data Registers" rgroup.long 0x300++0x3 line.long 0x0 "PDIR0,Port Input Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" endif textline " " bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" rgroup.long 0x304++0x3 line.long 0x0 "PDIR1,Port Input Data Register 1" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" textline " " endif bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" textline " " bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" rgroup.long 0x308++0x3 line.long 0x0 "PDIR2,Port Input Data Register 2" bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" rgroup.long 0x30C++0x3 line.long 0x0 "PDIR3,Port Input Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" textline " " bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" textline " " bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" textline " " bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" endif rgroup.long 0x310++0x3 line.long 0x0 "PDIR4,Port Input Data Register 4" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" textline " " bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " endif bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" rgroup.long 0x314++0x3 line.long 0x0 "PDIR5,Port Input Data Register 5" bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" rgroup.long 0x318++0x3 line.long 0x0 "PDIR6,Port Input Data Register 6" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" textline " " endif bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" rgroup.long 0x320++0x3 line.long 0x0 "PDIR8,Port Input Data Register 8" sif cpuis("MB9AFA32L")||cpuis("MB9AFA31L")||cpuis("MB9AF421K")||cpuis("MB9AF121K")||cpuis("MB9AF421L")||cpuis("MB9AF121L") bitfld.long 0x00 2. " P82 ,Pin 82" "Low,High" textline " " endif bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" rgroup.long 0x338++0x3 line.long 0x0 "PDIRE,Port Input Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" tree.end tree "Port Output Data Registers" group.long 0x400++0x3 line.long 0x0 "PDOR0,Port Output Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" endif textline " " bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" group.long 0x404++0x3 line.long 0x0 "PDOR1,Port Output Data Register 1" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" textline " " endif bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" textline " " bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" group.long 0x408++0x3 line.long 0x0 "PDOR2,Port Output Data Register 2" bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" group.long 0x40C++0x3 line.long 0x0 "PDOR3,Port Output Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" textline " " bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" textline " " bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" textline " " bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" endif group.long 0x410++0x3 line.long 0x0 "PDOR4,Port Output Data Register 4" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" textline " " bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " endif bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" group.long 0x414++0x3 line.long 0x0 "PDOR5,Port Output Data Register 5" bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" group.long 0x418++0x3 line.long 0x0 "PDOR6,Port Output Data Register 6" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")||cpuis("MB9AF121L")||cpuis("MB9AF421L")) bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" textline " " endif bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" group.long 0x420++0x3 line.long 0x0 "PDOR8,Port Output Data Register 8" sif cpuis("MB9AFA32L")||cpuis("MB9AFA31L")||cpuis("MB9AF421K")||cpuis("MB9AF121K")||cpuis("MB9AF421L")||cpuis("MB9AF121L") bitfld.long 0x00 2. " P82 ,Pin 82" "Low,High" textline " " endif bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" group.long 0x438++0x3 line.long 0x0 "PDORE,Port Output Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" tree.end tree "Analog Input Setting Register" group.long 0x500++0x3 line.long 0x0 "ADE,Analog Input Setting Register" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x0 9. " ADE19 ,Analog signal input pin 19 enable" "Digital I/O,Analog IN" bitfld.long 0x0 8. " ADE18 ,Analog signal input pin 18 enable" "Digital I/O,Analog IN" textline " " endif bitfld.long 0x0 7. " ADE17 ,Analog signal input pin 17 enable" "Digital I/O,Analog IN" textline " " sif (cpuis("MB9AF???K")) bitfld.long 0x0 6. " ADE16 ,Analog signal input pin 16 enable" "Digital I/O,Analog IN" textline " " endif bitfld.long 0x0 5. " ADE15 ,Analog signal input pin 15 enable" "Digital I/O,Analog IN" bitfld.long 0x0 4. " ADE14 ,Analog signal input pin 14 enable" "Digital I/O,Analog IN" bitfld.long 0x0 3. " ADE13 ,Analog signal input pin 13 enable" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 2. " ADE12 ,Analog signal input pin 12 enable" "Digital I/O,Analog IN" bitfld.long 0x0 1. " ADE11 ,Analog signal input pin 11 enable" "Digital I/O,Analog IN" bitfld.long 0x0 0. " ADE10 ,Analog signal input pin 10 enable" "Digital I/O,Analog IN" tree.end tree "Extended Pin Function Setting Register" group.long 0x600++0x3 line.long 0x0 "EPFR00,Extended Pin Function Setting Register 00" bitfld.long 0x00 17. " JTAGEN1S ,Selects whether to use two pins of TRSTX and TDI" "Not used,Used" bitfld.long 0x00 16. " JTAGEN0S ,Selects whether to use three pins of TCK, TMS, and TDO" "Not used,Used" textline " " sif (cpuis("MB9AF31?L")||cpuis("MB9AF31?K")||cpuis("MB9AFB4?L")||cpuis("MB9AF34?L")) bitfld.long 0x00 9. " USBP0E ,Selects whether to produce output D+ resistor control signal (HCONTX) for USB ch.0" "Not produced,Produced" textline " " endif sif (cpuis("MB9AF31?K")||cpuis("MB9AF11?K")||cpuis("MB9AF13?K")||cpuis("MB9AF13?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF34?L")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")) bitfld.long 0x00 6.--7. " SUBOUTE ,Selects sub clock divide output" "Not executed,SUBOUT_0,SUBOUT_1,SUBOUT_2" bitfld.long 0x00 4.--5. " RTCCOE ,Selects a RTC clock output" "Not executed,RTCCOE_0,RTCCOE_1,RTCCOE_2" textline " " endif bitfld.long 0x00 1.--2. " CROUTE ,Selects internal high-speed CR oscillation output" "Not produced,,CROUT_1,?..." bitfld.long 0x00 0. " NMIS ,Select whether to use the NMIX pin" "Not used,Used" sif (cpuis("MB9AF31?L")||cpuis("MB9AF31?K")||cpuis("MB9AFA3?L")||cpuis("MB9AF13?K")||cpuis("MB9AF11?K")) group.long 0x604++0x3 line.long 0x0 "EPFR01,Extended Pin Function Setting Register 01" sif (cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")) bitfld.long 0x00 29.--31. " IC03S ,IC03 Input Select Bit" ",,,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x00 26.--28. " IS02S ,IC02 Input Select Bit" ",,,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." textline " " bitfld.long 0x00 23.--25. " IC01S ,IC01 Input Select Bit" ",,,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x00 20.--22. " IC00S ,IC00 Input Select Bit" ",,,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " elif (cpuis("MB9AF31?K")||cpuis("MB9AF13?L")||cpuis("MB9AF13?K")||cpuis("MB9AF11?K")) bitfld.long 0x00 29.--31. " IC03S ,IC03 Input Select Bit" ",,,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x00 26.--28. " IS02S ,IC02 Input Select Bit" "IC02_0,,,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." textline " " bitfld.long 0x00 23.--25. " IC01S ,IC01 Input Select Bit" ",,,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x00 20.--22. " IC00S ,IC00 Input Select Bit" "IC00_0,,,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " endif sif (cpuis("MB9AF31?L")) bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" ",,,FRCK0_2" bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,?..." textline " " bitfld.long 0x00 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" textline " " elif (cpuis("MB9AF31?K")||cpuis("MB9AFA3?L")||cpuis("MB9AF13?K")||cpuis("MB9AF11?K")) bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" ",,,FRCK0_2" bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,,DTTIX0_2" textline " " bitfld.long 0x00 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" textline " " endif bitfld.long 0x00 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,?..." bitfld.long 0x00 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,?..." textline " " bitfld.long 0x00 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,?..." bitfld.long 0x00 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,?..." textline " " bitfld.long 0x00 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,?..." bitfld.long 0x00 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,?..." endif group.long 0x610++0x17 line.long 0x0 "EPFR04,Extended Pin Function Setting Register 04" sif (cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF13?L")||cpuis("MB9AF11?L")||cpuis("MB9AF14?L")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")) bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,TIOB3_1,?..." bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,,TIOA3_1,?..." bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" ",,TIOA3_1,?..." textline " " bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2" bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" ",,TIOA2_1,TIOA2_2" textline " " bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,TIOB1_1,?..." bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,,TIOA1_1,?..." bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" ",,TIOA1_1,?..." textline " " sif (cpuis("MB9AFA3?L")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,,,,SUBOUT,?..." elif (cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF14?L")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,,,,,Measuring pin" else bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,?..." endif textline " " bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,,TIOA0_1,?..." elif (cpuis("MB9AF31?K")||cpuis("MB9AF13?K")||cpuis("MB9AF11?K")) bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,,TIOA3_1,?..." bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" ",,TIOA3_1,?..." textline " " bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" ",,,TIOB2_2" bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" ",,TIOA2_1,TIOA2_2" textline " " bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB0_0,TIOB0_0,?..." bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,,TIOA1_1,?..." bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" ",,TIOA1_1,?..." textline " " sif (cpuis("MB9AF13?K")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,,,,,,Measuring pin" else bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,?..." endif textline " " bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,,TIOA0_1,?..." endif line.long 0x4 "EPFR05,Extended Pin Function Setting Register 05" sif (cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF13?L")||cpuis("MB9AF11?L")||cpuis("MB9AF14?L")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,?..." bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,?..." bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,?..." textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" ",,TIOB6_1,?..." bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,,TIOA6_1,?..." textline " " bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,?..." bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,,TIOA5_1,?..." bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" ",,TIOA5_1,?..." textline " " bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,?..." bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,,TIOA4_1,?..." elif (cpuis("MB9AF13?K")||cpuis("MB9AF11?K")||cpuis("MB9AF31?K")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,?..." bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,?..." bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,?..." textline " " bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,,TIOA5_1,?..." bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" ",,TIOA5_1,?..." textline " " bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,,TIOA4_1,?..." endif line.long 0x8 "EPFR06,Extended Pin Function Setting Register 06" sif (cpuis("MB9AF31?L")||cpuis("MB9AF13?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,?..." bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" ",,INT06_1,INT06_2" bitfld.long 0x08 10.--11. " EINT05S ,External Interrupt Input 5 Select Bit" ",,,INT05_2" textline " " bitfld.long 0x08 8.--9. " EINT04S ,External Interrupt Input 4 Select Bit" "INT04_0,INT04_0,INT04_1,INT04_2" bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" ",,INT03_1,INT03_2" bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,?..." textline " " bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,?..." bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,,INT00_2" elif (cpuis("MB9AF31?K")||cpuis("MB9AF13?K")||cpuis("MB9AF11?K")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,?..." bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" ",,INT06_1,?..." textline " " bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" ",,INT03_1,?..." bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,?..." bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,?..." textline " " bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,?..." endif line.long 0xC "EPFR07,Extended Pin Function Setting Register 07" sif (cpuis("MB9AF31?L")||cpuis("MB9AF14?L")||cpuis("MB9AF13?L")||cpuis("MB9AF11?L")||cpuis("MB9AF34?L")||cpuis("MB9AFA3?L")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "/Not produced,,SCK3_1/SCK3_1,?..." bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "/Not produced,,SOT3_1/SOT3_1,?..." bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" ",,SIN3_1,?..." textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "/Not produced,,,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "/Not produced,,,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" ",,,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "/Not produced,,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "/Not produced,,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" ",,SIN1_1,?..." textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,?..." elif (cpuis("MB9AF31?K")||cpuis("MB9AF11?K")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "/Not produced,,SCK3_1/SCK3_1,?..." bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "/Not produced,,SOT3_1/SOT3_1,?..." bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" ",,SIN3_1,?..." textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "/Not produced,,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "/Not produced,,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" ",,SIN1_1,?..." textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,SOT0_1/SOT0_1,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,SIN0_1,?..." elif (cpuis("MB9AF13?K")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "/Not produced,,SCK3_1/SCK3_1,?..." bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "/Not produced,,SOT3_1/SOT3_1,?..." bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" ",,SIN3_1,?..." textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "/Not produced,,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "/Not produced,,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" ",,SIN1_1,?..." textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,?..." endif line.long 0x10 "EPFR08,Extended Pin Function Setting Register 08" sif (cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AF11?L")||cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AFA4?L")) bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "/Not produced,,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "/Not produced,,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" ",,SIN7_1,?..." textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "/Not produced,,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "/Not produced,,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" ",,SIN6_1,?..." textline " " bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,?..." bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,?..." bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,?..." textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,?..." bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,?..." bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,?..." elif (cpuis("MB9AFA3?L")) bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "/Not produced,,SCK7_1/SCK7_1,SCK7_2/SCK7_2" bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "/Not produced,,SOT7_1/SOT7_1,SOT7_2/SOT7_2" bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" ",,SIN7_1,SIN7_2" textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "/Not produced,,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "/Not produced,,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" ",,SIN6_1,?..." textline " " bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,?..." bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,?..." bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,?..." textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,?..." bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,?..." bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,?..." elif (cpuis("MB9AF11?K")||cpuis("MB9AF13?K")||cpuis("MB9AF31?K")) bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,?..." bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,?..." endif line.long 0x14 "EPFR09,Extended Pin Function Setting Register 09" sif (cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AF11?L")||cpuis("MB9AF14?L")||cpuis("MB9AFA3?L")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")) bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" ",,,ADTG_2,ADTG_3,,,ADTG_6,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" ",,,ADTG_2,ADTG_3,,,ADTG_6,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" ",,,ADTG_2,ADTG_3,,,ADTG_6,?..." elif (cpuis("MB9AF11?K")||cpuis("MB9AF13?K")||cpuis("MB9AF31?K")) bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" ",,,ADTG_2,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" ",,,ADTG_2,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" ",,,ADTG_2,?..." endif sif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")) textline " " bitfld.long 0x14 10.--11. " QZIN1S ,Select input for QPRC ZIN1" ",,,ZIN1_2" bitfld.long 0x14 8.--9. " QBIN1S ,Select input for QPRC BIN1" ",,,BIN1_2" bitfld.long 0x14 6.--7. " QAIN1S ,Select input for QPRC AIN1" ",,,AIN1_2" textline " " bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" "BIN0_0,BIN0_0,BIN0_1,BIN0_2" bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" "AIN0_0,AIN0_0,AIN0_1,AIN0_2" elif (cpuis("MB9AF11?K")||cpuis("MB9AF31?K")) textline " " bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" ",,,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" ",,,BIN0_2" bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" ",,,AIN0_2" endif sif (cpuis("MB9AF34?L")||cpuis("MB9AF14?L")||cpuis("MB9AFA3?L")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")) group.long 0x38++0x3 line.long 0x00 "EPFR14,Extended Pin Function Setting Register 14" bitfld.long 0x00 31. " CEC1B ,Selects I/O for CEC1" "Not input/output,Input/output" bitfld.long 0x00 30. " CEC0B ,Selects I/O for CEC0" "Not input/output,Input/output" endif tree.end tree "Special Port Setting Register" group.long 0x580++0x3 line.long 0x0 "SPSR,Special Port Setting Register" sif (cpuis("MB9AF31?L")||cpuis("MB9AF31?K")||cpuis("MB9AFB4?L")||cpuis("MB9AF34?L")) bitfld.long 0x00 4. " USB0C ,USB (ch.0) Pin Setting Bit" "Not used,Used" textline " " endif bitfld.long 0x00 2. " MAINXC ,Main Clock (Oscillation) Pin Setting Bit" "Not used,Used" bitfld.long 0x00 0. " SUBXC ,Sub Clock (Oscillation) Pin Setting Bit" "Not used,Used" tree.end tree "Port Pseudo Open Drain Setting Registers" group.long 0x700++0x3 line.long 0x00 "PZR0,Port Pseudo Open Drain Setting Register 0" bitfld.long 0x00 15. " P0F ,Pin 0F" "High,Hi-Z" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) textline " " bitfld.long 0x00 12. " P0C ,Pin 0C" "High,Hi-Z" bitfld.long 0x00 11. " P0B ,Pin 0B" "High,Hi-Z" bitfld.long 0x00 10. " P0A ,Pin 0A" "High,Hi-Z" endif textline " " bitfld.long 0x00 4. " P04 ,Pin 04" "High,Hi-Z" bitfld.long 0x00 3. " P03 ,Pin 03" "High,Hi-Z" bitfld.long 0x00 2. " P02 ,Pin 02" "High,Hi-Z" textline " " bitfld.long 0x00 1. " P01 ,Pin 01" "High,Hi-Z" bitfld.long 0x00 0. " P00 ,Pin 00" "High,Hi-Z" group.long 0x704++0x3 line.long 0x00 "PZR1,Port Pseudo Open Drain Setting Register 1" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x00 9. " P19 ,Pin 19" "High,Hi-Z" bitfld.long 0x00 8. " P18 ,Pin 18" "High,Hi-Z" bitfld.long 0x00 7. " P17 ,Pin 17" "High,Hi-Z" textline " " endif bitfld.long 0x00 5. " P15 ,Pin 15" "High,Hi-Z" bitfld.long 0x00 4. " P14 ,Pin 14" "High,Hi-Z" bitfld.long 0x00 3. " P13 ,Pin 13" "High,Hi-Z" textline " " bitfld.long 0x00 2. " P12 ,Pin 12" "High,Hi-Z" bitfld.long 0x00 1. " P11 ,Pin 11" "High,Hi-Z" bitfld.long 0x00 0. " P10 ,Pin 10" "High,Hi-Z" group.long 0x708++0x3 line.long 0x00 "PZR2,Port Pseudo Open Drain Setting Register 2" bitfld.long 0x00 3. " P23 ,Pin 23" "High,Hi-Z" bitfld.long 0x00 2. " P22 ,Pin 22" "High,Hi-Z" bitfld.long 0x00 1. " P21 ,Pin 21" "High,Hi-Z" group.long 0x70C++0x3 line.long 0x00 "PZR3,Port Pseudo Open Drain Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "High,Hi-Z" bitfld.long 0x00 14. " P3E ,Pin 3E" "High,Hi-Z" bitfld.long 0x00 13. " P3D ,Pin 3D" "High,Hi-Z" textline " " bitfld.long 0x00 12. " P3C ,Pin 3C" "High,Hi-Z" bitfld.long 0x00 11. " P3B ,Pin 3B" "High,Hi-Z" bitfld.long 0x00 10. " P3A ,Pin 3A" "High,Hi-Z" textline " " bitfld.long 0x00 9. " P39 ,Pin 39" "High,Hi-Z" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) textline " " bitfld.long 0x00 3. " P33 ,Pin 33" "High,Hi-Z" bitfld.long 0x00 2. " P32 ,Pin 32" "High,Hi-Z" bitfld.long 0x00 1. " P31 ,Pin 31" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P30 ,Pin 30" "High,Hi-Z" endif group.long 0x710++0x3 line.long 0x00 "PZR4,Port Pseudo Open Drain Setting Register 4" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x00 14. " P4E ,Pin 4E" "High,Hi-Z" bitfld.long 0x00 13. " P4D ,Pin 4D" "High,Hi-Z" bitfld.long 0x00 12. " P4C ,Pin 4C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P4B ,Pin 4B" "High,Hi-Z" textline " " endif bitfld.long 0x00 10. " P4A ,Pin 4A" "High,Hi-Z" bitfld.long 0x00 9. " P49 ,Pin 49" "High,Hi-Z" bitfld.long 0x00 7. " P47 ,Pin 47" "High,Hi-Z" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "High,Hi-Z" group.long 0x714++0x3 line.long 0x00 "PZR5,Port Pseudo Open Drain Setting Register 5" bitfld.long 0x00 2. " P52 ,Pin 52" "High,Hi-Z" bitfld.long 0x00 1. " P51 ,Pin 51" "High,Hi-Z" bitfld.long 0x00 0. " P50 ,Pin 50" "High,Hi-Z" group.long 0x718++0x3 line.long 0x00 "PZR6,Port Pseudo Open Drain Setting Register 6" sif (cpuis("MB9AF13?L")||cpuis("MB9AF14?L")||cpuis("MB9AF11?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF14?L")||cpuis("MB9AF31?L")||cpuis("MB9AF34?L")||cpuis("MB9AFB4?L")||cpuis("MB9AFA4?L")) bitfld.long 0x00 2. " P62 ,Pin 62" "High,Hi-Z" textline " " endif bitfld.long 0x00 1. " P61 ,Pin 61" "High,Hi-Z" bitfld.long 0x00 0. " P60 ,Pin 60" "High,Hi-Z" group.long 0x720++0x3 line.long 0x00 "PZR8,Port Pseudo Open Drain Setting Register 8" sif cpuis("MB9AFA32L")||cpuis("MB9AFA31L") bitfld.long 0x00 2. " P82 ,Pin 82" "High,Hi-Z" textline " " endif bitfld.long 0x00 1. " P81 ,Pin 81" "High,Hi-Z" bitfld.long 0x00 0. " P80 ,Pin 80" "High,Hi-Z" group.long 0x738++0x3 line.long 0x00 "PZRE,Port Pseudo Open Drain Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "High,Hi-Z" bitfld.long 0x00 2. " PE2 ,Pin E2" "High,Hi-Z" bitfld.long 0x00 0. " PE0 ,Pin E0" "High,Hi-Z" tree.end width 12. elif (cpuis("MB9AF???M")||cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AFB10?RA")) width 8. tree "Port Function Setting Registers" group.long 0x0++0x3 line.long 0x00 "PFR0,Port Function Setting Register 0" bitfld.long 0x00 15. " P0F ,Pin 0F" "GPIO,Input/Output" bitfld.long 0x00 14. " P0E ,Pin 0E" "GPIO,Input/Output" bitfld.long 0x00 13. " P0D ,Pin 0D" "GPIO,Input/Output" bitfld.long 0x00 12. " P0C ,Pin 0C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P0B ,Pin 0B" "GPIO,Input/Output" bitfld.long 0x00 10. " P0A ,Pin 0A" "GPIO,Input/Output" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 9. " P09 ,Pin 09" "GPIO,Input/Output" bitfld.long 0x00 8. " P08 ,Pin 08" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 7. " P07 ,Pin 07" "GPIO,Input/Output" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 6. " P06 ,Pin 06" "GPIO,Input/Output" bitfld.long 0x00 5. " P05 ,Pin 05" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 4. " P04 ,Pin 04" "GPIO,Input/Output" bitfld.long 0x00 3. " P03 ,Pin 03" "GPIO,Input/Output" bitfld.long 0x00 2. " P02 ,Pin 02" "GPIO,Input/Output" bitfld.long 0x00 1. " P01 ,Pin 01" "GPIO,Input/Output" textline " " bitfld.long 0x00 0. " P00 ,Pin 00" "GPIO,Input/Output" group.long 0x4++0x3 line.long 0x00 "PFR1,Port Function Setting Register 1" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 15. " P1F ,Pin 1F" "GPIO,Input/Output" bitfld.long 0x00 14. " P1E ,Pin 1E" "GPIO,Input/Output" bitfld.long 0x00 13. " P1D ,Pin 1D" "GPIO,Input/Output" bitfld.long 0x00 12. " P1C ,Pin 1C" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 11. " P1B ,Pin 1B" "GPIO,Input/Output" bitfld.long 0x00 10. " P1A ,Pin 1A" "GPIO,Input/Output" bitfld.long 0x00 9. " P19 ,Pin 19" "GPIO,Input/Output" bitfld.long 0x00 8. " P18 ,Pin 18" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P17 ,Pin 17" "GPIO,Input/Output" bitfld.long 0x00 6. " P16 ,Pin 16" "GPIO,Input/Output" bitfld.long 0x00 5. " P15 ,Pin 15" "GPIO,Input/Output" bitfld.long 0x00 4. " P14 ,Pin 14" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P13 ,Pin 13" "GPIO,Input/Output" bitfld.long 0x00 2. " P12 ,Pin 12" "GPIO,Input/Output" bitfld.long 0x00 1. " P11 ,Pin 11" "GPIO,Input/Output" bitfld.long 0x00 0. " P10 ,Pin 10" "GPIO,Input/Output" group.long 0x8++0x3 line.long 0x00 "PFR2,Port Function Setting Register 2" sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 8. " P28 ,Pin 28" "GPIO,Input/Output" bitfld.long 0x00 7. " P27 ,Pin 27" "GPIO,Input/Output" bitfld.long 0x00 6. " P26 ,Pin 26" "GPIO,Input/Output" bitfld.long 0x00 5. " P25 ,Pin 25" "GPIO,Input/Output" textline " " bitfld.long 0x00 4. " P24 ,Pin 24" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 3. " P23 ,Pin 23" "GPIO,Input/Output" bitfld.long 0x00 2. " P22 ,Pin 22" "GPIO,Input/Output" bitfld.long 0x00 1. " P21 ,Pin 21" "GPIO,Input/Output" bitfld.long 0x00 0. " P20 ,Pin 20" "GPIO,Input/Output" group.long 0xC++0x3 line.long 0x00 "PFR3,Port Function Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "GPIO,Input/Output" bitfld.long 0x00 14. " P3E ,Pin 3E" "GPIO,Input/Output" bitfld.long 0x00 13. " P3D ,Pin 3D" "GPIO,Input/Output" bitfld.long 0x00 12. " P3C ,Pin 3C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P3B ,Pin 3B" "GPIO,Input/Output" bitfld.long 0x00 10. " P3A ,Pin 3A" "GPIO,Input/Output" bitfld.long 0x00 9. " P39 ,Pin 39" "GPIO,Input/Output" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 8. " P38 ,Pin 38" "GPIO,Input/Output" bitfld.long 0x00 7. " P37 ,Pin 37" "GPIO,Input/Output" bitfld.long 0x00 6. " P36 ,Pin 36" "GPIO,Input/Output" bitfld.long 0x00 5. " P35 ,Pin 35" "GPIO,Input/Output" textline " " bitfld.long 0x00 4. " P34 ,Pin 34" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 3. " P33 ,Pin 33" "GPIO,Input/Output" bitfld.long 0x00 2. " P32 ,Pin 32" "GPIO,Input/Output" bitfld.long 0x00 1. " P31 ,Pin 31" "GPIO,Input/Output" bitfld.long 0x00 0. " P30 ,Pin 30" "GPIO,Input/Output" group.long 0x10++0x3 line.long 0x00 "PFR4,Port Function Setting Register 4" ; bitfld.long 0x00 15. " P4F ,Pin 4F" "GPIO,Input/Output" bitfld.long 0x00 14. " P4E ,Pin 4E" "GPIO,Input/Output" bitfld.long 0x00 13. " P4D ,Pin 4D" "GPIO,Input/Output" bitfld.long 0x00 12. " P4C ,Pin 4C" "GPIO,Input/Output" bitfld.long 0x00 11. " P4B ,Pin 4B" "GPIO,Input/Output" textline " " bitfld.long 0x00 10. " P4A ,Pin 4A" "GPIO,Input/Output" bitfld.long 0x00 9. " P49 ,Pin 49" "GPIO,Input/Output" bitfld.long 0x00 8. " P48 ,Pin 48" "GPIO,Input/Output" bitfld.long 0x00 7. " P47 ,Pin 47" "GPIO,Input/Output" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "GPIO,Input/Output" bitfld.long 0x00 5. " P45 ,Pin 45" "GPIO,Input/Output" bitfld.long 0x00 4. " P44 ,Pin 44" "GPIO,Input/Output" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) textline " " bitfld.long 0x00 3. " P43 ,Pin 43" "GPIO,Input/Output" bitfld.long 0x00 2. " P42 ,Pin 42" "GPIO,Input/Output" bitfld.long 0x00 1. " P41 ,Pin 41" "GPIO,Input/Output" bitfld.long 0x00 0. " P40 ,Pin 40" "GPIO,Input/Output" endif group.long 0x14++0x3 line.long 0x00 "PFR5,Port Function Setting Register 5" sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 11. " P5B ,Pin 5B" "GPIO,Input/Output" bitfld.long 0x00 10. " P5A ,Pin 5A" "GPIO,Input/Output" bitfld.long 0x00 9. " P59 ,Pin 59" "GPIO,Input/Output" bitfld.long 0x00 8. " P58 ,Pin 58" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P57 ,Pin 57" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 6. " P56 ,Pin 56" "GPIO,Input/Output" bitfld.long 0x00 5. " P55 ,Pin 55" "GPIO,Input/Output" bitfld.long 0x00 4. " P54 ,Pin 54" "GPIO,Input/Output" bitfld.long 0x00 3. " P53 ,Pin 53" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P52 ,Pin 52" "GPIO,Input/Output" bitfld.long 0x00 1. " P51 ,Pin 51" "GPIO,Input/Output" bitfld.long 0x00 0. " P50 ,Pin 50" "GPIO,Input/Output" group.long 0x18++0x3 line.long 0x00 "PFR6,Port Function Setting Register 6" sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 8. " P68 ,Pin 68" "GPIO,Input/Output" bitfld.long 0x00 7. " P67 ,Pin 67" "GPIO,Input/Output" bitfld.long 0x00 6. " P66 ,Pin 66" "GPIO,Input/Output" bitfld.long 0x00 5. " P65 ,Pin 65" "GPIO,Input/Output" textline " " bitfld.long 0x00 4. " P64 ,Pin 64" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 3. " P63 ,Pin 63" "GPIO,Input/Output" bitfld.long 0x00 2. " P62 ,Pin 62" "GPIO,Input/Output" bitfld.long 0x00 1. " P61 ,Pin 61" "GPIO,Input/Output" bitfld.long 0x00 0. " P60 ,Pin 60" "GPIO,Input/Output" sif (cpuis("MB9AF10?RA")) group.long 0x1C++0x3 line.long 0x00 "PFR7,Port Function Setting Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "GPIO,Input/Output" bitfld.long 0x00 3. " P73 ,Pin 73" "GPIO,Input/Output" bitfld.long 0x00 2. " P72 ,Pin 72" "GPIO,Input/Output" bitfld.long 0x00 1. " P71 ,Pin 71" "GPIO,Input/Output" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "GPIO,Input/Output" endif group.long 0x20++0x3 line.long 0x00 "PFR8,Port Function Setting Register 8" bitfld.long 0x00 1. " P81 ,Pin 81" "GPIO,Input/Output" bitfld.long 0x00 0. " P80 ,Pin 80" "GPIO,Input/Output" sif (!cpuis("MB9AF10?RA")&&!cpuis("MB9AF10?NA")) group.long 0x38++0x3 line.long 0x00 "PFRE,Port Function Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "GPIO,Input/Output" bitfld.long 0x00 2. " PE2 ,Pin E2" "GPIO,Input/Output" bitfld.long 0x00 0. " PE0 ,Pin E0" "GPIO,Input/Output" endif tree.end tree "Pull-up Setting Registers" group.long 0x100++0x3 line.long 0x0 "PCR0,Pull-up Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Disconnected,Connected" bitfld.long 0x0 14. " P0E ,Pin 0E" "Disconnected,Connected" bitfld.long 0x0 13. " P0D ,Pin 0D" "Disconnected,Connected" bitfld.long 0x0 12. " P0C ,Pin 0C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Disconnected,Connected" bitfld.long 0x0 10. " P0A ,Pin 0A" "Disconnected,Connected" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 9. " P09 ,Pin 09" "Disconnected,Connected" bitfld.long 0x0 8. " P08 ,Pin 08" "Disconnected,Connected" textline " " endif bitfld.long 0x0 7. " P07 ,Pin 07" "Disconnected,Connected" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 6. " P06 ,Pin 06" "Disconnected,Connected" bitfld.long 0x0 5. " P05 ,Pin 05" "Disconnected,Connected" textline " " endif bitfld.long 0x0 4. " P04 ,Pin 04" "Disconnected,Connected" bitfld.long 0x0 3. " P03 ,Pin 03" "Disconnected,Connected" bitfld.long 0x0 2. " P02 ,Pin 02" "Disconnected,Connected" bitfld.long 0x0 1. " P01 ,Pin 01" "Disconnected,Connected" textline " " bitfld.long 0x0 0. " P00 ,Pin 00" "Disconnected,Connected" group.long 0x104++0x3 line.long 0x0 "PCR1,Pull-up Setting Register 1" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 15. " P1F ,Pin 1F" "Disconnected,Connected" bitfld.long 0x0 14. " P1E ,Pin 1E" "Disconnected,Connected" bitfld.long 0x0 13. " P1D ,Pin 1D" "Disconnected,Connected" bitfld.long 0x0 12. " P1C ,Pin 1C" "Disconnected,Connected" textline " " endif bitfld.long 0x0 11. " P1B ,Pin 1B" "Disconnected,Connected" bitfld.long 0x0 10. " P1A ,Pin 1A" "Disconnected,Connected" bitfld.long 0x0 9. " P19 ,Pin 19" "Disconnected,Connected" bitfld.long 0x0 8. " P18 ,Pin 18" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Disconnected,Connected" bitfld.long 0x0 6. " P16 ,Pin 16" "Disconnected,Connected" bitfld.long 0x0 5. " P15 ,Pin 15" "Disconnected,Connected" bitfld.long 0x0 4. " P14 ,Pin 14" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Disconnected,Connected" bitfld.long 0x0 2. " P12 ,Pin 12" "Disconnected,Connected" bitfld.long 0x0 1. " P11 ,Pin 11" "Disconnected,Connected" bitfld.long 0x0 0. " P10 ,Pin 10" "Disconnected,Connected" group.long 0x108++0x3 line.long 0x0 "PCR2,Pull-up Setting Register 2" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P28 ,Pin 28" "Disconnected,Connected" bitfld.long 0x0 7. " P27 ,Pin 27" "Disconnected,Connected" bitfld.long 0x0 6. " P26 ,Pin 26" "Disconnected,Connected" bitfld.long 0x0 5. " P25 ,Pin 25" "Disconnected,Connected" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Disconnected,Connected" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Disconnected,Connected" bitfld.long 0x0 2. " P22 ,Pin 22" "Disconnected,Connected" bitfld.long 0x0 1. " P21 ,Pin 21" "Disconnected,Connected" bitfld.long 0x0 0. " P20 ,Pin 20" "Disconnected,Connected" group.long 0x10C++0x3 line.long 0x0 "PCR3,Pull-up Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Disconnected,Connected" bitfld.long 0x0 14. " P3E ,Pin 3E" "Disconnected,Connected" bitfld.long 0x0 13. " P3D ,Pin 3D" "Disconnected,Connected" bitfld.long 0x0 12. " P3C ,Pin 3C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Disconnected,Connected" bitfld.long 0x0 10. " P3A ,Pin 3A" "Disconnected,Connected" bitfld.long 0x0 9. " P39 ,Pin 39" "Disconnected,Connected" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P38 ,Pin 38" "Disconnected,Connected" bitfld.long 0x0 7. " P37 ,Pin 37" "Disconnected,Connected" bitfld.long 0x0 6. " P36 ,Pin 36" "Disconnected,Connected" bitfld.long 0x0 5. " P35 ,Pin 35" "Disconnected,Connected" textline " " bitfld.long 0x0 4. " P34 ,Pin 34" "Disconnected,Connected" textline " " endif bitfld.long 0x0 3. " P33 ,Pin 33" "Disconnected,Connected" bitfld.long 0x0 2. " P32 ,Pin 32" "Disconnected,Connected" bitfld.long 0x0 1. " P31 ,Pin 31" "Disconnected,Connected" bitfld.long 0x0 0. " P30 ,Pin 30" "Disconnected,Connected" group.long 0x110++0x3 line.long 0x0 "PCR4,Pull-up Setting Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Disconnected,Connected" bitfld.long 0x0 13. " P4D ,Pin 4D" "Disconnected,Connected" bitfld.long 0x0 12. " P4C ,Pin 4C" "Disconnected,Connected" bitfld.long 0x0 11. " P4B ,Pin 4B" "Disconnected,Connected" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Disconnected,Connected" bitfld.long 0x0 9. " P49 ,Pin 49" "Disconnected,Connected" bitfld.long 0x0 8. " P48 ,Pin 48" "Disconnected,Connected" bitfld.long 0x0 7. " P47 ,Pin 47" "Disconnected,Connected" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Disconnected,Connected" bitfld.long 0x0 5. " P45 ,Pin 45" "Disconnected,Connected" bitfld.long 0x0 4. " P44 ,Pin 44" "Disconnected,Connected" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) textline " " bitfld.long 0x0 3. " P43 ,Pin 43" "Disconnected,Connected" bitfld.long 0x0 2. " P42 ,Pin 42" "Disconnected,Connected" bitfld.long 0x0 1. " P41 ,Pin 41" "Disconnected,Connected" bitfld.long 0x0 0. " P40 ,Pin 40" "Disconnected,Connected" endif group.long 0x114++0x3 line.long 0x0 "PCR5,Pull-up Setting Register 5" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Disconnected,Connected" bitfld.long 0x0 10. " P5A ,Pin 5A" "Disconnected,Connected" bitfld.long 0x0 9. " P59 ,Pin 59" "Disconnected,Connected" bitfld.long 0x0 8. " P58 ,Pin 58" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Disconnected,Connected" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Disconnected,Connected" bitfld.long 0x0 5. " P55 ,Pin 55" "Disconnected,Connected" bitfld.long 0x0 4. " P54 ,Pin 54" "Disconnected,Connected" bitfld.long 0x0 3. " P53 ,Pin 53" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Disconnected,Connected" bitfld.long 0x0 1. " P51 ,Pin 51" "Disconnected,Connected" bitfld.long 0x0 0. " P50 ,Pin 50" "Disconnected,Connected" group.long 0x118++0x3 line.long 0x0 "PCR6,Pull-up Setting Register 6" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P68 ,Pin 68" "Disconnected,Connected" bitfld.long 0x0 7. " P67 ,Pin 67" "Disconnected,Connected" bitfld.long 0x0 6. " P66 ,Pin 66" "Disconnected,Connected" bitfld.long 0x0 5. " P65 ,Pin 65" "Disconnected,Connected" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Disconnected,Connected" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Disconnected,Connected" bitfld.long 0x0 2. " P62 ,Pin 62" "Disconnected,Connected" bitfld.long 0x0 1. " P61 ,Pin 61" "Disconnected,Connected" bitfld.long 0x0 0. " P60 ,Pin 60" "Disconnected,Connected" sif (cpuis("MB9AF10?RA")) group.long 0x11C++0x3 line.long 0x0 "PCR7,Pull-up Setting Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Disconnected,Connected" bitfld.long 0x0 3. " P73 ,Pin 73" "Disconnected,Connected" bitfld.long 0x0 2. " P72 ,Pin 72" "Disconnected,Connected" bitfld.long 0x0 1. " P71 ,Pin 71" "Disconnected,Connected" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Disconnected,Connected" endif sif (!cpuis("MB9AF10?RA")&&!cpuis("MB9AF10?NA")) group.long 0x138++0x3 line.long 0x0 "PCRE,Pull-up Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Disconnected,Connected" bitfld.long 0x0 2. " PE2 ,Pin E2" "Disconnected,Connected" bitfld.long 0x0 0. " PE0 ,Pin E0" "Disconnected,Connected" endif tree.end tree "Port Input/output Direction Setting Registers" group.long 0x200++0x3 line.long 0x0 "DDR0,Port input/output Direction Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Input,Output" bitfld.long 0x0 14. " P0E ,Pin 0E" "Input,Output" bitfld.long 0x0 13. " P0D ,Pin 0D" "Input,Output" bitfld.long 0x0 12. " P0C ,Pin 0C" "Input,Output" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Input,Output" bitfld.long 0x0 10. " P0A ,Pin 0A" "Input,Output" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 9. " P09 ,Pin 09" "Input,Output" bitfld.long 0x0 8. " P08 ,Pin 08" "Input,Output" textline " " endif bitfld.long 0x0 7. " P07 ,Pin 07" "Input,Output" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 6. " P06 ,Pin 06" "Input,Output" bitfld.long 0x0 5. " P05 ,Pin 05" "Input,Output" textline " " endif bitfld.long 0x0 4. " P04 ,Pin 04" "Input,Output" bitfld.long 0x0 3. " P03 ,Pin 03" "Input,Output" bitfld.long 0x0 2. " P02 ,Pin 02" "Input,Output" bitfld.long 0x0 1. " P01 ,Pin 01" "Input,Output" textline " " bitfld.long 0x0 0. " P00 ,Pin 00" "Input,Output" group.long 0x204++0x3 line.long 0x0 "DDR1,Port input/output Direction Setting Register 1" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 15. " P1F ,Pin 1F" "Input,Output" bitfld.long 0x0 14. " P1E ,Pin 1E" "Input,Output" bitfld.long 0x0 13. " P1D ,Pin 1D" "Input,Output" bitfld.long 0x0 12. " P1C ,Pin 1C" "Input,Output" textline " " endif bitfld.long 0x0 11. " P1B ,Pin 1B" "Input,Output" bitfld.long 0x0 10. " P1A ,Pin 1A" "Input,Output" bitfld.long 0x0 9. " P19 ,Pin 19" "Input,Output" bitfld.long 0x0 8. " P18 ,Pin 18" "Input,Output" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Input,Output" bitfld.long 0x0 6. " P16 ,Pin 16" "Input,Output" bitfld.long 0x0 5. " P15 ,Pin 15" "Input,Output" bitfld.long 0x0 4. " P14 ,Pin 14" "Input,Output" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Input,Output" bitfld.long 0x0 2. " P12 ,Pin 12" "Input,Output" bitfld.long 0x0 1. " P11 ,Pin 11" "Input,Output" bitfld.long 0x0 0. " P10 ,Pin 10" "Input,Output" group.long 0x208++0x3 line.long 0x0 "DDR2,Port input/output Direction Setting Register 2" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P28 ,Pin 28" "Input,Output" bitfld.long 0x0 7. " P27 ,Pin 27" "Input,Output" bitfld.long 0x0 6. " P26 ,Pin 26" "Input,Output" bitfld.long 0x0 5. " P25 ,Pin 25" "Input,Output" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Input,Output" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Input,Output" bitfld.long 0x0 2. " P22 ,Pin 22" "Input,Output" bitfld.long 0x0 1. " P21 ,Pin 21" "Input,Output" bitfld.long 0x0 0. " P20 ,Pin 20" "Input,Output" group.long 0x20C++0x3 line.long 0x0 "DDR3,Port input/output Direction Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Input,Output" bitfld.long 0x0 14. " P3E ,Pin 3E" "Input,Output" bitfld.long 0x0 13. " P3D ,Pin 3D" "Input,Output" bitfld.long 0x0 12. " P3C ,Pin 3C" "Input,Output" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Input,Output" bitfld.long 0x0 10. " P3A ,Pin 3A" "Input,Output" bitfld.long 0x0 9. " P39 ,Pin 39" "Input,Output" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P38 ,Pin 38" "Input,Output" bitfld.long 0x0 7. " P37 ,Pin 37" "Input,Output" bitfld.long 0x0 6. " P36 ,Pin 36" "Input,Output" bitfld.long 0x0 5. " P35 ,Pin 35" "Input,Output" textline " " bitfld.long 0x0 4. " P34 ,Pin 34" "Input,Output" textline " " endif bitfld.long 0x0 3. " P33 ,Pin 33" "Input,Output" bitfld.long 0x0 2. " P32 ,Pin 32" "Input,Output" bitfld.long 0x0 1. " P31 ,Pin 31" "Input,Output" bitfld.long 0x0 0. " P30 ,Pin 30" "Input,Output" group.long 0x210++0x3 line.long 0x0 "DDR4,Port input/output Direction Setting Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Input,Output" bitfld.long 0x0 13. " P4D ,Pin 4D" "Input,Output" bitfld.long 0x0 12. " P4C ,Pin 4C" "Input,Output" bitfld.long 0x0 11. " P4B ,Pin 4B" "Input,Output" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Input,Output" bitfld.long 0x0 9. " P49 ,Pin 49" "Input,Output" bitfld.long 0x0 8. " P48 ,Pin 48" "Input,Output" bitfld.long 0x0 7. " P47 ,Pin 47" "Input,Output" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Input,Output" bitfld.long 0x0 5. " P45 ,Pin 45" "Input,Output" bitfld.long 0x0 4. " P44 ,Pin 44" "Input,Output" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) textline " " bitfld.long 0x0 3. " P43 ,Pin 43" "Input,Output" bitfld.long 0x0 2. " P42 ,Pin 42" "Input,Output" bitfld.long 0x0 1. " P41 ,Pin 41" "Input,Output" bitfld.long 0x0 0. " P40 ,Pin 40" "Input,Output" endif group.long 0x214++0x3 line.long 0x0 "DDR5,Port input/output Direction Setting Register 5" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Input,Output" bitfld.long 0x0 10. " P5A ,Pin 5A" "Input,Output" bitfld.long 0x0 9. " P59 ,Pin 59" "Input,Output" bitfld.long 0x0 8. " P58 ,Pin 58" "Input,Output" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Input,Output" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Input,Output" bitfld.long 0x0 5. " P55 ,Pin 55" "Input,Output" bitfld.long 0x0 4. " P54 ,Pin 54" "Input,Output" textline " " bitfld.long 0x0 3. " P53 ,Pin 53" "Input,Output" bitfld.long 0x0 2. " P52 ,Pin 52" "Input,Output" bitfld.long 0x0 1. " P51 ,Pin 51" "Input,Output" bitfld.long 0x0 0. " P50 ,Pin 50" "Input,Output" group.long 0x218++0x3 line.long 0x0 "DDR6,Port input/output Direction Setting Register 6" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P68 ,Pin 68" "Input,Output" bitfld.long 0x0 7. " P67 ,Pin 67" "Input,Output" bitfld.long 0x0 6. " P66 ,Pin 66" "Input,Output" bitfld.long 0x0 5. " P65 ,Pin 65" "Input,Output" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Input,Output" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Input,Output" bitfld.long 0x0 2. " P62 ,Pin 62" "Input,Output" bitfld.long 0x0 1. " P61 ,Pin 61" "Input,Output" bitfld.long 0x0 0. " P60 ,Pin 60" "Input,Output" sif (cpuis("MB9AF10?RA")) group.long 0x21C++0x3 line.long 0x0 "DDR7,Port input/output Direction Setting Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Input,Output" bitfld.long 0x0 3. " P73 ,Pin 73" "Input,Output" bitfld.long 0x0 2. " P72 ,Pin 72" "Input,Output" bitfld.long 0x0 1. " P71 ,Pin 71" "Input,Output" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Input,Output" endif group.long 0x220++0x3 line.long 0x0 "DDR8,Port input/output Direction Setting Register 8" bitfld.long 0x0 1. " P81 ,Pin 81" "Input,Output" bitfld.long 0x0 0. " P80 ,Pin 80" "Input,Output" sif (!cpuis("MB9AF10?RA")&&!cpuis("MB9AF10?NA")) group.long 0x238++0x3 line.long 0x0 "DDRE,Port input/output Direction Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Input,Output" bitfld.long 0x0 2. " PE2 ,Pin E2" "Input,Output" bitfld.long 0x0 0. " PE0 ,Pin E0" "Input,Output" endif tree.end tree "Port Input Data Registers" rgroup.long 0x300++0x3 line.long 0x0 "PDIR0,Port Input Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" bitfld.long 0x0 14. " P0E ,Pin 0E" "Low,High" bitfld.long 0x0 13. " P0D ,Pin 0D" "Low,High" bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" textline " " endif bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" textline " " endif bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" textline " " bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" rgroup.long 0x304++0x3 line.long 0x0 "PDIR1,Port Input Data Register 1" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x0 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x0 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x0 12. " P1C ,Pin 1C" "Low,High" textline " " endif bitfld.long 0x0 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x0 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x0 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" rgroup.long 0x308++0x3 line.long 0x0 "PDIR2,Port Input Data Register 2" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x0 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x0 6. " P26 ,Pin 26" "Low,High" bitfld.long 0x0 5. " P25 ,Pin 25" "Low,High" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Low,High" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x0 0. " P20 ,Pin 20" "Low,High" rgroup.long 0x30C++0x3 line.long 0x0 "PDIR3,Port Input Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P38 ,Pin 38" "Low,High" bitfld.long 0x0 7. " P37 ,Pin 37" "Low,High" bitfld.long 0x0 6. " P36 ,Pin 36" "Low,High" bitfld.long 0x0 5. " P35 ,Pin 35" "Low,High" textline " " bitfld.long 0x0 4. " P34 ,Pin 34" "Low,High" textline " " endif bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" rgroup.long 0x310++0x3 line.long 0x0 "PDIR4,Port Input Data Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x0 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x0 4. " P44 ,Pin 44" "Low,High" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) textline " " bitfld.long 0x0 3. " P43 ,Pin 43" "Low,High" bitfld.long 0x0 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x0 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x0 0. " P40 ,Pin 40" "Low,High" endif rgroup.long 0x314++0x3 line.long 0x0 "PDIR5,Port Input Data Register 5" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x0 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x0 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x0 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Low,High" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x0 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x0 4. " P54 ,Pin 54" "Low,High" bitfld.long 0x0 3. " P53 ,Pin 53" "Low,High" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" rgroup.long 0x318++0x3 line.long 0x0 "PDIR6,Port Input Data Register 6" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P68 ,Pin 68" "Low,High" bitfld.long 0x0 7. " P67 ,Pin 67" "Low,High" bitfld.long 0x0 6. " P66 ,Pin 66" "Low,High" bitfld.long 0x0 5. " P65 ,Pin 65" "Low,High" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Low,High" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Low,High" bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" sif (cpuis("MB9AF10?RA")) rgroup.long 0x31C++0x3 line.long 0x0 "PDIR7,Port Input Data Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x0 3. " P73 ,Pin 73" "Low,High" bitfld.long 0x0 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x0 1. " P71 ,Pin 71" "Low,High" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Low,High" endif rgroup.long 0x320++0x3 line.long 0x0 "PDIR8,Port Input Data Register 8" bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" sif (!cpuis("MB9AF10?RA")&&!cpuis("MB9AF10?NA")) rgroup.long 0x338++0x3 line.long 0x0 "PDIRE,Port Input Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" endif tree.end tree "Port Output Data Registers" group.long 0x400++0x3 line.long 0x0 "PDOR0,Port Output Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" bitfld.long 0x0 14. " P0E ,Pin 0E" "Low,High" bitfld.long 0x0 13. " P0D ,Pin 0D" "Low,High" bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" textline " " endif bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" textline " " endif bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" textline " " bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" group.long 0x404++0x3 line.long 0x0 "PDOR1,Port Output Data Register 1" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x0 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x0 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x0 12. " P1C ,Pin 1C" "Low,High" textline " " endif bitfld.long 0x0 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x0 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x0 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" group.long 0x408++0x3 line.long 0x0 "PDOR2,Port Output Data Register 2" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x0 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x0 6. " P26 ,Pin 26" "Low,High" bitfld.long 0x0 5. " P25 ,Pin 25" "Low,High" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Low,High" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x0 0. " P20 ,Pin 20" "Low,High" group.long 0x40C++0x3 line.long 0x0 "PDOR3,Port Output Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P38 ,Pin 38" "Low,High" bitfld.long 0x0 7. " P37 ,Pin 37" "Low,High" bitfld.long 0x0 6. " P36 ,Pin 36" "Low,High" bitfld.long 0x0 5. " P35 ,Pin 35" "Low,High" textline " " bitfld.long 0x0 4. " P34 ,Pin 34" "Low,High" textline " " endif bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" group.long 0x410++0x3 line.long 0x0 "PDOR4,Port Output Data Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x0 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x0 4. " P44 ,Pin 44" "Low,High" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) textline " " bitfld.long 0x0 3. " P43 ,Pin 43" "Low,High" bitfld.long 0x0 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x0 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x0 0. " P40 ,Pin 40" "Low,High" endif group.long 0x414++0x3 line.long 0x0 "PDOR5,Port Output Data Register 5" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x0 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x0 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x0 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Low,High" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x0 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x0 4. " P54 ,Pin 54" "Low,High" bitfld.long 0x0 3. " P53 ,Pin 53" "Low,High" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" group.long 0x418++0x3 line.long 0x0 "PDOR6,Port Output Data Register 6" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0 8. " P68 ,Pin 68" "Low,High" bitfld.long 0x0 7. " P67 ,Pin 67" "Low,High" bitfld.long 0x0 6. " P66 ,Pin 66" "Low,High" bitfld.long 0x0 5. " P65 ,Pin 65" "Low,High" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Low,High" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Low,High" bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" sif (cpuis("MB9AF10?RA")) group.long 0x41C++0x3 line.long 0x0 "PDOR7,Port Output Data Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x0 3. " P73 ,Pin 73" "Low,High" bitfld.long 0x0 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x0 1. " P71 ,Pin 71" "Low,High" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Low,High" endif group.long 0x420++0x3 line.long 0x0 "PDOR8,Port Output Data Register 8" bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" group.long 0x424++0x3 line.long 0x0 "PDOR9,Port Output Data Register 9" bitfld.long 0x0 15. " P9F ,Pin 9F" "Low,High" bitfld.long 0x0 14. " P9E ,Pin 9E" "Low,High" bitfld.long 0x0 13. " P9D ,Pin 9D" "Low,High" bitfld.long 0x0 12. " P9C ,Pin 9C" "Low,High" textline " " bitfld.long 0x0 11. " P9B ,Pin 9B" "Low,High" bitfld.long 0x0 10. " P9A ,Pin 9A" "Low,High" bitfld.long 0x0 9. " P99 ,Pin 99" "Low,High" bitfld.long 0x0 8. " P98 ,Pin 98" "Low,High" textline " " bitfld.long 0x0 7. " P97 ,Pin 97" "Low,High" bitfld.long 0x0 6. " P96 ,Pin 96" "Low,High" bitfld.long 0x0 5. " P95 ,Pin 95" "Low,High" bitfld.long 0x0 4. " P94 ,Pin 94" "Low,High" textline " " bitfld.long 0x0 3. " P93 ,Pin 93" "Low,High" bitfld.long 0x0 2. " P92 ,Pin 92" "Low,High" bitfld.long 0x0 1. " P91 ,Pin 91" "Low,High" bitfld.long 0x0 0. " P90 ,Pin 90" "Low,High" sif (!cpuis("MB9AF10?RA")&&!cpuis("MB9AF10?NA")) group.long 0x438++0x3 line.long 0x0 "PDORE,Port Output Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" endif tree.end tree "Analog Input Setting Register" group.long 0x500++0x3 line.long 0x0 "ADE,Analog Input Setting Register" sif (cpuis("MB9AF?4??")) sif (cpuis("MB9AF?4?N")) bitfld.long 0x0 22. " ADE22 ,Analog signal input pin 22 enable" "Digital I/O,Analog IN" else bitfld.long 0x0 23. " ADE23 ,Analog signal input pin 23 enable" "Digital I/O,Analog IN" bitfld.long 0x0 22. " ADE22 ,Analog signal input pin 22 enable" "Digital I/O,Analog IN" bitfld.long 0x0 21. " ADE21 ,Analog signal input pin 21 enable" "Digital I/O,Analog IN" bitfld.long 0x0 20. " ADE20 ,Analog signal input pin 20 enable" "Digital I/O,Analog IN" endif textline " " bitfld.long 0x0 19. " ADE19 ,Analog signal input pin 19 enable" "Digital I/O,Analog IN" bitfld.long 0x0 18. " ADE18 ,Analog signal input pin 18 enable" "Digital I/O,Analog IN" bitfld.long 0x0 17. " ADE17 ,Analog signal input pin 17 enable" "Digital I/O,Analog IN" bitfld.long 0x0 16. " ADE16 ,Analog signal input pin 16 enable" "Digital I/O,Analog IN" textline " " endif sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x0 15. " ADE15 ,Analog signal input pin 15 enable" "Digital I/O,Analog IN" bitfld.long 0x0 14. " ADE14 ,Analog signal input pin 14 enable" "Digital I/O,Analog IN" bitfld.long 0x0 13. " ADE13 ,Analog signal input pin 13 enable" "Digital I/O,Analog IN" bitfld.long 0x0 12. " ADE12 ,Analog signal input pin 12 enable" "Digital I/O,Analog IN" textline " " endif bitfld.long 0x0 11. " ADE11 ,Analog signal input pin 11 enable" "Digital I/O,Analog IN" bitfld.long 0x0 10. " ADE10 ,Analog signal input pin 10 enable" "Digital I/O,Analog IN" bitfld.long 0x0 9. " ADE9 ,Analog signal input pin 9 enable" "Digital I/O,Analog IN" bitfld.long 0x0 8. " ADE8 ,Analog signal input pin 8 enable" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 7. " ADE7 ,Analog signal input pin 7 enable" "Digital I/O,Analog IN" bitfld.long 0x0 6. " ADE6 ,Analog signal input pin 6 enable" "Digital I/O,Analog IN" bitfld.long 0x0 5. " ADE5 ,Analog signal input pin 5 enable" "Digital I/O,Analog IN" bitfld.long 0x0 4. " ADE4 ,Analog signal input pin 4 enable" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 3. " ADE3 ,Analog signal input pin 3 enable" "Digital I/O,Analog IN" bitfld.long 0x0 2. " ADE2 ,Analog signal input pin 2 enable" "Digital I/O,Analog IN" bitfld.long 0x0 1. " ADE1 ,Analog signal input pin 1 enable" "Digital I/O,Analog IN" bitfld.long 0x0 0. " ADE0 ,Analog signal input pin 0 enable" "Digital I/O,Analog IN" tree.end tree "Extended Pin Function Setting Register" group.long 0x600++0x3 line.long 0x0 "EPFR00,Extended Pin Function Setting Register 00" sif (cpuis("MB9AF???N")&&!cpuis("MB9AF?3?N")) bitfld.long 0x00 25. " TRC1E ,Select whether to use two pins of TRACED2 and TRACED3" "Not used,Used" bitfld.long 0x00 24. " TRC0E ,Select whether to use three pins of TRACECLK, TRACED0, and TRACED1" "Not used,Used" textline " " endif bitfld.long 0x00 17. " JTAGEN1S ,Select whether to use two pins of TRSTX and TDI" "Not used,Used" bitfld.long 0x00 16. " JTAGEN0S ,Select whether to use three pins of TCK, TMS, and TDO" "Not used,Used" textline " " sif (cpuis("MB9AF31??")||cpuis("MB9AF34??")||cpuis("MB9AFB4??")) bitfld.long 0x00 9. " USBP0E ,Selects whether to produce output D+ resistor control signal (HCONTX) for USBch.0" "Not produced,Produced" textline " " endif sif (cpuis("MB9AF34??")||cpuis("MB9AFA3??")||cpuis("MB9AF13??")||cpuis("MB9AF14??")||cpuis("MB9AFA4??")||cpuis("MB9AFB4??")) bitfld.long 0x00 6.--7. " SUBOUTE ,Selects sub clock divide output" "Not executed,SUBOUT_0,SUBOUT_1,SUBOUT_2" bitfld.long 0x00 4.--5. " RTCCOE ,Selects a RTC clock output" "Not executed,RTCCOE_0,RTCCOE_1,RTCCOE_2" textline " " endif sif (cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 1.--2. " CROUTE ,Selects internal high-speed CR oscillation output" "Not produced,CROUT_0,?..." else bitfld.long 0x00 1.--2. " CROUTE ,Selects internal high-speed CR oscillation output" "Not produced,CROUT_0,CROUT_1,?..." endif textline " " bitfld.long 0x00 0. " NMIS ,Select whether to use the NMIX pin" "Not used,Used" sif (cpuis("MB9AF31??")||cpuis("MB9AFA3??")||cpuis("MB9AF11??")||cpuis("MB9AF13??")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) group.long 0x604++0x3 line.long 0x00 "EPFR01,Extended Pin Function Setting Register 01" sif (cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9AF11?N")||cpuis("MB9AF13?N")) bitfld.long 0x00 29.--31. " IC03S ,IC03 Input Select Bit" "IC03_0,IC03_0,IC03_1,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x00 26.--28. " IS02S ,IC02 Input Select Bit" "IC02_0,IC02_0,IC02_1,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." textline " " bitfld.long 0x00 23.--25. " IC01S ,IC01 Input Select Bit" "IC01_0,IC01_0,IC01_1,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x00 20.--22. " IC00S ,IC00 Input Select Bit" "IC00_0,IC00_0,IC00_1,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " elif (cpuis("MB9AF31?M")||cpuis("MB9AFA3?M")||cpuis("MB9AF11?M")||cpuis("MB9AF13?M")) bitfld.long 0x00 29.--31. " IC03S ,IC03 Input Select Bit" ",,,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x00 26.--28. " IS02S ,IC02 Input Select Bit" ",,,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." textline " " bitfld.long 0x00 23.--25. " IC01S ,IC01 Input Select Bit" ",,IC01_1,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x00 20.--22. " IC00S ,IC00 Input Select Bit" ",,IC00_1,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " elif (cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 29.--31. " IC03S ,IC03 Input Select Bit" "IC03_0,IC03_0,IC03_1,,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x00 26.--28. " IS02S ,IC02 Input Select Bit" "IC02_0,IC02_0,IC02_1,,MFSch.2LSYN,MFSch.6LSYN,?..." textline " " bitfld.long 0x00 23.--25. " IC01S ,IC01 Input Select Bit" "IC01_0,IC01_0,IC01_1,,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x00 20.--22. " IC00S ,IC00 Input Select Bit" "IC00_0,IC00_0,IC00_1,,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " endif sif (cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "FRCK0_0,FRCK0_0,FRCK0_1,?..." bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,DTTIX0_1,?..." elif (cpuis("MB9AFA3?N")||cpuis("MB9AF13?N")) bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "FRCK0_0,FRCK0_0,FRCK0_1,FRCK0_2" bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,DTTIX0_1,DTTIX0_2" elif (cpuis("MB9AFA3?M")||cpuis("MB9AF13?M")) bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" ",,,FRCK0_2" bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,,DTTIX0_2" elif (cpuis("MB9AF31?N")||cpuis("MB9AF11?N")) bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "FRCK0_0,FRCK0_0,FRCK0_1,FRCK0_2" bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,DTTIX0_1,?..." else bitfld.long 0x00 18.--19. " FRCK0S ,FRCK0 Input Select Bit" ",,,FRCK0_2" bitfld.long 0x00 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,?..." endif textline " " sif (cpuis("MB9AF???RA")) bitfld.long 0x00 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" bitfld.long 0x00 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,RTO05_1,?..." textline " " bitfld.long 0x00 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,RTO04_1,?..." bitfld.long 0x00 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,RTO03_1,?..." textline " " bitfld.long 0x00 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,RTO02_1,?..." bitfld.long 0x00 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,RTO01_1,?..." bitfld.long 0x00 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,RTO00_1,?..." else bitfld.long 0x00 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" bitfld.long 0x00 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,?..." textline " " bitfld.long 0x00 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,?..." bitfld.long 0x00 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,?..." textline " " bitfld.long 0x00 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,?..." bitfld.long 0x00 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,?..." textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")) bitfld.long 0x00 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,RTO00_1,?..." else bitfld.long 0x00 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,?..." endif endif endif sif (cpuis("MB9AF31??")||cpuis("MB9AF11??")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) group.long 0x608++0x3 line.long 0x0 "EPFR02,Extended Pin Function Setting Register 02" bitfld.long 0x00 29.--31. " IC13S ,IC13 Input Select Bit" "IC13_0,IC13_0,IC13_1,,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x00 26.--28. " IS12S ,IC12 Input Select Bit" "IC12_0,IC12_0,IC12_1,,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x00 23.--25. " IC11S ,IC11 Input Select Bit" "IC11_0,IC11_0,IC11_1,,MFSch.1LSYN,MFSch.5LSYN,?..." textline " " bitfld.long 0x00 20.--22. " IC10S ,IC10 Input Select Bit" "IC10_0,IC10_0,IC10_1,,MFSch.0LSYN,MFSch.4LSYN,?..." bitfld.long 0x00 18.--19. " FRCK1S ,FRCK1 Input Select Bit" "FRCK1_0,FRCK1_0,FRCK1_1,?..." bitfld.long 0x00 16.--17. " DTTI1S ,DTTIX1 Input Select Bit" "DTTIX1_0,DTTIX1_0,DTTIX1_1,?..." textline " " bitfld.long 0x00 12. " DTTI1C ,DTTIX1 Function Select Bit" "Not switched,Switched" textline " " sif (cpuis("MB9AF?1?M")) bitfld.long 0x00 10.--11. " RTO15E ,RTO15E Output Select Bit" "Not produced,RTO15_0,RTO15_1,?..." bitfld.long 0x00 8.--9. " RTO14E ,RTO14E Output Select Bit" "Not produced,RTO14_0,RTO14_1,?..." bitfld.long 0x00 6.--7. " RTO13E ,RTO13E Output Select Bit" "Not produced,RTO13_0,?..." textline " " bitfld.long 0x00 4.--5. " RTO012E ,RTO12E Output Select Bit" "Not produced,RTO12_0,?..." bitfld.long 0x00 2.--3. " RTO11E ,RTO11E Output Select Bit" "Not produced,RTO11_0,?..." bitfld.long 0x00 0.--1. " RTO10E ,RTO10E Output Select Bit" "Not produced,RTO10_0,?..." else bitfld.long 0x00 10.--11. " RTO15E ,RTO15E Output Select Bit" "Not produced,RTO15_0,RTO15_1,?..." bitfld.long 0x00 8.--9. " RTO14E ,RTO14E Output Select Bit" "Not produced,RTO14_0,RTO14_1,?..." bitfld.long 0x00 6.--7. " RTO13E ,RTO13E Output Select Bit" "Not produced,RTO13_0,RTO13_1,?..." textline " " bitfld.long 0x00 4.--5. " RTO012E ,RTO12E Output Select Bit" "Not produced,RTO12_0,RTO12_1,?..." bitfld.long 0x00 2.--3. " RTO11E ,RTO11E Output Select Bit" "Not produced,RTO11_0,RTO11_1,?..." bitfld.long 0x00 0.--1. " RTO10E ,RTO10E Output Select Bit" "Not produced,RTO10_0,RTO10_1,?..." endif endif group.long 0x610++0x17 line.long 0x0 "EPFR04,Extended Pin Function Setting Register 04" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,TIOB3_1,TIOB3_2" bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,TIOA3_0,TIOA3_1,TIOA3_2" bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" "TIOA3_0,TIOA3_0,TIOA3_1,TIOA3_2" textline " " bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2" bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,TIOA2_0,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" "TIOA2_0,TIOA2_0,TIOA2_1,TIOA2_2" textline " " bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,TIOB1_1,TIOB1_2" bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,TIOA1_0,TIOA1_1,TIOA1_2" bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" "TIOA1_0,TIOA1_0,TIOA1_1,TIOA1_2" textline " " sif (cpuis("MB9AFA4??")||cpuis("MB9AFB4??")||cpuis("MB9AF14??")||cpuis("MB9AF34??")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2,,,,Measuring pin" elif (cpuis("MB9AFA3??")||cpuis("MB9AF13??")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2,,,SUBOUT,?..." else bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2,?..." endif textline " " bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,TIOA0_0,TIOA0_1,TIOA0_2" else bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,TIOB3_1,TIOB3_2" bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,,TIOA3_1,TIOA3_2" bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" ",,TIOA3_1,TIOA3_2" textline " " bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2" bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" ",,TIOA2_1,TIOA2_2" textline " " bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,TIOB1_1,TIOB1_2" bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,,TIOA1_1,TIOA1_2" bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" ",,TIOA1_1,TIOA1_2" textline " " sif (cpuis("MB9AFA3??")||cpuis("MB9AF13??")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,,,,SUBOUT,?..." elif (cpuis("MB9AFA4??")||cpuis("MB9AFB4??")||cpuis("MB9AF14??")||cpuis("MB9AF34??")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,,,,,Measuring pin" else bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,?..." endif textline " " bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,,TIOA0_1,?..." endif line.long 0x4 "EPFR05,Extended Pin Function Setting Register 05" sif (cpuis("MB9AF10?RA")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" "TIOB7_0,TIOB7_0,TIOB7_1,TIOB7_2" bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,TIOA7_0,TIOA7_1,TIOA7_2" bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" "TIOA7_0,TIOA7_0,TIOA7_1,TIOA7_2" textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" ",,TIOB6_1,?..." bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,,TIOA6_1,?..." textline " " bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,TIOB5_1,TIOB5_2" bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,TIOA5_0,TIOA5_1,TIOA5_2" bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" "TIOA5_0,TIOA5_0,TIOA5_1,TIOA5_2" textline " " bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,TIOB4_2" bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,TIOA4_2" elif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,?..." bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,?..." bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,?..." textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" ",,TIOB6_1,?..." bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,,TIOA6_1,?..." textline " " bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,TIOB5_1,TIOB5_2" bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,TIOA5_0,TIOA5_1,TIOA5_2" bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" "TIOA5_0,TIOA5_0,TIOA5_1,TIOA5_2" textline " " bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,?..." bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,?..." else bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,?..." bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,?..." bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,?..." textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" ",,TIOB6_1,?..." bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,,TIOA6_1,?..." textline " " bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,?..." bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,TIOA5_0,TIOA5_1,?..." bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" "TIOA5_0,TIOA5_0,TIOA5_1,?..." textline " " bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,?..." bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,?..." endif line.long 0x8 "EPFR06,Extended Pin Function Setting Register 06" sif (cpuis("MB9AF10?RA")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,INT15_2" bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" ",,INT14_1,INT14_2" bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" ",,INT13_1,INT13_2" textline " " bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" ",,INT12_1,INT12_2" bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" ",,INT11_1,INT11_2" bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" ",,INT10_1,INT10_2" textline " " bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" ",,INT09_1,INT09_2" bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" ",,INT08_1,INT08_2" textline " " elif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,?..." bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" ",,INT14_1,?..." bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" ",,INT13_1,?..." textline " " bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" ",,INT12_1,?..." bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" ",,INT11_1,?..." bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" ",,INT10_1,?..." textline " " bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" ",,INT09_1,?..." bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" ",,INT08_1,INT08_2" textline " " else bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,?..." bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" ",,INT14_1,?..." bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" ",,INT08_1,?..." textline " " endif bitfld.long 0x08 14.--15. " EINT07S ,External Interrupt Input 7 Select Bit" ",,,INT07_2" bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" ",,INT06_1,INT06_2" bitfld.long 0x08 10.--11. " EINT05S ,External Interrupt Input 5 Select Bit" "INT05_0,INT05_0,INT05_1,INT05_2" textline " " bitfld.long 0x08 8.--9. " EINT04S ,External Interrupt Input 4 Select Bit" "INT04_0,INT04_0,INT04_1,INT04_2" bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" "INT03_0,INT03_0,INT03_1,INT03_2" textline " " sif (cpuis("MB9AF10?RA")) bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,INT02_2" bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,INT01_2" bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,INT00_1,INT00_2" elif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")) bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,?..." bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,?..." bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,INT00_1,INT00_2" else bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,?..." bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,?..." bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,,INT00_2" endif line.long 0xC "EPFR07,Extended Pin Function Setting Register 07" sif (cpuis("MB9AF10?RA")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "SCK3_0/Not produced,SCK3_0/SCK3_0,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "SOT3_0/Not produced,SOT3_0/SOT3_0,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" "SIN3_0,SIN3_0,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "SCK2_0/Not produced,SCK2_0/SCK2_0,SCK2_1/SCK2_1,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "SOT2_0/Not produced,SOT2_0/SOT2_0,SOT2_1/SOT2_1,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" "SIN2_0,SIN2_0,SIN2_1,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "SCK1_0/Not produced,SCK1_0/SCK1_0,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "SOT1_0/Not produced,SOT1_0/SOT1_0,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" "SIN1_0,SIN1_0,SIN1_1,?..." else bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "/Not produced,,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "/Not produced,,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" ",,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "/Not produced,,,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "/Not produced,,,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" ",,,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "/Not produced,,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "/Not produced,,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" ",,SIN1_1,?..." endif textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,SCK0_1/SCK0_1,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,SOT0_1/SOT0_1,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,SIN0_1,?..." line.long 0x10 "EPFR08,Extended Pin Function Setting Register 08" sif (cpuis("MB9AF10?RA")) bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "SCK7_0/Not produced,SCK7_0/SCK7_0,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "SOT7_0/Not produced,SOT7_0/SOT7_0,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" "SIN7_0,SIN7_0,SIN7_1,?..." textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,SIN6_1,?..." textline " " else bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "/Not produced,,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "/Not produced,,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" ",,SIN7_1,?..." textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,SIN6_1,?..." textline " " endif sif (cpuis("MB9AF10?RA")) bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,SCK5_1/SCK5_1,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,SOT5_1/SOT5_1,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,,SIN5_2" textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,SCK4_1/SCK4_1,SCK4_2/SCK4_2" bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,SOT4_1/SOT4_1,SOT4_2/SOT4_2" bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,SIN4_1,SIN4_2" textline " " elif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")) bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,,SIN5_2" textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,SCK4_1/SCK4_1,SCK4_2/SCK4_2" bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,SOT4_1/SOT4_1,SOT4_2/SOT4_2" bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,SIN4_1,SIN4_2" textline " " else bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,?..." bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,?..." bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,?..." textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,?..." bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,SOT4_1/SOT4_1,?..." bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,SIN4_1,?..." textline " " endif sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x10 2.--3. " CTS4S ,CTS4S Input Select Bit" "CTS4_0,CTS4_0,CTS4_1,CTS4_2" bitfld.long 0x10 0.--1. " RTS4E ,RTS4E Output Select Bit" "Not produced,RTS4_0,RTS4_1,RTS4_2" else bitfld.long 0x10 2.--3. " CTS4S ,CTS4S Input Select Bit" "CTS4_0,CTS4_0,?..." bitfld.long 0x10 0.--1. " RTS4E ,RTS4E Output Select Bit" "Not produced,RTS4_0,?..." endif line.long 0x14 "EPFR09,Extended Pin Function Setting Register 09" sif (cpuis("MB9AF10?RA")) bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." elif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")) bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." else bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,,ADTG_6,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,,ADTG_6,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,,ADTG_6,?..." endif sif (cpuis("MB9AF31??")||cpuis("MB9AF11??")) textline " " bitfld.long 0x14 10.--11. " QZIN1S ,Select input for QPRC ZIN1" ",,ZIN1_1,ZIN1_2" bitfld.long 0x14 8.--9. " QBIN1S ,Select input for QPRC BIN1" ",,BIN1_1,BIN1_2" bitfld.long 0x14 6.--7. " QAIN1S ,Select input for QPRC AIN1" ",,AIN1_1,AIN1_2" textline " " bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" "BIN0_0,BIN0_0,BIN0_1,BIN0_2" bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" "AIN0_0,AIN0_0,AIN0_1,AIN0_2" endif sif (!cpuis("MB9AF?3??")) group.long 0x628++0x7 line.long 0x00 "EPFR10,Extended Pin Function Setting Register 10" bitfld.long 0x00 31. " UEA24E ,Selects output for external bus Adress24" "Not produced,Produced" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 30. " UEA23E ,Selects output for external bus Adress23" "Not produced,Produced" bitfld.long 0x00 29. " UEA22E ,Selects output for external bus Adress22" "Not produced,Produced" bitfld.long 0x00 28. " UEA21E ,Selects output for external bus Adress21" "Not produced,Produced" textline " " bitfld.long 0x00 27. " UEA20E ,Selects output for external bus Adress20" "Not produced,Produced" textline " " endif bitfld.long 0x00 26. " UEA19E ,Selects output for external bus Adress19" "Not produced,Produced" bitfld.long 0x00 25. " UEA18E ,Selects output for external bus Adress18" "Not produced,Produced" bitfld.long 0x00 24. " UEA17E ,Selects output for external bus Adress17" "Not produced,Produced" textline " " bitfld.long 0x00 23. " UEA16E ,Selects output for external bus Adress16" "Not produced,Produced" bitfld.long 0x00 22. " UEA15E ,Selects output for external bus Adress15" "Not produced,Produced" bitfld.long 0x00 21. " UEA14E ,Selects output for external bus Adress14" "Not produced,Produced" textline " " bitfld.long 0x00 20. " UEA13E ,Selects output for external bus Adress13" "Not produced,Produced" bitfld.long 0x00 19. " UEA12E ,Selects output for external bus Adress12" "Not produced,Produced" bitfld.long 0x00 18. " UEA11E ,Selects output for external bus Adress11" "Not produced,Produced" textline " " bitfld.long 0x00 17. " UEA10E ,Selects output for external bus Adress10" "Not produced,Produced" bitfld.long 0x00 16. " UEA09E ,Selects output for external bus Adress09" "Not produced,Produced" bitfld.long 0x00 15. " UEA08E ,Selects output for external bus Adress08" "Not produced,Produced" textline " " bitfld.long 0x00 14. " UEA00E ,Selects output for external bus Adress00" "Not produced,Produced" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?RA")) bitfld.long 0x00 13. " UECS7E ,Selects output for external bus CS7" "Not produced,Produced" bitfld.long 0x00 12. " UECS6E ,Selects output for external bus CS6" "Not produced,Produced" bitfld.long 0x00 11. " UECS5E ,Selects output for external bus CS5" "Not produced,Produced" textline " " bitfld.long 0x00 10. " UECS4E ,Selects output for external bus CS4" "Not produced,Produced" bitfld.long 0x00 9. " UECS3E ,Selects output for external bus CS3" "Not produced,Produced" bitfld.long 0x00 8. " UECS2E ,Selects output for external bus CS2" "Not produced,Produced" textline " " bitfld.long 0x00 7. " UECS1E ,Selects output for external bus CS1" "Not produced,Produced" elif (cpuis("MB9AF10?NA")) bitfld.long 0x00 13. " UECS7E ,Selects output for external bus CS7" "Not produced,Produced" bitfld.long 0x00 9. " UECS3E ,Selects output for external bus CS3" "Not produced,Produced" bitfld.long 0x00 8. " UECS2E ,Selects output for external bus CS2" "Not produced,Produced" textline " " bitfld.long 0x00 7. " UECS1E ,Selects output for external bus CS1" "Not produced,Produced" else bitfld.long 0x00 13. " UECS7E ,Selects output for external bus CS7" "Not produced,Produced" bitfld.long 0x00 12. " UECS6E ,Selects output for external bus CS6" "Not produced,Produced" bitfld.long 0x00 7. " UECS1E ,Selects output for external bus CS1" "Not produced,Produced" endif textline " " sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 6. " UEFLSE ,Selects output for external bus NAND-Flash control signal" "Not produced,Produced" textline " " endif bitfld.long 0x00 5. " UEOEXE ,Selects output for external bus OEX" "Not produced,Produced" bitfld.long 0x00 4. " UEDQME ,Selects output for external bus DQM" "Not produced,Produced" bitfld.long 0x00 3. " UEWEXE ,Selects output for external bus WEX" "Not produced,Produced" textline " " sif (!cpuis("MB9AF10?NA")||!cpuis("MB9AF10?RA")) bitfld.long 0x00 2. " UECLKE ,Selects output for external bus clock" "Not produced,Produced" endif textline " " bitfld.long 0x00 1. " UEDTHB ,Selects input/output for external bus data" "Not produced,Produced" bitfld.long 0x00 0. " UEDEFB ,Selects input/output for external bus signal" "Not produced,Produced" line.long 0x04 "EPFR11,Extended Pin Function Setting Register 11" bitfld.long 0x04 25. " UERLC ,Selects relocation of the external bus pin" "0,1" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x04 24. " UED15B ,Selects input/output for external bus data 15" "Not produced,Produced" bitfld.long 0x04 23. " UED14B ,Selects output for external bus data 14" "Not produced,Produced" bitfld.long 0x04 22. " UED13B ,Selects output for external bus data 13" "Not produced,Produced" textline " " bitfld.long 0x04 21. " UED12B ,Selects output for external bus data 12" "Not produced,Produced" bitfld.long 0x04 20. " UED11B ,Selects output for external bus data 11" "Not produced,Produced" textline " " endif bitfld.long 0x04 19. " UED10B ,Selects output for external bus data 10" "Not produced,Produced" bitfld.long 0x04 18. " UED09B ,Selects output for external bus data 09" "Not produced,Produced" bitfld.long 0x04 17. " UED08B ,Selects output for external bus data 08" "Not produced,Produced" textline " " bitfld.long 0x04 16. " UED07B ,Selects output for external bus data 07" "Not produced,Produced" bitfld.long 0x04 15. " UED06B ,Selects output for external bus data 06" "Not produced,Produced" bitfld.long 0x04 14. " UED05B ,Selects output for external bus data 05" "Not produced,Produced" textline " " bitfld.long 0x04 13. " UED04B ,Selects output for external bus data 04" "Not produced,Produced" bitfld.long 0x04 12. " UED03B ,Selects output for external bus data 03" "Not produced,Produced" bitfld.long 0x04 11. " UED02B ,Selects output for external bus data 02" "Not produced,Produced" textline " " bitfld.long 0x04 10. " UED01B ,Selects output for external bus data 01" "Not produced,Produced" bitfld.long 0x04 9. " UED00B ,Selects output for external bus data 00" "Not produced,Produced" bitfld.long 0x04 8. " UEA07E ,Selects output for external bus address07" "Not produced,Produced" textline " " bitfld.long 0x04 7. " UEA06E ,Selects output for external bus address06" "Not produced,Produced" bitfld.long 0x04 6. " UEA05E ,Selects output for external bus address05" "Not produced,Produced" bitfld.long 0x04 5. " UEA04E ,Selects output for external bus address04" "Not produced,Produced" textline " " bitfld.long 0x04 4. " UEA03E ,Selects output for external bus address03" "Not produced,Produced" bitfld.long 0x04 3. " UEA02E ,Selects output for external bus address02" "Not produced,Produced" bitfld.long 0x04 2. " UEA01E ,Selects output for external bus address01" "Not produced,Produced" textline " " bitfld.long 0x04 1. " UECS0E ,Selects output for external bus address00" "Not produced,Produced" bitfld.long 0x04 0. " UEALEE ,Selects output for external bus ALE signal" "Not produced,Produced" endif sif (cpuis("MB9AF34??")||cpuis("MB9AF14??")||cpuis("MB9AF13??")||cpuis("MB9AFA3??")||cpuis("MB9AFA4??")||cpuis("MB9AFB4??")) group.long 0x638++0x3 line.long 0x00 "EPFR14,Extended Pin Function Setting Register 14" bitfld.long 0x00 31. " CEC1B ,Selects I/O for CEC1" "Not input/output,Input/output" bitfld.long 0x00 30. " CEC0B ,Selects I/O for CEC0" "Not input/output,Input/output" endif tree.end tree "Special Port Setting Register" group.long 0x580++0x3 line.long 0x0 "SPSR,Special Port Setting Register" sif (cpuis("MB9AF31??")||cpuis("MB9AFB4??")||cpuis("MB9AF34??")) bitfld.long 0x00 4. " USB0C ,USB (ch.0) Pin Setting Register" "Not used,Used" textline " " endif bitfld.long 0x00 2. " MAINXC ,Main Clock (Oscillation) Pin Setting Register" "Not used,Used" bitfld.long 0x00 0. " SUBXC ,Sub Clock (Oscillation) Pin Setting Register" "Not used,Used" tree.end tree "Port Pseudo Open Drain Setting Registers" group.long 0x700++0x3 line.long 0x00 "PZR0,Port Pseudo Open Drain Setting Register 0" bitfld.long 0x00 15. " P0F ,Pin 0F" "High,Hi-Z" bitfld.long 0x00 14. " P0E ,Pin 0E" "High,Hi-Z" bitfld.long 0x00 13. " P0D ,Pin 0D" "High,Hi-Z" textline " " bitfld.long 0x00 12. " P0C ,Pin 0C" "High,Hi-Z" bitfld.long 0x00 11. " P0B ,Pin 0B" "High,Hi-Z" bitfld.long 0x00 10. " P0A ,Pin 0A" "High,Hi-Z" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 9. " P09 ,Pin 09" "High,Hi-Z" bitfld.long 0x00 8. " P08 ,Pin 08" "High,Hi-Z" textline " " endif bitfld.long 0x00 7. " P07 ,Pin 07" "High,Hi-Z" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 6. " P06 ,Pin 06" "High,Hi-Z" bitfld.long 0x00 5. " P05 ,Pin 05" "High,Hi-Z" textline " " endif bitfld.long 0x00 4. " P04 ,Pin 04" "High,Hi-Z" bitfld.long 0x00 3. " P03 ,Pin 03" "High,Hi-Z" bitfld.long 0x00 2. " P02 ,Pin 02" "High,Hi-Z" textline " " bitfld.long 0x00 1. " P01 ,Pin 01" "High,Hi-Z" bitfld.long 0x00 0. " P00 ,Pin 00" "High,Hi-Z" group.long 0x704++0x3 line.long 0x00 "PZR1,Port Pseudo Open Drain Setting Register 1" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 15. " P1F ,Pin 1F" "High,Hi-Z" bitfld.long 0x00 14. " P1E ,Pin 1E" "High,Hi-Z" bitfld.long 0x00 13. " P1D ,Pin 1D" "High,Hi-Z" textline " " bitfld.long 0x00 12. " P1C ,Pin 1C" "High,Hi-Z" textline " " endif bitfld.long 0x00 11. " P1B ,Pin 1B" "High,Hi-Z" bitfld.long 0x00 10. " P1A ,Pin 1A" "High,Hi-Z" bitfld.long 0x00 9. " P19 ,Pin 19" "High,Hi-Z" textline " " bitfld.long 0x00 8. " P18 ,Pin 18" "High,Hi-Z" bitfld.long 0x00 7. " P17 ,Pin 17" "High,Hi-Z" bitfld.long 0x00 6. " P16 ,Pin 16" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P15 ,Pin 15" "High,Hi-Z" bitfld.long 0x00 4. " P14 ,Pin 14" "High,Hi-Z" bitfld.long 0x00 3. " P13 ,Pin 13" "High,Hi-Z" textline " " bitfld.long 0x00 2. " P12 ,Pin 12" "High,Hi-Z" bitfld.long 0x00 1. " P11 ,Pin 11" "High,Hi-Z" bitfld.long 0x00 0. " P10 ,Pin 10" "High,Hi-Z" group.long 0x708++0x3 line.long 0x00 "PZR2,Port Pseudo Open Drain Setting Register 2" sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 8. " P28 ,Pin 28" "High,Hi-Z" bitfld.long 0x00 7. " P27 ,Pin 27" "High,Hi-Z" bitfld.long 0x00 6. " P26 ,Pin 26" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P25 ,Pin 25" "High,Hi-Z" bitfld.long 0x00 4. " P24 ,Pin 24" "High,Hi-Z" textline " " endif bitfld.long 0x00 3. " P23 ,Pin 23" "High,Hi-Z" bitfld.long 0x00 2. " P22 ,Pin 22" "High,Hi-Z" bitfld.long 0x00 1. " P21 ,Pin 21" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P20 ,Pin 20" "High,Hi-Z" group.long 0x70C++0x3 line.long 0x00 "PZR3,Port Pseudo Open Drain Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "High,Hi-Z" bitfld.long 0x00 14. " P3E ,Pin 3E" "High,Hi-Z" bitfld.long 0x00 13. " P3D ,Pin 3D" "High,Hi-Z" textline " " bitfld.long 0x00 12. " P3C ,Pin 3C" "High,Hi-Z" bitfld.long 0x00 11. " P3B ,Pin 3B" "High,Hi-Z" bitfld.long 0x00 10. " P3A ,Pin 3A" "High,Hi-Z" textline " " bitfld.long 0x00 9. " P39 ,Pin 39" "High,Hi-Z" textline " " sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) bitfld.long 0x00 8. " P38 ,Pin 38" "High,Hi-Z" bitfld.long 0x00 7. " P37 ,Pin 37" "High,Hi-Z" bitfld.long 0x00 6. " P36 ,Pin 36" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P35 ,Pin 35" "High,Hi-Z" bitfld.long 0x00 4. " P34 ,Pin 34" "High,Hi-Z" textline " " endif bitfld.long 0x00 3. " P33 ,Pin 33" "High,Hi-Z" bitfld.long 0x00 2. " P32 ,Pin 32" "High,Hi-Z" bitfld.long 0x00 1. " P31 ,Pin 31" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P30 ,Pin 30" "High,Hi-Z" group.long 0x710++0x3 line.long 0x00 "PZR4,Port Pseudo Open Drain Setting Register 4" bitfld.long 0x00 14. " P4E ,Pin 4E" "High,Hi-Z" bitfld.long 0x00 13. " P4D ,Pin 4D" "High,Hi-Z" bitfld.long 0x00 12. " P4C ,Pin 4C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P4B ,Pin 4B" "High,Hi-Z" bitfld.long 0x00 10. " P4A ,Pin 4A" "High,Hi-Z" bitfld.long 0x00 9. " P49 ,Pin 49" "High,Hi-Z" textline " " bitfld.long 0x00 8. " P48 ,Pin 48" "High,Hi-Z" bitfld.long 0x00 7. " P47 ,Pin 47" "High,Hi-Z" bitfld.long 0x00 6. " P46 ,Pin 46" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P45 ,Pin 45" "High,Hi-Z" bitfld.long 0x00 4. " P44 ,Pin 44" "High,Hi-Z" sif (cpuis("MB9AF???N")||cpuis("MB9AF10?NA")||cpuis("MB9AF10?RA")) textline " " bitfld.long 0x00 3. " P43 ,Pin 43" "High,Hi-Z" bitfld.long 0x00 2. " P42 ,Pin 42" "High,Hi-Z" bitfld.long 0x00 1. " P41 ,Pin 41" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P40 ,Pin 40" "High,Hi-Z" endif group.long 0x714++0x3 line.long 0x00 "PZR5,Port Pseudo Open Drain Setting Register 5" sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 11. " P5B ,Pin 5B" "High,Hi-Z" bitfld.long 0x00 10. " P5A ,Pin 5A" "High,Hi-Z" bitfld.long 0x00 9. " P59 ,Pin 59" "High,Hi-Z" textline " " bitfld.long 0x00 8. " P58 ,Pin 58" "High,Hi-Z" bitfld.long 0x00 7. " P57 ,Pin 57" "High,Hi-Z" textline " " endif bitfld.long 0x00 6. " P56 ,Pin 56" "High,Hi-Z" bitfld.long 0x00 5. " P55 ,Pin 55" "High,Hi-Z" bitfld.long 0x00 4. " P54 ,Pin 54" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P53 ,Pin 53" "High,Hi-Z" bitfld.long 0x00 2. " P52 ,Pin 52" "High,Hi-Z" bitfld.long 0x00 1. " P51 ,Pin 51" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P50 ,Pin 50" "High,Hi-Z" group.long 0x718++0x3 line.long 0x00 "PZR6,Port Pseudo Open Drain Setting Register 6" sif (cpuis("MB9AF10?RA")) bitfld.long 0x00 8. " P68 ,Pin 68" "High,Hi-Z" bitfld.long 0x00 7. " P67 ,Pin 67" "High,Hi-Z" bitfld.long 0x00 6. " P66 ,Pin 66" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P65 ,Pin 65" "High,Hi-Z" bitfld.long 0x00 4. " P64 ,Pin 64" "High,Hi-Z" textline " " endif bitfld.long 0x00 3. " P63 ,Pin 63" "High,Hi-Z" bitfld.long 0x00 2. " P62 ,Pin 62" "High,Hi-Z" bitfld.long 0x00 1. " P61 ,Pin 61" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P60 ,Pin 60" "High,Hi-Z" sif (cpuis("MB9AF10?RA")) group.long 0x71C++0x3 line.long 0x00 "PZR7,Port Pseudo Open Drain Setting Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "High,Hi-Z" bitfld.long 0x00 3. " P73 ,Pin 73" "High,Hi-Z" bitfld.long 0x00 2. " P72 ,Pin 72" "High,Hi-Z" textline " " bitfld.long 0x00 1. " P71 ,Pin 71" "High,Hi-Z" bitfld.long 0x00 0. " P70 ,Pin 70" "High,Hi-Z" endif group.long 0x720++0x3 line.long 0x00 "PZR8,Port Pseudo Open Drain Setting Register 8" sif (cpuis("MB9AF13?N")||cpuis("MB9AF13?M")||cpuis("MB9AFA3?N")||cpuis("MB9AFA3?M")) bitfld.long 0x00 2. " P82 ,Pin 82" "High,Hi-Z" textline " " endif bitfld.long 0x00 1. " P81 ,Pin 81" "High,Hi-Z" bitfld.long 0x00 0. " P80 ,Pin 80" "High,Hi-Z" sif (!cpuis("MB9AF10?RA")&&!cpuis("MB9AF10?NA")) group.long 0x738++0x3 line.long 0x00 "PZRE,Port Pseudo Open Drain Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "High,Hi-Z" bitfld.long 0x00 2. " PE2 ,Pin E2" "High,Hi-Z" bitfld.long 0x00 0. " PE0 ,Pin E0" "High,Hi-Z" endif tree.end width 12. elif (cpuis("MB9BF???S")||cpuis("MB9BF???T")) width 8. tree "Port Function Setting Registers" group.long 0x0++0x3 line.long 0x00 "PFR0,Port Function Setting Register 0" bitfld.long 0x00 9. " P09 ,Pin 09" "GPIO,Input/Output" bitfld.long 0x00 8. " P08 ,Pin 08" "GPIO,Input/Output" bitfld.long 0x00 7. " P07 ,Pin 07" "GPIO,Input/Output" bitfld.long 0x00 6. " P06 ,Pin 06" "GPIO,Input/Output" textline " " bitfld.long 0x00 5. " P05 ,Pin 05" "GPIO,Input/Output" bitfld.long 0x00 4. " P04 ,Pin 04" "GPIO,Input/Output" bitfld.long 0x00 3. " P03 ,Pin 03" "GPIO,Input/Output" bitfld.long 0x00 2. " P02 ,Pin 02" "GPIO,Input/Output" textline " " bitfld.long 0x00 1. " P01 ,Pin 01" "GPIO,Input/Output" bitfld.long 0x00 0. " P00 ,Pin 00" "GPIO,Input/Output" group.long 0x4++0x3 line.long 0x00 "PFR1,Port Function Setting Register 1" bitfld.long 0x00 15. " P1F ,Pin 1F" "GPIO,Input/Output" bitfld.long 0x00 14. " P1E ,Pin 1E" "GPIO,Input/Output" bitfld.long 0x00 13. " P1D ,Pin 1D" "GPIO,Input/Output" bitfld.long 0x00 12. " P1C ,Pin 1C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P1B ,Pin 1B" "GPIO,Input/Output" bitfld.long 0x00 10. " P1A ,Pin 1A" "GPIO,Input/Output" bitfld.long 0x00 9. " P19 ,Pin 19" "GPIO,Input/Output" bitfld.long 0x00 8. " P18 ,Pin 18" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P17 ,Pin 17" "GPIO,Input/Output" bitfld.long 0x00 6. " P16 ,Pin 16" "GPIO,Input/Output" bitfld.long 0x00 5. " P15 ,Pin 15" "GPIO,Input/Output" bitfld.long 0x00 4. " P14 ,Pin 14" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P13 ,Pin 13" "GPIO,Input/Output" bitfld.long 0x00 2. " P12 ,Pin 12" "GPIO,Input/Output" bitfld.long 0x00 1. " P11 ,Pin 11" "GPIO,Input/Output" bitfld.long 0x00 0. " P10 ,Pin 10" "GPIO,Input/Output" group.long 0x8++0x3 line.long 0x00 "PFR2,Port Function Setting Register 2" bitfld.long 0x00 9. " P29 ,Pin 29" "GPIO,Input/Output" bitfld.long 0x00 8. " P28 ,Pin 28" "GPIO,Input/Output" bitfld.long 0x00 7. " P27 ,Pin 27" "GPIO,Input/Output" bitfld.long 0x00 6. " P26 ,Pin 26" "GPIO,Input/Output" textline " " bitfld.long 0x00 5. " P25 ,Pin 25" "GPIO,Input/Output" bitfld.long 0x00 4. " P24 ,Pin 24" "GPIO,Input/Output" bitfld.long 0x00 3. " P23 ,Pin 23" "GPIO,Input/Output" bitfld.long 0x00 2. " P22 ,Pin 22" "GPIO,Input/Output" textline " " bitfld.long 0x00 1. " P21 ,Pin 21" "GPIO,Input/Output" bitfld.long 0x00 0. " P20 ,Pin 20" "GPIO,Input/Output" group.long 0xC++0x3 line.long 0x00 "PFR3,Port Function Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "GPIO,Input/Output" bitfld.long 0x00 14. " P3E ,Pin 3E" "GPIO,Input/Output" bitfld.long 0x00 13. " P3D ,Pin 3D" "GPIO,Input/Output" bitfld.long 0x00 12. " P3C ,Pin 3C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P3B ,Pin 3B" "GPIO,Input/Output" bitfld.long 0x00 10. " P3A ,Pin 3A" "GPIO,Input/Output" bitfld.long 0x00 9. " P39 ,Pin 39" "GPIO,Input/Output" bitfld.long 0x00 8. " P38 ,Pin 38" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P37 ,Pin 37" "GPIO,Input/Output" bitfld.long 0x00 6. " P36 ,Pin 36" "GPIO,Input/Output" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x00 5. " P35 ,Pin 35" "GPIO,Input/Output" bitfld.long 0x00 4. " P34 ,Pin 34" "GPIO,Input/Output" bitfld.long 0x00 3. " P33 ,Pin 33" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P32 ,Pin 32" "GPIO,Input/Output" bitfld.long 0x00 1. " P31 ,Pin 31" "GPIO,Input/Output" bitfld.long 0x00 0. " P30 ,Pin 30" "GPIO,Input/Output" endif group.long 0x10++0x3 line.long 0x00 "PFR4,Port Function Setting Register 4" bitfld.long 0x00 14. " P4E ,Pin 4E" "GPIO,Input/Output" bitfld.long 0x00 13. " P4D ,Pin 4D" "GPIO,Input/Output" bitfld.long 0x00 12. " P4C ,Pin 4C" "GPIO,Input/Output" bitfld.long 0x00 11. " P4B ,Pin 4B" "GPIO,Input/Output" textline " " bitfld.long 0x00 10. " P4A ,Pin 4A" "GPIO,Input/Output" bitfld.long 0x00 9. " P49 ,Pin 49" "GPIO,Input/Output" bitfld.long 0x00 8. " P48 ,Pin 48" "GPIO,Input/Output" bitfld.long 0x00 7. " P47 ,Pin 47" "GPIO,Input/Output" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "GPIO,Input/Output" bitfld.long 0x00 5. " P45 ,Pin 45" "GPIO,Input/Output" bitfld.long 0x00 4. " P44 ,Pin 44" "GPIO,Input/Output" bitfld.long 0x00 3. " P43 ,Pin 43" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P42 ,Pin 42" "GPIO,Input/Output" bitfld.long 0x00 1. " P41 ,Pin 41" "GPIO,Input/Output" bitfld.long 0x00 0. " P40 ,Pin 40" "GPIO,Input/Output" group.long 0x14++0x3 line.long 0x00 "PFR5,Port Function Setting Register 5" sif (cpuis("MB9BF???T")) bitfld.long 0x00 13. " P5D ,Pin 5D" "GPIO,Input/Output" bitfld.long 0x00 12. " P5C ,Pin 5C" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 11. " P5B ,Pin 5B" "GPIO,Input/Output" bitfld.long 0x00 10. " P5A ,Pin 5A" "GPIO,Input/Output" bitfld.long 0x00 9. " P59 ,Pin 59" "GPIO,Input/Output" bitfld.long 0x00 8. " P58 ,Pin 58" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P57 ,Pin 57" "GPIO,Input/Output" bitfld.long 0x00 6. " P56 ,Pin 56" "GPIO,Input/Output" bitfld.long 0x00 5. " P55 ,Pin 55" "GPIO,Input/Output" bitfld.long 0x00 4. " P54 ,Pin 54" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P53 ,Pin 53" "GPIO,Input/Output" bitfld.long 0x00 2. " P52 ,Pin 52" "GPIO,Input/Output" bitfld.long 0x00 1. " P51 ,Pin 51" "GPIO,Input/Output" bitfld.long 0x00 0. " P50 ,Pin 50" "GPIO,Input/Output" group.long 0x18++0x3 line.long 0x00 "PFR6,Port Function Setting Register 6" bitfld.long 0x00 2. " P62 ,Pin 62" "GPIO,Input/Output" bitfld.long 0x00 1. " P61 ,Pin 61" "GPIO,Input/Output" bitfld.long 0x00 0. " P60 ,Pin 60" "GPIO,Input/Output" group.long 0x1C++0x3 line.long 0x00 "PFR7,Port Function Setting Register 7" sif (cpuis("MB9BF???T")) bitfld.long 0x00 15. " P7F ,Pin 7F" "GPIO,Input/Output" bitfld.long 0x00 14. " P7E ,Pin 7E" "GPIO,Input/Output" bitfld.long 0x00 13. " P7D ,Pin 7D" "GPIO,Input/Output" bitfld.long 0x00 12. " P7C ,Pin 7C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P7B ,Pin 7B" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 10. " P7A ,Pin 7A" "GPIO,Input/Output" bitfld.long 0x00 9. " P79 ,Pin 79" "GPIO,Input/Output" bitfld.long 0x00 8. " P78 ,Pin 78" "GPIO,Input/Output" bitfld.long 0x00 7. " P77 ,Pin 77" "GPIO,Input/Output" textline " " bitfld.long 0x00 6. " P76 ,Pin 76" "GPIO,Input/Output" bitfld.long 0x00 5. " P75 ,Pin 75" "GPIO,Input/Output" bitfld.long 0x00 4. " P74 ,Pin 74" "GPIO,Input/Output" bitfld.long 0x00 3. " P73 ,Pin 73" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P72 ,Pin 72" "GPIO,Input/Output" bitfld.long 0x00 1. " P71 ,Pin 71" "GPIO,Input/Output" bitfld.long 0x00 0. " P70 ,Pin 70" "GPIO,Input/Output" group.long 0x20++0x3 line.long 0x00 "PFR8,Port Function Setting Register 8" bitfld.long 0x00 3. " P83 ,Pin 83" "GPIO,Input/Output" bitfld.long 0x00 2. " P82 ,Pin 82" "GPIO,Input/Output" bitfld.long 0x00 1. " P81 ,Pin 81" "GPIO,Input/Output" bitfld.long 0x00 0. " P80 ,Pin 80" "GPIO,Input/Output" sif (cpuis("MB9BF???T")) group.long 0x24++0x3 line.long 0x00 "PFR9,Port Function Setting Register 9" bitfld.long 0x00 5. " P95 ,Pin 95" "GPIO,Input/Output" bitfld.long 0x00 4. " P94 ,Pin 94" "GPIO,Input/Output" bitfld.long 0x00 3. " P93 ,Pin 93" "GPIO,Input/Output" bitfld.long 0x00 2. " P92 ,Pin 92" "GPIO,Input/Output" textline " " bitfld.long 0x00 1. " P91 ,Pin 91" "GPIO,Input/Output" bitfld.long 0x00 0. " P90 ,Pin 90" "GPIO,Input/Output" endif group.long 0x28++0x3 line.long 0x00 "PFRA,Port Function Setting Register A" bitfld.long 0x00 5. " PA5 ,Pin A5" "GPIO,Input/Output" bitfld.long 0x00 4. " PA4 ,Pin A4" "GPIO,Input/Output" bitfld.long 0x00 3. " PA3 ,Pin A3" "GPIO,Input/Output" bitfld.long 0x00 2. " PA2 ,Pin A2" "GPIO,Input/Output" textline " " bitfld.long 0x00 1. " PA1 ,Pin A1" "GPIO,Input/Output" bitfld.long 0x00 0. " PA0 ,Pin A0" "GPIO,Input/Output" sif (cpuis("MB9BF???T")) group.long 0x2C++0x3 line.long 0x00 "PFRB,Port Function Setting Register B" bitfld.long 0x00 7. " PB7 ,Pin B7" "GPIO,Input/Output" bitfld.long 0x00 6. " PB6 ,Pin B6" "GPIO,Input/Output" bitfld.long 0x00 5. " PB5 ,Pin B5" "GPIO,Input/Output" bitfld.long 0x00 4. " PB4 ,Pin B4" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " PB3 ,Pin B3" "GPIO,Input/Output" bitfld.long 0x00 2. " PB2 ,Pin B2" "GPIO,Input/Output" bitfld.long 0x00 1. " PB1 ,Pin B1" "GPIO,Input/Output" bitfld.long 0x00 0. " PB0 ,Pin B0" "GPIO,Input/Output" endif group.long 0x30++0x3 line.long 0x00 "PFRC,Port Function Setting Register C" bitfld.long 0x00 15. " PCF ,Pin CF" "GPIO,Input/Output" bitfld.long 0x00 14. " PCE ,Pin CE" "GPIO,Input/Output" bitfld.long 0x00 13. " PCD ,Pin CD" "GPIO,Input/Output" bitfld.long 0x00 12. " PCC ,Pin CC" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " PCB ,Pin CB" "GPIO,Input/Output" bitfld.long 0x00 10. " PCA ,Pin CA" "GPIO,Input/Output" bitfld.long 0x00 9. " PC9 ,Pin C9" "GPIO,Input/Output" bitfld.long 0x00 8. " PC8 ,Pin C8" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " PC7 ,Pin C7" "GPIO,Input/Output" bitfld.long 0x00 6. " PC6 ,Pin C6" "GPIO,Input/Output" bitfld.long 0x00 5. " PC5 ,Pin C5" "GPIO,Input/Output" bitfld.long 0x00 4. " PC4 ,Pin C4" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " PC3 ,Pin C3" "GPIO,Input/Output" bitfld.long 0x00 2. " PC2 ,Pin C2" "GPIO,Input/Output" bitfld.long 0x00 1. " PC1 ,Pin C1" "GPIO,Input/Output" bitfld.long 0x00 0. " PC0 ,Pin C0" "GPIO,Input/Output" group.long 0x34++0x3 line.long 0x00 "PFRD,Port Function Setting Register D" bitfld.long 0x00 3. " PD3 ,Pin D3" "GPIO,Input/Output" bitfld.long 0x00 2. " PD2 ,Pin D2" "GPIO,Input/Output" bitfld.long 0x00 1. " PD1 ,Pin D1" "GPIO,Input/Output" bitfld.long 0x00 0. " PD0 ,Pin D0" "GPIO,Input/Output" group.long 0x38++0x3 line.long 0x00 "PFRE,Port Function Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "GPIO,Input/Output" bitfld.long 0x00 2. " PE2 ,Pin E2" "GPIO,Input/Output" bitfld.long 0x00 1. " PE1 ,Pin E1" "GPIO,Input/Output" bitfld.long 0x00 0. " PE0 ,Pin E0" "GPIO,Input/Output" group.long 0x3C++0x3 line.long 0x00 "PFRF,Port Function Setting Register F" bitfld.long 0x00 6. " PF6 ,Pin F6" "GPIO,Input/Output" bitfld.long 0x00 5. " PF5 ,Pin F5" "GPIO,Input/Output" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x00 4. " PF4 ,Pin F4" "GPIO,Input/Output" bitfld.long 0x00 3. " PF3 ,Pin F3" "GPIO,Input/Output" bitfld.long 0x00 2. " PF2 ,Pin F2" "GPIO,Input/Output" bitfld.long 0x00 1. " PF1 ,Pin F1" "GPIO,Input/Output" textline " " bitfld.long 0x00 0. " PF0 ,Pin F0" "GPIO,Input/Output" endif tree.end tree "Pull-up Setting Registers" group.long 0x100++0x3 line.long 0x0 "PCR0,Pull-up Setting Register 0" bitfld.long 0x0 9. " P09 ,Pin 09" "Disconnected,Connected" bitfld.long 0x0 8. " P08 ,Pin 08" "Disconnected,Connected" bitfld.long 0x0 7. " P07 ,Pin 07" "Disconnected,Connected" bitfld.long 0x0 6. " P06 ,Pin 06" "Disconnected,Connected" textline " " bitfld.long 0x0 5. " P05 ,Pin 05" "Disconnected,Connected" bitfld.long 0x0 4. " P04 ,Pin 04" "Disconnected,Connected" bitfld.long 0x0 3. " P03 ,Pin 03" "Disconnected,Connected" bitfld.long 0x0 2. " P02 ,Pin 02" "Disconnected,Connected" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Disconnected,Connected" bitfld.long 0x0 0. " P00 ,Pin 00" "Disconnected,Connected" group.long 0x104++0x3 line.long 0x0 "PCR1,Pull-up Setting Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Disconnected,Connected" bitfld.long 0x0 14. " P1E ,Pin 1E" "Disconnected,Connected" bitfld.long 0x0 13. " P1D ,Pin 1D" "Disconnected,Connected" bitfld.long 0x0 12. " P1C ,Pin 1C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Disconnected,Connected" bitfld.long 0x0 10. " P1A ,Pin 1A" "Disconnected,Connected" bitfld.long 0x0 9. " P19 ,Pin 19" "Disconnected,Connected" bitfld.long 0x0 8. " P18 ,Pin 18" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Disconnected,Connected" bitfld.long 0x0 6. " P16 ,Pin 16" "Disconnected,Connected" bitfld.long 0x0 5. " P15 ,Pin 15" "Disconnected,Connected" bitfld.long 0x0 4. " P14 ,Pin 14" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Disconnected,Connected" bitfld.long 0x0 2. " P12 ,Pin 12" "Disconnected,Connected" bitfld.long 0x0 1. " P11 ,Pin 11" "Disconnected,Connected" bitfld.long 0x0 0. " P10 ,Pin 10" "Disconnected,Connected" group.long 0x108++0x3 line.long 0x0 "PCR2,Pull-up Setting Register 2" bitfld.long 0x0 9. " P29 ,Pin 29" "Disconnected,Connected" bitfld.long 0x0 8. " P28 ,Pin 28" "Disconnected,Connected" bitfld.long 0x0 7. " P27 ,Pin 27" "Disconnected,Connected" bitfld.long 0x0 6. " P26 ,Pin 26" "Disconnected,Connected" textline " " bitfld.long 0x0 5. " P25 ,Pin 25" "Disconnected,Connected" bitfld.long 0x0 4. " P24 ,Pin 24" "Disconnected,Connected" bitfld.long 0x0 3. " P23 ,Pin 23" "Disconnected,Connected" bitfld.long 0x0 2. " P22 ,Pin 22" "Disconnected,Connected" textline " " bitfld.long 0x0 1. " P21 ,Pin 21" "Disconnected,Connected" bitfld.long 0x0 0. " P20 ,Pin 20" "Disconnected,Connected" group.long 0x10C++0x3 line.long 0x0 "PCR3,Pull-up Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Disconnected,Connected" bitfld.long 0x0 14. " P3E ,Pin 3E" "Disconnected,Connected" bitfld.long 0x0 13. " P3D ,Pin 3D" "Disconnected,Connected" bitfld.long 0x0 12. " P3C ,Pin 3C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Disconnected,Connected" bitfld.long 0x0 10. " P3A ,Pin 3A" "Disconnected,Connected" bitfld.long 0x0 9. " P39 ,Pin 39" "Disconnected,Connected" bitfld.long 0x0 8. " P38 ,Pin 38" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Disconnected,Connected" bitfld.long 0x0 6. " P36 ,Pin 36" "Disconnected,Connected" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 5. " P35 ,Pin 35" "Disconnected,Connected" bitfld.long 0x0 4. " P34 ,Pin 34" "Disconnected,Connected" bitfld.long 0x0 3. " P33 ,Pin 33" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P32 ,Pin 32" "Disconnected,Connected" bitfld.long 0x0 1. " P31 ,Pin 31" "Disconnected,Connected" bitfld.long 0x0 0. " P30 ,Pin 30" "Disconnected,Connected" endif group.long 0x110++0x3 line.long 0x0 "PCR4,Pull-up Setting Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Disconnected,Connected" bitfld.long 0x0 13. " P4D ,Pin 4D" "Disconnected,Connected" bitfld.long 0x0 12. " P4C ,Pin 4C" "Disconnected,Connected" bitfld.long 0x0 11. " P4B ,Pin 4B" "Disconnected,Connected" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Disconnected,Connected" bitfld.long 0x0 9. " P49 ,Pin 49" "Disconnected,Connected" bitfld.long 0x0 8. " P48 ,Pin 48" "Disconnected,Connected" bitfld.long 0x0 7. " P47 ,Pin 47" "Disconnected,Connected" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Disconnected,Connected" bitfld.long 0x0 5. " P45 ,Pin 45" "Disconnected,Connected" bitfld.long 0x0 4. " P44 ,Pin 44" "Disconnected,Connected" bitfld.long 0x0 3. " P43 ,Pin 43" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Disconnected,Connected" bitfld.long 0x0 1. " P41 ,Pin 41" "Disconnected,Connected" bitfld.long 0x0 0. " P40 ,Pin 40" "Disconnected,Connected" group.long 0x114++0x3 line.long 0x0 "PCR5,Pull-up Setting Register 5" sif (cpuis("MB9BF???T")) bitfld.long 0x0 13. " P5D ,Pin 5D" "Disconnected,Connected" bitfld.long 0x0 12. " P5C ,Pin 5C" "Disconnected,Connected" textline " " endif bitfld.long 0x0 11. " P5B ,Pin 5B" "Disconnected,Connected" bitfld.long 0x0 10. " P5A ,Pin 5A" "Disconnected,Connected" bitfld.long 0x0 9. " P59 ,Pin 59" "Disconnected,Connected" bitfld.long 0x0 8. " P58 ,Pin 58" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Disconnected,Connected" bitfld.long 0x0 6. " P56 ,Pin 56" "Disconnected,Connected" bitfld.long 0x0 5. " P55 ,Pin 55" "Disconnected,Connected" bitfld.long 0x0 4. " P54 ,Pin 54" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P53 ,Pin 53" "Disconnected,Connected" bitfld.long 0x0 2. " P52 ,Pin 52" "Disconnected,Connected" bitfld.long 0x0 1. " P51 ,Pin 51" "Disconnected,Connected" bitfld.long 0x0 0. " P50 ,Pin 50" "Disconnected,Connected" group.long 0x118++0x3 line.long 0x0 "PCR6,Pull-up Setting Register 6" bitfld.long 0x0 2. " P62 ,Pin 62" "Disconnected,Connected" bitfld.long 0x0 1. " P61 ,Pin 61" "Disconnected,Connected" bitfld.long 0x0 0. " P60 ,Pin 60" "Disconnected,Connected" group.long 0x11C++0x3 line.long 0x0 "PCR7,Pull-up Setting Register 7" sif (cpuis("MB9BF???T")) bitfld.long 0x0 15. " P7F ,Pin 7F" "Disconnected,Connected" bitfld.long 0x0 14. " P7E ,Pin 7E" "Disconnected,Connected" bitfld.long 0x0 13. " P7D ,Pin 7D" "Disconnected,Connected" bitfld.long 0x0 12. " P7C ,Pin 7C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P7B ,Pin 7B" "Disconnected,Connected" textline " " endif bitfld.long 0x0 10. " P7A ,Pin 7A" "Disconnected,Connected" bitfld.long 0x0 9. " P79 ,Pin 79" "Disconnected,Connected" bitfld.long 0x0 8. " P78 ,Pin 78" "Disconnected,Connected" bitfld.long 0x0 7. " P77 ,Pin 77" "Disconnected,Connected" textline " " bitfld.long 0x0 6. " P76 ,Pin 76" "Disconnected,Connected" bitfld.long 0x0 5. " P75 ,Pin 75" "Disconnected,Connected" bitfld.long 0x0 4. " P74 ,Pin 74" "Disconnected,Connected" bitfld.long 0x0 3. " P73 ,Pin 73" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P72 ,Pin 72" "Disconnected,Connected" bitfld.long 0x0 1. " P71 ,Pin 71" "Disconnected,Connected" bitfld.long 0x0 0. " P70 ,Pin 70" "Disconnected,Connected" sif (cpuis("MB9BF???T")) group.long 0x124++0x3 line.long 0x0 "PCR9,Pull-up Setting Register 9" bitfld.long 0x0 5. " P95 ,Pin 95" "Disconnected,Connected" bitfld.long 0x0 4. " P94 ,Pin 94" "Disconnected,Connected" bitfld.long 0x0 3. " P93 ,Pin 93" "Disconnected,Connected" bitfld.long 0x0 2. " P92 ,Pin 92" "Disconnected,Connected" textline " " bitfld.long 0x0 1. " P91 ,Pin 91" "Disconnected,Connected" bitfld.long 0x0 0. " P90 ,Pin 90" "Disconnected,Connected" endif group.long 0x128++0x3 line.long 0x0 "PCRA,Pull-up Setting Register A" bitfld.long 0x0 5. " PA5 ,Pin A5" "Disconnected,Connected" bitfld.long 0x0 4. " PA4 ,Pin A4" "Disconnected,Connected" bitfld.long 0x0 3. " PA3 ,Pin A3" "Disconnected,Connected" bitfld.long 0x0 2. " PA2 ,Pin A2" "Disconnected,Connected" textline " " bitfld.long 0x0 1. " PA1 ,Pin A1" "Disconnected,Connected" bitfld.long 0x0 0. " PA0 ,Pin A0" "Disconnected,Connected" sif (cpuis("MB9BF???T")) group.long 0x12C++0x3 line.long 0x0 "PCRB,Pull-up Setting Register B" bitfld.long 0x0 7. " PB7 ,Pin B7" "Disconnected,Connected" bitfld.long 0x0 6. " PB6 ,Pin B6" "Disconnected,Connected" bitfld.long 0x0 5. " PB5 ,Pin B5" "Disconnected,Connected" bitfld.long 0x0 4. " PB4 ,Pin B4" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " PB3 ,Pin B3" "Disconnected,Connected" bitfld.long 0x0 2. " PB2 ,Pin B2" "Disconnected,Connected" bitfld.long 0x0 1. " PB1 ,Pin B1" "Disconnected,Connected" bitfld.long 0x0 0. " PB0 ,Pin B0" "Disconnected,Connected" endif group.long 0x130++0x3 line.long 0x0 "PCRC,Pull-up Setting Register C" bitfld.long 0x0 15. " PCF ,Pin CF" "Disconnected,Connected" bitfld.long 0x0 14. " PCE ,Pin CE" "Disconnected,Connected" bitfld.long 0x0 13. " PCD ,Pin CD" "Disconnected,Connected" bitfld.long 0x0 12. " PCC ,Pin CC" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " PCB ,Pin CB" "Disconnected,Connected" bitfld.long 0x0 10. " PCA ,Pin CA" "Disconnected,Connected" bitfld.long 0x0 9. " PC9 ,Pin C9" "Disconnected,Connected" bitfld.long 0x0 8. " PC8 ,Pin C8" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " PC7 ,Pin C7" "Disconnected,Connected" bitfld.long 0x0 6. " PC6 ,Pin C6" "Disconnected,Connected" bitfld.long 0x0 5. " PC5 ,Pin C5" "Disconnected,Connected" bitfld.long 0x0 4. " PC4 ,Pin C4" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " PC3 ,Pin C3" "Disconnected,Connected" bitfld.long 0x0 2. " PC2 ,Pin C2" "Disconnected,Connected" bitfld.long 0x0 1. " PC1 ,Pin C1" "Disconnected,Connected" bitfld.long 0x0 0. " PC0 ,Pin C0" "Disconnected,Connected" group.long 0x134++0x3 line.long 0x0 "PCRD,Pull-up Setting Register D" bitfld.long 0x0 3. " PD3 ,Pin D3" "Disconnected,Connected" bitfld.long 0x0 2. " PD2 ,Pin D2" "Disconnected,Connected" bitfld.long 0x0 1. " PD1 ,Pin D1" "Disconnected,Connected" bitfld.long 0x0 0. " PD0 ,Pin D0" "Disconnected,Connected" group.long 0x138++0x3 line.long 0x0 "PCRE,Pull-up Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Disconnected,Connected" bitfld.long 0x0 2. " PE2 ,Pin E2" "Disconnected,Connected" bitfld.long 0x0 1. " PE1 ,Pin E1" "Disconnected,Connected" bitfld.long 0x0 0. " PE0 ,Pin E0" "Disconnected,Connected" group.long 0x13C++0x3 line.long 0x0 "PCRF,Pull-up Setting Register F" bitfld.long 0x0 6. " PF6 ,Pin F6" "Disconnected,Connected" bitfld.long 0x0 5. " PF5 ,Pin F5" "Disconnected,Connected" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 4. " PF4 ,Pin F4" "Disconnected,Connected" bitfld.long 0x0 3. " PF3 ,Pin F3" "Disconnected,Connected" bitfld.long 0x0 2. " PF2 ,Pin F2" "Disconnected,Connected" bitfld.long 0x0 1. " PF1 ,Pin F1" "Disconnected,Connected" textline " " bitfld.long 0x0 0. " PF0 ,Pin F0" "Disconnected,Connected" endif tree.end tree "Port Input/output Direction Setting Registers" group.long 0x200++0x3 line.long 0x0 "DDR0,Port input/output Direction Setting Register 0" bitfld.long 0x0 9. " P09 ,Pin 09" "Input,Output" bitfld.long 0x0 8. " P08 ,Pin 08" "Input,Output" bitfld.long 0x0 7. " P07 ,Pin 07" "Input,Output" bitfld.long 0x0 6. " P06 ,Pin 06" "Input,Output" textline " " bitfld.long 0x0 5. " P05 ,Pin 05" "Input,Output" bitfld.long 0x0 4. " P04 ,Pin 04" "Input,Output" bitfld.long 0x0 3. " P03 ,Pin 03" "Input,Output" bitfld.long 0x0 2. " P02 ,Pin 02" "Input,Output" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Input,Output" bitfld.long 0x0 0. " P00 ,Pin 00" "Input,Output" group.long 0x204++0x3 line.long 0x0 "DDR1,Port input/output Direction Setting Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Input,Output" bitfld.long 0x0 14. " P1E ,Pin 1E" "Input,Output" bitfld.long 0x0 13. " P1D ,Pin 1D" "Input,Output" bitfld.long 0x0 12. " P1C ,Pin 1C" "Input,Output" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Input,Output" bitfld.long 0x0 10. " P1A ,Pin 1A" "Input,Output" bitfld.long 0x0 9. " P19 ,Pin 19" "Input,Output" bitfld.long 0x0 8. " P18 ,Pin 18" "Input,Output" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Input,Output" bitfld.long 0x0 6. " P16 ,Pin 16" "Input,Output" bitfld.long 0x0 5. " P15 ,Pin 15" "Input,Output" bitfld.long 0x0 4. " P14 ,Pin 14" "Input,Output" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Input,Output" bitfld.long 0x0 2. " P12 ,Pin 12" "Input,Output" bitfld.long 0x0 1. " P11 ,Pin 11" "Input,Output" bitfld.long 0x0 0. " P10 ,Pin 10" "Input,Output" group.long 0x208++0x3 line.long 0x0 "DDR2,Port input/output Direction Setting Register 2" bitfld.long 0x0 9. " P29 ,Pin 29" "Input,Output" bitfld.long 0x0 8. " P28 ,Pin 28" "Input,Output" bitfld.long 0x0 7. " P27 ,Pin 27" "Input,Output" bitfld.long 0x0 6. " P26 ,Pin 26" "Input,Output" textline " " bitfld.long 0x0 5. " P25 ,Pin 25" "Input,Output" bitfld.long 0x0 4. " P24 ,Pin 24" "Input,Output" bitfld.long 0x0 3. " P23 ,Pin 23" "Input,Output" bitfld.long 0x0 2. " P22 ,Pin 22" "Input,Output" textline " " bitfld.long 0x0 1. " P21 ,Pin 21" "Input,Output" bitfld.long 0x0 0. " P20 ,Pin 20" "Input,Output" group.long 0x20C++0x3 line.long 0x0 "DDR3,Port input/output Direction Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Input,Output" bitfld.long 0x0 14. " P3E ,Pin 3E" "Input,Output" bitfld.long 0x0 13. " P3D ,Pin 3D" "Input,Output" bitfld.long 0x0 12. " P3C ,Pin 3C" "Input,Output" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Input,Output" bitfld.long 0x0 10. " P3A ,Pin 3A" "Input,Output" bitfld.long 0x0 9. " P39 ,Pin 39" "Input,Output" bitfld.long 0x0 8. " P38 ,Pin 38" "Input,Output" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Input,Output" bitfld.long 0x0 6. " P36 ,Pin 36" "Input,Output" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 5. " P35 ,Pin 35" "Input,Output" bitfld.long 0x0 4. " P34 ,Pin 34" "Input,Output" bitfld.long 0x0 3. " P33 ,Pin 33" "Input,Output" bitfld.long 0x0 2. " P32 ,Pin 32" "Input,Output" textline " " bitfld.long 0x0 1. " P31 ,Pin 31" "Input,Output" bitfld.long 0x0 0. " P30 ,Pin 30" "Input,Output" endif group.long 0x210++0x3 line.long 0x0 "DDR4,Port input/output Direction Setting Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Input,Output" bitfld.long 0x0 13. " P4D ,Pin 4D" "Input,Output" bitfld.long 0x0 12. " P4C ,Pin 4C" "Input,Output" bitfld.long 0x0 11. " P4B ,Pin 4B" "Input,Output" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Input,Output" bitfld.long 0x0 9. " P49 ,Pin 49" "Input,Output" bitfld.long 0x0 8. " P48 ,Pin 48" "Input,Output" bitfld.long 0x0 7. " P47 ,Pin 47" "Input,Output" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Input,Output" bitfld.long 0x0 5. " P45 ,Pin 45" "Input,Output" bitfld.long 0x0 4. " P44 ,Pin 44" "Input,Output" bitfld.long 0x0 3. " P43 ,Pin 43" "Input,Output" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Input,Output" bitfld.long 0x0 1. " P41 ,Pin 41" "Input,Output" bitfld.long 0x0 0. " P40 ,Pin 40" "Input,Output" group.long 0x214++0x3 line.long 0x0 "DDR5,Port input/output Direction Setting Register 5" sif (cpuis("MB9BF???T")) bitfld.long 0x0 13. " P5D ,Pin 5D" "Input,Output" bitfld.long 0x0 12. " P5C ,Pin 5C" "Input,Output" textline " " endif bitfld.long 0x0 11. " P5B ,Pin 5B" "Input,Output" bitfld.long 0x0 10. " P5A ,Pin 5A" "Input,Output" bitfld.long 0x0 9. " P59 ,Pin 59" "Input,Output" bitfld.long 0x0 8. " P58 ,Pin 58" "Input,Output" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Input,Output" bitfld.long 0x0 6. " P56 ,Pin 56" "Input,Output" bitfld.long 0x0 5. " P55 ,Pin 55" "Input,Output" bitfld.long 0x0 4. " P54 ,Pin 54" "Input,Output" textline " " bitfld.long 0x0 3. " P53 ,Pin 53" "Input,Output" bitfld.long 0x0 2. " P52 ,Pin 52" "Input,Output" bitfld.long 0x0 1. " P51 ,Pin 51" "Input,Output" bitfld.long 0x0 0. " P50 ,Pin 50" "Input,Output" group.long 0x218++0x3 line.long 0x0 "DDR6,Port input/output Direction Setting Register 6" bitfld.long 0x0 2. " P62 ,Pin 62" "Input,Output" bitfld.long 0x0 1. " P61 ,Pin 61" "Input,Output" bitfld.long 0x0 0. " P60 ,Pin 60" "Input,Output" group.long 0x21C++0x3 line.long 0x0 "DDR7,Port input/output Direction Setting Register 7" sif (cpuis("MB9BF???T")) bitfld.long 0x0 15. " P7F ,Pin 7F" "Input,Output" bitfld.long 0x0 14. " P7E ,Pin 7E" "Input,Output" bitfld.long 0x0 13. " P7D ,Pin 7D" "Input,Output" bitfld.long 0x0 12. " P7C ,Pin 7C" "Input,Output" textline " " bitfld.long 0x0 11. " P7B ,Pin 7B" "Input,Output" textline " " endif bitfld.long 0x0 10. " P7A ,Pin 7A" "Input,Output" bitfld.long 0x0 9. " P79 ,Pin 79" "Input,Output" bitfld.long 0x0 8. " P78 ,Pin 78" "Input,Output" bitfld.long 0x0 7. " P77 ,Pin 77" "Input,Output" textline " " bitfld.long 0x0 6. " P76 ,Pin 76" "Input,Output" bitfld.long 0x0 5. " P75 ,Pin 75" "Input,Output" bitfld.long 0x0 4. " P74 ,Pin 74" "Input,Output" bitfld.long 0x0 3. " P73 ,Pin 73" "Input,Output" textline " " bitfld.long 0x0 2. " P72 ,Pin 72" "Input,Output" bitfld.long 0x0 1. " P71 ,Pin 71" "Input,Output" bitfld.long 0x0 0. " P70 ,Pin 70" "Input,Output" group.long 0x220++0x3 line.long 0x0 "DDR8,Port input/output Direction Setting Register 8" bitfld.long 0x0 3. " P83 ,Pin 83" "Input,Output" bitfld.long 0x0 2. " P82 ,Pin 82" "Input,Output" bitfld.long 0x0 1. " P81 ,Pin 81" "Input,Output" bitfld.long 0x0 0. " P80 ,Pin 80" "Input,Output" sif (cpuis("MB9BF???T")) group.long 0x224++0x3 line.long 0x0 "DDR9,Port input/output Direction Setting Register 9" bitfld.long 0x0 5. " P95 ,Pin 95" "Input,Output" bitfld.long 0x0 4. " P94 ,Pin 94" "Input,Output" bitfld.long 0x0 3. " P93 ,Pin 93" "Input,Output" bitfld.long 0x0 2. " P92 ,Pin 92" "Input,Output" textline " " bitfld.long 0x0 1. " P91 ,Pin 91" "Input,Output" bitfld.long 0x0 0. " P90 ,Pin 90" "Input,Output" endif group.long 0x228++0x3 line.long 0x0 "DDRA,Port input/output Direction Setting Register A" bitfld.long 0x0 5. " PA5 ,Pin A5" "Input,Output" bitfld.long 0x0 4. " PA4 ,Pin A4" "Input,Output" bitfld.long 0x0 3. " PA3 ,Pin A3" "Input,Output" bitfld.long 0x0 2. " PA2 ,Pin A2" "Input,Output" textline " " bitfld.long 0x0 1. " PA1 ,Pin A1" "Input,Output" bitfld.long 0x0 0. " PA0 ,Pin A0" "Input,Output" sif (cpuis("MB9BF???T")) group.long 0x22C++0x3 line.long 0x0 "DDRB,Port input/output Direction Setting Register B" bitfld.long 0x0 7. " PB7 ,Pin B7" "Input,Output" bitfld.long 0x0 6. " PB6 ,Pin B6" "Input,Output" bitfld.long 0x0 5. " PB5 ,Pin B5" "Input,Output" bitfld.long 0x0 4. " PB4 ,Pin B4" "Input,Output" textline " " bitfld.long 0x0 3. " PB3 ,Pin B3" "Input,Output" bitfld.long 0x0 2. " PB2 ,Pin B2" "Input,Output" bitfld.long 0x0 1. " PB1 ,Pin B1" "Input,Output" bitfld.long 0x0 0. " PB0 ,Pin B0" "Input,Output" endif group.long 0x230++0x3 line.long 0x0 "DDRC,Port input/output Direction Setting Register C" bitfld.long 0x0 3. " PC3 ,Pin C3" "Input,Output" bitfld.long 0x0 2. " PC2 ,Pin C2" "Input,Output" bitfld.long 0x0 1. " PC1 ,Pin C1" "Input,Output" bitfld.long 0x0 0. " PC0 ,Pin C0" "Input,Output" group.long 0x234++0x3 line.long 0x0 "DDRD,Port input/output Direction Setting Register D" bitfld.long 0x0 3. " PD3 ,Pin D3" "Input,Output" bitfld.long 0x0 2. " PD2 ,Pin D2" "Input,Output" bitfld.long 0x0 1. " PD1 ,Pin D1" "Input,Output" bitfld.long 0x0 0. " PD0 ,Pin D0" "Input,Output" group.long 0x238++0x3 line.long 0x0 "DDRE,Port input/output Direction Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Input,Output" bitfld.long 0x0 2. " PE2 ,Pin E2" "Input,Output" bitfld.long 0x0 1. " PE1 ,Pin E1" "Input,Output" bitfld.long 0x0 0. " PE0 ,Pin E0" "Input,Output" group.long 0x23C++0x3 line.long 0x0 "DDRF,Port input/output Direction Setting Register F" bitfld.long 0x0 6. " PF6 ,Pin F6" "Input,Output" bitfld.long 0x0 5. " PF5 ,Pin F5" "Input,Output" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 4. " PF4 ,Pin F4" "Input,Output" bitfld.long 0x0 3. " PF3 ,Pin F3" "Input,Output" bitfld.long 0x0 2. " PF2 ,Pin F2" "Input,Output" bitfld.long 0x0 1. " PF1 ,Pin F1" "Input,Output" textline " " bitfld.long 0x0 0. " PF0 ,Pin F0" "Input,Output" endif tree.end tree "Port Input Data Registers" group.long 0x300++0x3 line.long 0x0 "PDIR0,Port Input Data Register 0" bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" textline " " bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" group.long 0x304++0x3 line.long 0x0 "PDIR1,Port Input Data Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x0 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x0 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x0 12. " P1C ,Pin 1C" "Low,High" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x0 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x0 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" group.long 0x308++0x3 line.long 0x0 "PDIR2,Port Input Data Register 2" bitfld.long 0x0 9. " P29 ,Pin 29" "Low,High" bitfld.long 0x0 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x0 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x0 6. " P26 ,Pin 26" "Low,High" textline " " bitfld.long 0x0 5. " P25 ,Pin 25" "Low,High" bitfld.long 0x0 4. " P24 ,Pin 24" "Low,High" bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" textline " " bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x0 0. " P20 ,Pin 20" "Low,High" group.long 0x30C++0x3 line.long 0x0 "PDIR3,Port Input Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" bitfld.long 0x0 8. " P38 ,Pin 38" "Low,High" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Low,High" bitfld.long 0x0 6. " P36 ,Pin 36" "Low,High" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 5. " P35 ,Pin 35" "Low,High" bitfld.long 0x0 4. " P34 ,Pin 34" "Low,High" bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" textline " " bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" endif group.long 0x310++0x3 line.long 0x0 "PDIR4,Port Input Data Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x0 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x0 4. " P44 ,Pin 44" "Low,High" bitfld.long 0x0 3. " P43 ,Pin 43" "Low,High" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x0 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x0 0. " P40 ,Pin 40" "Low,High" group.long 0x314++0x3 line.long 0x0 "PDIR5,Port Input Data Register 5" sif (cpuis("MB9BF???T")) bitfld.long 0x0 13. " P5D ,Pin 5D" "Low,High" bitfld.long 0x0 12. " P5C ,Pin 5C" "Low,High" textline " " endif bitfld.long 0x0 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x0 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x0 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x0 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Low,High" bitfld.long 0x0 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x0 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x0 4. " P54 ,Pin 54" "Low,High" textline " " bitfld.long 0x0 3. " P53 ,Pin 53" "Low,High" bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" group.long 0x318++0x3 line.long 0x0 "PDIR6,Port Input Data Register 6" bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" group.long 0x31C++0x3 line.long 0x0 "PDIR7,Port Input Data Register 7" sif (cpuis("MB9BF???T")) bitfld.long 0x0 15. " P7F ,Pin 7F" "Low,High" bitfld.long 0x0 14. " P7E ,Pin 7E" "Low,High" bitfld.long 0x0 13. " P7D ,Pin 7D" "Low,High" bitfld.long 0x0 12. " P7C ,Pin 7C" "Low,High" textline " " bitfld.long 0x0 11. " P7B ,Pin 7B" "Low,High" textline " " endif bitfld.long 0x0 10. " P7A ,Pin 7A" "Low,High" bitfld.long 0x0 9. " P79 ,Pin 79" "Low,High" bitfld.long 0x0 8. " P78 ,Pin 78" "Low,High" bitfld.long 0x0 7. " P77 ,Pin 77" "Low,High" textline " " bitfld.long 0x0 6. " P76 ,Pin 76" "Low,High" bitfld.long 0x0 5. " P75 ,Pin 75" "Low,High" bitfld.long 0x0 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x0 3. " P73 ,Pin 73" "Low,High" textline " " bitfld.long 0x0 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x0 1. " P71 ,Pin 71" "Low,High" bitfld.long 0x0 0. " P70 ,Pin 70" "Low,High" group.long 0x320++0x3 line.long 0x0 "PDIR8,Port Input Data Register 8" bitfld.long 0x0 3. " P83 ,Pin 83" "Low,High" bitfld.long 0x0 2. " P82 ,Pin 82" "Low,High" bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" sif (cpuis("MB9BF???T")) group.long 0x324++0x3 line.long 0x0 "PDIR9,Port Input Data Register 9" bitfld.long 0x0 5. " P95 ,Pin 95" "Low,High" bitfld.long 0x0 4. " P94 ,Pin 94" "Low,High" bitfld.long 0x0 3. " P93 ,Pin 93" "Low,High" bitfld.long 0x0 2. " P92 ,Pin 92" "Low,High" textline " " bitfld.long 0x0 1. " P91 ,Pin 91" "Low,High" bitfld.long 0x0 0. " P90 ,Pin 90" "Low,High" endif group.long 0x328++0x3 line.long 0x0 "PDIRA,Port Input Data Register A" bitfld.long 0x0 5. " PA5 ,Pin A5" "Low,High" bitfld.long 0x0 4. " PA4 ,Pin A4" "Low,High" bitfld.long 0x0 3. " PA3 ,Pin A3" "Low,High" bitfld.long 0x0 2. " PA2 ,Pin A2" "Low,High" textline " " bitfld.long 0x0 1. " PA1 ,Pin A1" "Low,High" bitfld.long 0x0 0. " PA0 ,Pin A0" "Low,High" sif (cpuis("MB9BF???T")) group.long 0x32C++0x3 line.long 0x0 "PDIRB,Port Input Data Register B" bitfld.long 0x0 7. " PB7 ,Pin B7" "Low,High" bitfld.long 0x0 6. " PB6 ,Pin B6" "Low,High" bitfld.long 0x0 5. " PB5 ,Pin B5" "Low,High" bitfld.long 0x0 4. " PB4 ,Pin B4" "Low,High" textline " " bitfld.long 0x0 3. " PB3 ,Pin B3" "Low,High" bitfld.long 0x0 2. " PB2 ,Pin B2" "Low,High" bitfld.long 0x0 1. " PB1 ,Pin B1" "Low,High" bitfld.long 0x0 0. " PB0 ,Pin B0" "Low,High" endif group.long 0x330++0x3 line.long 0x0 "PDIRC,Port Input Data Register C" bitfld.long 0x0 15. " PCF ,Pin CF" "Low,High" bitfld.long 0x0 14. " PCE ,Pin CE" "Low,High" bitfld.long 0x0 13. " PCD ,Pin CD" "Low,High" bitfld.long 0x0 12. " PCC ,Pin CC" "Low,High" textline " " bitfld.long 0x0 11. " PCB ,Pin CB" "Low,High" bitfld.long 0x0 10. " PCA ,Pin CA" "Low,High" bitfld.long 0x0 9. " PC9 ,Pin C9" "Low,High" bitfld.long 0x0 8. " PC8 ,Pin C8" "Low,High" textline " " bitfld.long 0x0 7. " PC7 ,Pin C7" "Low,High" bitfld.long 0x0 6. " PC6 ,Pin C6" "Low,High" bitfld.long 0x0 5. " PC5 ,Pin C5" "Low,High" bitfld.long 0x0 4. " PC4 ,Pin C4" "Low,High" textline " " bitfld.long 0x0 3. " PC3 ,Pin C3" "Low,High" bitfld.long 0x0 2. " PC2 ,Pin C2" "Low,High" bitfld.long 0x0 1. " PC1 ,Pin C1" "Low,High" bitfld.long 0x0 0. " PC0 ,Pin C0" "Low,High" group.long 0x334++0x3 line.long 0x0 "PDIRD,Port Input Data Register D" bitfld.long 0x0 3. " PD3 ,Pin D3" "Low,High" bitfld.long 0x0 2. " PD2 ,Pin D2" "Low,High" bitfld.long 0x0 1. " PD1 ,Pin D1" "Low,High" bitfld.long 0x0 0. " PD0 ,Pin D0" "Low,High" group.long 0x338++0x3 line.long 0x0 "PDIRE,Port Input Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 1. " PE1 ,Pin E1" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" group.long 0x33C++0x3 line.long 0x0 "PDIRF,Port Input Data Register F" bitfld.long 0x0 6. " PF6 ,Pin F6" "Low,High" bitfld.long 0x0 5. " PF5 ,Pin F5" "Low,High" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 4. " PF4 ,Pin F4" "Low,High" bitfld.long 0x0 3. " PF3 ,Pin F3" "Low,High" bitfld.long 0x0 2. " PF2 ,Pin F2" "Low,High" bitfld.long 0x0 1. " PF1 ,Pin F1" "Low,High" textline " " bitfld.long 0x0 0. " PF0 ,Pin F0" "Low,High" endif tree.end tree "Port Output Data Registers" group.long 0x400++0x3 line.long 0x0 "PDOR0,Port Output Data Register 0" bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" textline " " bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" textline " " bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" group.long 0x404++0x3 line.long 0x0 "PDOR1,Port Output Data Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x0 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x0 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x0 12. " P1C ,Pin 1C" "Low,High" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x0 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x0 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" group.long 0x408++0x3 line.long 0x0 "PDOR2,Port Output Data Register 2" bitfld.long 0x0 9. " P29 ,Pin 29" "Low,High" bitfld.long 0x0 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x0 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x0 6. " P26 ,Pin 26" "Low,High" textline " " bitfld.long 0x0 5. " P25 ,Pin 25" "Low,High" bitfld.long 0x0 4. " P24 ,Pin 24" "Low,High" bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" textline " " bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x0 0. " P20 ,Pin 20" "Low,High" group.long 0x40C++0x3 line.long 0x0 "PDOR3,Port Output Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" bitfld.long 0x0 8. " P38 ,Pin 38" "Low,High" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Low,High" bitfld.long 0x0 6. " P36 ,Pin 36" "Low,High" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 5. " P35 ,Pin 35" "Low,High" bitfld.long 0x0 4. " P34 ,Pin 34" "Low,High" textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" endif group.long 0x410++0x3 line.long 0x0 "PDOR4,Port Output Data Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x0 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x0 4. " P44 ,Pin 44" "Low,High" bitfld.long 0x0 3. " P43 ,Pin 43" "Low,High" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x0 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x0 0. " P40 ,Pin 40" "Low,High" group.long 0x414++0x3 line.long 0x0 "PDOR5,Port Output Data Register 5" sif (cpuis("MB9BF???T")) bitfld.long 0x0 13. " P5D ,Pin 5D" "Low,High" bitfld.long 0x0 12. " P5C ,Pin 5C" "Low,High" textline " " endif bitfld.long 0x0 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x0 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x0 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x0 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Low,High" bitfld.long 0x0 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x0 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x0 4. " P54 ,Pin 54" "Low,High" textline " " bitfld.long 0x0 3. " P53 ,Pin 53" "Low,High" bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" group.long 0x418++0x3 line.long 0x0 "PDOR6,Port Output Data Register 6" bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" group.long 0x41C++0x3 line.long 0x0 "PDOR7,Port Output Data Register 7" sif (cpuis("MB9BF???T")) bitfld.long 0x0 15. " P7F ,Pin 7F" "Low,High" bitfld.long 0x0 14. " P7E ,Pin 7E" "Low,High" bitfld.long 0x0 13. " P7D ,Pin 7D" "Low,High" bitfld.long 0x0 12. " P7C ,Pin 7C" "Low,High" textline " " bitfld.long 0x0 11. " P7B ,Pin 7B" "Low,High" textline " " endif bitfld.long 0x0 10. " P7A ,Pin 7A" "Low,High" bitfld.long 0x0 9. " P79 ,Pin 79" "Low,High" bitfld.long 0x0 8. " P78 ,Pin 78" "Low,High" bitfld.long 0x0 7. " P77 ,Pin 77" "Low,High" textline " " bitfld.long 0x0 6. " P76 ,Pin 76" "Low,High" bitfld.long 0x0 5. " P75 ,Pin 75" "Low,High" bitfld.long 0x0 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x0 3. " P73 ,Pin 73" "Low,High" textline " " bitfld.long 0x0 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x0 1. " P71 ,Pin 71" "Low,High" bitfld.long 0x0 0. " P70 ,Pin 70" "Low,High" group.long 0x420++0x3 line.long 0x0 "PDOR8,Port Output Data Register 8" bitfld.long 0x0 3. " P83 ,Pin 83" "Low,High" bitfld.long 0x0 2. " P82 ,Pin 82" "Low,High" bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" sif (cpuis("MB9BF???T")) group.long 0x424++0x3 line.long 0x0 "PDOR9,Port Output Data Register 9" bitfld.long 0x0 5. " P95 ,Pin 95" "Low,High" bitfld.long 0x0 4. " P94 ,Pin 94" "Low,High" bitfld.long 0x0 3. " P93 ,Pin 93" "Low,High" bitfld.long 0x0 2. " P92 ,Pin 92" "Low,High" textline " " bitfld.long 0x0 1. " P91 ,Pin 91" "Low,High" bitfld.long 0x0 0. " P90 ,Pin 90" "Low,High" endif group.long 0x428++0x3 line.long 0x0 "PDORA,Port Output Data Register A" bitfld.long 0x0 5. " PA5 ,Pin A5" "Low,High" bitfld.long 0x0 4. " PA4 ,Pin A4" "Low,High" bitfld.long 0x0 3. " PA3 ,Pin A3" "Low,High" bitfld.long 0x0 2. " PA2 ,Pin A2" "Low,High" textline " " bitfld.long 0x0 1. " PA1 ,Pin A1" "Low,High" bitfld.long 0x0 0. " PA0 ,Pin A0" "Low,High" sif (cpuis("MB9BF???T")) group.long 0x42C++0x3 line.long 0x0 "PDORB,Port Output Data Register B" bitfld.long 0x0 15. " PBF ,Pin BF" "Low,High" bitfld.long 0x0 14. " PBE ,Pin BE" "Low,High" bitfld.long 0x0 13. " PBD ,Pin BD" "Low,High" bitfld.long 0x0 12. " PBC ,Pin BC" "Low,High" textline " " bitfld.long 0x0 11. " PBB ,Pin BB" "Low,High" bitfld.long 0x0 10. " PBA ,Pin BA" "Low,High" bitfld.long 0x0 9. " PB9 ,Pin B9" "Low,High" bitfld.long 0x0 8. " PB8 ,Pin B8" "Low,High" textline " " bitfld.long 0x0 7. " PB7 ,Pin B7" "Low,High" bitfld.long 0x0 6. " PB6 ,Pin B6" "Low,High" bitfld.long 0x0 5. " PB5 ,Pin B5" "Low,High" bitfld.long 0x0 4. " PB4 ,Pin B4" "Low,High" textline " " bitfld.long 0x0 3. " PB3 ,Pin B3" "Low,High" bitfld.long 0x0 2. " PB2 ,Pin B2" "Low,High" bitfld.long 0x0 1. " PB1 ,Pin B1" "Low,High" bitfld.long 0x0 0. " PB0 ,Pin B0" "Low,High" endif group.long 0x430++0x3 line.long 0x0 "PDORC,Port Output Data Register C" bitfld.long 0x0 15. " PCF ,Pin CF" "Low,High" bitfld.long 0x0 14. " PCE ,Pin CE" "Low,High" bitfld.long 0x0 13. " PCD ,Pin CD" "Low,High" bitfld.long 0x0 12. " PCC ,Pin CC" "Low,High" textline " " bitfld.long 0x0 11. " PCB ,Pin CB" "Low,High" bitfld.long 0x0 10. " PCA ,Pin CA" "Low,High" bitfld.long 0x0 9. " PC9 ,Pin C9" "Low,High" bitfld.long 0x0 8. " PC8 ,Pin C8" "Low,High" textline " " bitfld.long 0x0 7. " PC7 ,Pin C7" "Low,High" bitfld.long 0x0 6. " PC6 ,Pin C6" "Low,High" bitfld.long 0x0 5. " PC5 ,Pin C5" "Low,High" bitfld.long 0x0 4. " PC4 ,Pin C4" "Low,High" textline " " bitfld.long 0x0 3. " PC3 ,Pin C3" "Low,High" bitfld.long 0x0 2. " PC2 ,Pin C2" "Low,High" bitfld.long 0x0 1. " PC1 ,Pin C1" "Low,High" bitfld.long 0x0 0. " PC0 ,Pin C0" "Low,High" group.long 0x434++0x3 line.long 0x0 "PDORD,Port Output Data Register D" bitfld.long 0x0 3. " PD3 ,Pin D3" "Low,High" bitfld.long 0x0 2. " PD2 ,Pin D2" "Low,High" bitfld.long 0x0 1. " PD1 ,Pin D1" "Low,High" bitfld.long 0x0 0. " PD0 ,Pin D0" "Low,High" group.long 0x438++0x3 line.long 0x0 "PDORE,Port Output Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 1. " PE1 ,Pin E1" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" group.long 0x43C++0x3 line.long 0x0 "PDORF,Port Output Data Register F" bitfld.long 0x0 6. " PF6 ,Pin F6" "Low,High" bitfld.long 0x0 5. " PF5 ,Pin F5" "Low,High" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x0 4. " PF4 ,Pin F4" "Low,High" bitfld.long 0x0 3. " PF3 ,Pin F3" "Low,High" bitfld.long 0x0 2. " PF2 ,Pin F2" "Low,High" bitfld.long 0x0 1. " PF1 ,Pin F1" "Low,High" textline " " bitfld.long 0x0 0. " PF0 ,Pin F0" "Low,High" endif tree.end tree "Analog Input Setting Register" group.long 0x500++0x3 line.long 0x0 "ADE,Analog Input Setting Register" bitfld.long 0x00 31. " P31 ,Pin 31" "Digital I/O,Analog IN" bitfld.long 0x00 30. " P30 ,Pin 30" "Digital I/O,Analog IN" bitfld.long 0x00 29. " P29 ,Pin 29" "Digital I/O,Analog IN" bitfld.long 0x00 28. " P28 ,Pin 28" "Digital I/O,Analog IN" textline " " bitfld.long 0x00 27. " P27 ,Pin 27" "Digital I/O,Analog IN" bitfld.long 0x00 26. " P26 ,Pin 26" "Digital I/O,Analog IN" bitfld.long 0x00 25. " P25 ,Pin 25" "Digital I/O,Analog IN" bitfld.long 0x00 24. " P24 ,Pin 24" "Digital I/O,Analog IN" textline " " sif cpuis("MB9BF???T") bitfld.long 0x00 23. " P23 ,Pin 23" "Digital I/O,Analog IN" bitfld.long 0x00 22. " P22 ,Pin 22" "Digital I/O,Analog IN" bitfld.long 0x00 21. " P21 ,Pin 21" "Digital I/O,Analog IN" bitfld.long 0x00 20. " P20 ,Pin 20" "Digital I/O,Analog IN" textline " " bitfld.long 0x00 19. " P19 ,Pin 19" "Digital I/O,Analog IN" bitfld.long 0x00 18. " P18 ,Pin 18" "Digital I/O,Analog IN" bitfld.long 0x00 17. " P17 ,Pin 17" "Digital I/O,Analog IN" bitfld.long 0x00 16. " P16 ,Pin 16" "Digital I/O,Analog IN" textline " " endif bitfld.long 0x0 15. " P15 ,Pin 1F" "Digital I/O,Analog IN" bitfld.long 0x0 14. " P14 ,Pin 1E" "Digital I/O,Analog IN" bitfld.long 0x0 13. " P13 ,Pin 1D" "Digital I/O,Analog IN" bitfld.long 0x0 12. " P12 ,Pin 1C" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 11. " P11 ,Pin 1B" "Digital I/O,Analog IN" bitfld.long 0x0 10. " P10 ,Pin 1A" "Digital I/O,Analog IN" bitfld.long 0x0 9. " P09 ,Pin 19" "Digital I/O,Analog IN" bitfld.long 0x0 8. " P08 ,Pin 18" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 7. " P07 ,Pin 17" "Digital I/O,Analog IN" bitfld.long 0x0 6. " P06 ,Pin 16" "Digital I/O,Analog IN" bitfld.long 0x0 5. " P05 ,Pin 15" "Digital I/O,Analog IN" bitfld.long 0x0 4. " P04 ,Pin 14" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 3. " P03 ,Pin 13" "Digital I/O,Analog IN" bitfld.long 0x0 2. " P02 ,Pin 12" "Digital I/O,Analog IN" bitfld.long 0x0 1. " P01 ,Pin 11" "Digital I/O,Analog IN" bitfld.long 0x0 0. " P00 ,Pin 10" "Digital I/O,Analog IN" tree.end tree "Extended Pin Function Setting Register" group.long 0x600++0xB line.long 0x0 "EPFR00,Extended Pin Function Setting Register 00" bitfld.long 0x00 25. " TRC1E ,Select wether to use two pins of TRACED2 and TRACED3" "Not used,Used" bitfld.long 0x00 24. " TRC0E ,Select wether to use three pins of TRACECLK, TRACED0, and TRACED1" "Not used,Used" textline " " bitfld.long 0x00 17. " JTAGEN1S ,Select wether to use two pins of TRSTX and TDI" "Not used,Used" bitfld.long 0x00 16. " JTAGEN0S ,Select wether to use three pins of TCK, TMS, and TDO" "Not used,Used" textline " " sif (cpuis("MB9BF21??")||cpuis("MB9BF31??")||cpuis("MB9BF51??")||cpuis("MB9BF61??")) bitfld.long 0x00 13. " USBP1E ,Selects wether to produce output D+ resistor control signal (HCONTX) for USBch.1" "Not produced,Produced" bitfld.long 0x00 9. " USBP0E ,Selects wether to produce output D+ resistor control signal (HCONTX) for USBch.0" "Not produced,Produced" textline " " endif bitfld.long 0x00 1.--2. " CROUTE ,Selects internal high-speed CR oscillation output" "Not produced,CROUT_0,CROUT_1,CROUT_2" bitfld.long 0x00 0. " NMIS ,Select wether to use the NMIX pin" "Not used,Used" line.long 0x4 "EPFR01,Extended Pin Function Setting Register 01" sif (cpuis("MB9BF???T")) bitfld.long 0x04 29.--31. " IC03S ,IC03 Input Select Bit" "IC03_0,IC03_0,IC03_1,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" else bitfld.long 0x04 29.--31. " IC03S ,IC03 Input Select Bit" ",,IC03_1,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" endif textline " " bitfld.long 0x04 26.--28. " IS02S ,IC02 Input Select Bit" "IC02_0,IC02_0,IC02_1,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x04 23.--25. " IC01S ,IC01 Input Select Bit" "IC01_0,IC01_0,IC01_1,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x04 20.--22. " IC00S ,IC00 Input Select Bit" "IC00_0,IC00_0,IC00_1,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x04 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "FRCK0_0,FRCK0_0,FRCK0_1,FRCK0_2" else bitfld.long 0x04 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "Reserved,Reserved,FRCK0_1,FRCK0_2" endif textline " " bitfld.long 0x04 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,DTTIX0_1,?..." bitfld.long 0x04 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" textline " " bitfld.long 0x04 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,RTO05_1,?..." bitfld.long 0x04 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,RTO04_1,?..." bitfld.long 0x04 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,RTO03_1,?..." textline " " bitfld.long 0x04 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,RTO02_1,?..." bitfld.long 0x04 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,RTO01_1,?..." bitfld.long 0x04 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,RTO00_1,?..." line.long 0x8 "EPFR02,Extended Pin Function Setting Register 02" bitfld.long 0x08 29.--31. " IC13S ,IC13 Input Select Bit" "IC13_0,IC13_0,IC13_1,Reserved,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x08 26.--28. " IS12S ,IC12 Input Select Bit" "IC12_0,IC12_0,IC12_1,Reserved,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x08 23.--25. " IC11S ,IC11 Input Select Bit" "IC11_0,IC11_0,IC11_1,Reserved,MFSch.1LSYN,MFSch.5LSYN,?..." textline " " bitfld.long 0x08 20.--22. " IC10S ,IC10 Input Select Bit" "IC10_0,IC10_0,IC10_1,Reserved,MFSch.0LSYN,MFSch.4LSYN,?..." bitfld.long 0x08 18.--19. " FRCK1S ,FRCK1 Input Select Bit" "FRCK1_0,FRCK1_0,FRCK1_1,?..." bitfld.long 0x08 16.--17. " DTTI1S ,DTTIX1 Input Select Bit" "DTTIX1_0,DTTIX1_0,DTTIX1_1,?..." textline " " bitfld.long 0x08 12. " DTTI1C ,DTTIX1 Function Select Bit" "Not switched,Switched" bitfld.long 0x08 10.--11. " RTO15E ,RTO15E Output Select Bit" "Not produced,RTO15_0,RTO15_1,?..." bitfld.long 0x08 8.--9. " RTO14E ,RTO14E Output Select Bit" "Not produced,RTO14_0,RTO14_1,?..." textline " " bitfld.long 0x08 6.--7. " RTO13E ,RTO13E Output Select Bit" "Not produced,RTO13_0,RTO13_1,?..." bitfld.long 0x08 4.--5. " RTO012E ,RTO12E Output Select Bit" "Not produced,RTO12_0,RTO12_1,?..." bitfld.long 0x08 2.--3. " RTO11E ,RTO11E Output Select Bit" "Not produced,RTO11_0,RTO11_1,?..." textline " " bitfld.long 0x08 0.--1. " RTO10E ,RTO10E Output Select Bit" "Not produced,RTO10_0,RTO10_1,?..." group.long 0x60C++0x3 line.long 0x00 "EPFR03,Extended Pin Function Setting Register 03" sif (cpuis("MB9BF???T")) bitfld.long 0x00 29.--31. " IC23S ,IC23 Input Select Bit" "IC23_0,IC23_0,IC23_1,,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x00 26.--28. " IS22S ,IC22 Input Select Bit" "IC22_0,IC22_0,IC22_1,,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x00 23.--25. " IC21S ,IC21 Input Select Bit" "IC21_0,IC21_0,IC21_1,,MFSch.1LSYN,MFSch.5LSYN,?..." textline " " bitfld.long 0x00 20.--22. " IC20S ,IC20 Input Select Bit" "IC20_0,IC20_0,IC20_1,,MFSch.0LSYN,MFSch.4LSYN,?..." bitfld.long 0x00 18.--19. " FRCK2S ,FRCK2 Input Select Bit" "FRCK2_0,FRCK2_0,FRCK2_1,?..." bitfld.long 0x00 16.--17. " DTTI2S ,DTTIX2 Input Select Bit" "DTTIX2_0,DTTIX2_0,DTTIX2_1,?..." textline " " bitfld.long 0x00 12. " DTTI2C ,DTTIX2 Function Select Bit" "Not switched,Switched" bitfld.long 0x00 10.--11. " RTO25E ,RTO25E Output Select Bit" "Not produced,RTO25_0,RTO25_1,?..." bitfld.long 0x00 8.--9. " RTO24E ,RTO24E Output Select Bit" "Not produced,RTO24_0,RTO24_1,?..." textline " " bitfld.long 0x00 6.--7. " RTO23E ,RTO23E Output Select Bit" "Not produced,RTO23_0,RTO23_1,?..." bitfld.long 0x00 4.--5. " RTO022E ,RTO22E Output Select Bit" "Not produced,RTO22_0,RTO22_1,?..." bitfld.long 0x00 2.--3. " RTO21E ,RTO21E Output Select Bit" "Not produced,RTO21_0,RTO21_1,?..." textline " " bitfld.long 0x00 0.--1. " RTO20E ,RTO20E Output Select Bit" "Not produced,RTO20_0,RTO20_1,?..." else bitfld.long 0x00 29.--31. " IC23S ,IC23 Input Select Bit" "IC23_0,IC23_0,,,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x00 26.--28. " IS22S ,IC22 Input Select Bit" "IC22_0,IC22_0,,,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x00 23.--25. " IC21S ,IC21 Input Select Bit" "IC21_0,IC21_0,,,MFSch.1LSYN,MFSch.5LSYN,?..." textline " " bitfld.long 0x00 20.--22. " IC20S ,IC20 Input Select Bit" "IC20_0,IC20_0,,,MFSch.0LSYN,MFSch.4LSYN,?..." bitfld.long 0x00 18.--19. " FRCK2S ,FRCK2 Input Select Bit" "FRCK2_0,FRCK2_0,?..." bitfld.long 0x00 16.--17. " DTTI2S ,DTTIX2 Input Select Bit" "DTTIX2_0,DTTIX2_0,?..." textline " " bitfld.long 0x00 12. " DTTI2C ,DTTIX2 Function Select Bit" "Not switched,Switched" bitfld.long 0x00 10.--11. " RTO25E ,RTO25E Output Select Bit" "Not produced,RTO25_0,?..." bitfld.long 0x00 8.--9. " RTO24E ,RTO24E Output Select Bit" "Not produced,RTO24_0,?..." textline " " bitfld.long 0x00 6.--7. " RTO23E ,RTO23E Output Select Bit" "Not produced,RTO23_0,?..." bitfld.long 0x00 4.--5. " RTO022E ,RTO22E Output Select Bit" "Not produced,RTO22_0,?..." bitfld.long 0x00 2.--3. " RTO21E ,RTO21E Output Select Bit" "Not produced,RTO21_0,?..." textline " " bitfld.long 0x00 0.--1. " RTO20E ,RTO20E Output Select Bit" "Not produced,RTO20_0,?..." endif group.long 0x610++0x2F line.long 0x0 "EPFR04,Extended Pin Function Setting Register 04" sif (cpuis("MB9BF???T")) bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,TIOB3_1,TIOB3_2" else bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,,TIOB3_2" endif textline " " bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,TIOA3_0,TIOA3_1,TIOA3_2" bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" "TIOA3_0,TIOA3_0,TIOA3_1,TIOA3_2" textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2" else bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,,TIOB2_2" endif textline " " bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,TIOA2_0,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" "TIOA2_0,TIOA2_0,TIOA2_1,TIOA2_2" textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,TIOB1_1,TIOB1_2" else bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,,TIOB1_2" endif textline " " bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,TIOA1_0,TIOA1_1,TIOA1_2" bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" "TIOA1_0,TIOA1_0,TIOA1_1,TIOA1_2" textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2,?..." else bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,,TIOB0_2,?..." endif textline " " bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,TIOA0_0,TIOA0_1,TIOA0_2" line.long 0x4 "EPFR05,Extended Pin Function Setting Register 05" sif (cpuis("MB9BF???T")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" "TIOB7_0,TIOB7_0,TIOB7_1,TIOB7_2" bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,TIOA7_0,TIOA7_1,TIOA7_2" bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" "TIOA7_0,TIOA7_0,TIOA7_1,TIOA7_2" textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" "TIOB6_0,TIOB6_0,TIOB6_1,TIOB6_2" bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,TIOA6_0,TIOA6_1,TIOA6_2" else bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,TIOB7_2" bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,TIOA7_2" bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,TIOA7_2" textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" ",,TIOB6_1,?..." bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,,TIOA6_1,?..." endif textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,TIOB5_1,TIOB5_2" else bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,,TIOB5_2" endif textline " " bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,TIOA5_0,TIOA5_1,TIOA5_2" bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" "TIOA5_0,TIOA5_0,TIOA5_1,TIOA5_2" textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,TIOB4_2" else bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,,TIOB4_2" endif textline " " bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,TIOA4_2" line.long 0x8 "EPFR06,Extended Pin Function Setting Register 06" sif (cpuis("MB9BF???T")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" "INT15_0,INT15_0,INT15_1,INT15_2" bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" "INT14_0,INT14_0,INT14_1,INT14_2" bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" "INT13_0,INT13_0,INT13_1,INT13_2" textline " " bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" "INT12_0,INT12_0,INT12_1,INT12_2" bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" "INT11_0,INT11_0,INT11_1,INT11_2" bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" "INT10_0,INT10_0,INT10_1,INT10_2" textline " " bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" "INT09_0,INT09_0,INT09_1,INT09_2" bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" "INT08_0,INT08_0,INT08_1,INT08_2" bitfld.long 0x08 14.--15. " EINT07S ,External Interrupt Input 7 Select Bit" "INT07_0,INT07_0,INT07_1,INT07_2" textline " " bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" "INT06_0,INT06_0,INT06_1,INT06_2" bitfld.long 0x08 10.--11. " EINT05S ,External Interrupt Input 5 Select Bit" "INT05_0,INT05_0,INT05_1,INT05_2" bitfld.long 0x08 8.--9. " EINT04S ,External Interrupt Input 4 Select Bit" "INT04_0,INT04_0,INT04_1,INT04_2" textline " " bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" "INT03_0,INT03_0,INT03_1,INT03_2" bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,INT02_2" bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,INT01_2" textline " " bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,INT00_1,INT00_2" else bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,INT15_2" bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" ",,INT14_1,INT14_2" bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" ",,INT13_1,INT13_2" textline " " bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" ",,INT12_1,INT12_2" bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" ",,INT11_1,INT11_2" bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" ",,INT10_1,INT10_2" textline " " bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" "INT09_0,INT09_0,INT09_1,INT09_2" bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" "INT08_0,INT08_0,,INT08_2" bitfld.long 0x08 14.--15. " EINT07S ,External Interrupt Input 7 Select Bit" ",,INT07_1,INT07_2" textline " " bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" ",,INT06_1,INT06_2" bitfld.long 0x08 10.--11. " EINT05S ,External Interrupt Input 5 Select Bit" "INT05_0,INT05_0,INT05_1,?..." bitfld.long 0x08 8.--9. " EINT04S ,External Interrupt Input 4 Select Bit" ",,INT04_1,?..." textline " " bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" "INT03_0,INT03_0,INT03_1,?..." bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,INT02_2" bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,INT01_2" textline " " bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,INT00_1,INT00_2" endif line.long 0xC "EPFR07,Extended Pin Function Setting Register 07" bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "SCK3_0/Not produced,SCK3_0/SCK3_0,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "SOT3_0/Not produced,SOT3_0/SOT3_0,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" "SIN3_0,SIN3_0,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "SCK2_0/Not produced,SCK2_0/SCK2_0,SCK2_1/SCK2_1,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "SOT2_0/Not produced,SOT2_0/SOT2_0,SOT2_1/SOT2_1,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" "SIN2_0,SIN2_0,SIN2_1,SIN2_2" textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "SCK1_0/Not produced,SCK1_0/SCK1_0,SCK1_1/SCK1_1,SCK1_2/SCK1_2" bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "SOT1_0/Not produced,SOT1_0/SOT1_0,SOT1_1/SOT1_1,SOT1_2/SOT1_2" bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" "SIN1_0,SIN1_0,SIN1_1,SIN1_2" textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,SCK0_1/SCK0_1,SCK0_2/SCK0_2" bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,SOT0_1/SOT0_1,SOT0_2/SOT0_2" bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,SIN0_1,SIN0_2" else bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "SCK1_0/Not produced,SCK1_0/SCK1_0,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "SOT1_0/Not produced,SOT1_0/SOT1_0,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" "SIN1_0,SIN1_0,SIN1_1,?..." textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,SCK0_1/SCK0_1,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,SOT0_1/SOT0_1,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,SIN0_1,?..." endif line.long 0x10 "EPFR08,Extended Pin Function Setting Register 08" sif cpuis("MB9BF???T") bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "SCK7_0/Not produced,SCK7_0/SCK7_0,SCK7_1/SCK7_1,SCK7_2/SCK7_2" bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "SOT7_0/Not produced,SOT7_0/SOT7_0,SOT7_1/SOT7_1,SOT7_2/SOT7_2" bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" "SIN7_0,SIN7_0,SIN7_1,SIN7_2" textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,SCK6_1/SCK6_1,SCK6_2/SCK6_2" bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,SOT6_1/SOT6_1,SOT6_2/SOT6_2" bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,SIN6_1,SIN6_2" textline " " bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,SCK5_1/SCK5_1,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,SOT5_1/SOT5_1,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,SIN5_1,SIN5_2" else bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "SCK7_0/Not produced,SCK7_0/SCK7_0,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "SOT7_0/Not produced,SOT7_0/SOT7_0,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" "SIN7_0,SIN7_0,SIN7_1,?..." textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,?..." textline " " bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,,SIN5_2" endif textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,SCK4_1/SCK4_1,SCK4_2/SCK4_2" bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,SOT4_1/SOT4_1,SOT4_2/SOT4_2" bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,SIN4_1,SIN4_2" textline " " bitfld.long 0x10 2.--3. " CTS4S ,CTS4S Input Select Bit" "CTS4_0,CTS4_0,CTS4_1,CTS4_2" bitfld.long 0x10 0.--1. " RTS4E ,RTS4E Output Select Bit" "Not produced,RTS4_0,RTS4_1,RTS4_2" line.long 0x14 "EPFR09,Extended Pin Function Setting Register 09" sif (cpuis("MB9BF41?T")||cpuis("MB9BF51?T")) bitfld.long 0x14 30.--31. " CTX1E ,Select output for CAN TX1" "Not produced,TX1_0,TX1_1,TX1_2" bitfld.long 0x14 28.--29. " CRX1S ,Select input for CAN RX1" "RX1_0,RX1_0,RX1_1,RX1_2" textline " " bitfld.long 0x14 26.--27. " CTX0E ,Select output for CAN TX0" "Not produced,TX0_0,TX0_1,TX0_2" bitfld.long 0x14 24.--25. " CRX0S ,Select input for CAN RX0" "RX0_0,RX0_0,RX0_1,RX0_2" textline " " elif (cpuis("MB9BF41?S")||cpuis("MB9BF51?S")) bitfld.long 0x14 30.--31. " CTX1E ,Select output for CAN TX1" "Not produced,TX1_0,TX1_1,TX1_2" bitfld.long 0x14 28.--29. " CRX1S ,Select input for CAN RX1" "RX1_0,RX1_0,RX1_1,RX1_2" textline " " bitfld.long 0x14 26.--27. " CTX0E ,Select output for CAN TX0" "Not produced,TX0_0,Reserved,TX0_2" bitfld.long 0x14 24.--25. " CRX0S ,Select input for CAN RX0" "RX0_0,RX0_0,Reserved,RX0_2" textline " " endif sif (cpuis("MB9BF???T")) bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" else bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,,ADTG_7,ADTG_8,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,,ADTG_7,ADTG_8,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,,ADTG_7,ADTG_8,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif textline " " bitfld.long 0x14 10.--11. " QZIN1S ,Select input for QPRC ZIN1" "ZIN1_0,ZIN1_0,ZIN1_1,ZIN1_2" bitfld.long 0x14 8.--9. " QBIN1S ,Select input for QPRC BIN1" "BIN1_0,BIN1_0,BIN1_1,BIN1_2" bitfld.long 0x14 6.--7. " QAIN1S ,Select input for QPRC AIN1" "AIN1_0,AIN1_0,AIN1_1,AIN1_2" textline " " sif (cpuis("MB9BF???T")) bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" "BIN0_0,BIN0_0,BIN0_1,BIN0_2" bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" "AIN0_0,AIN0_0,AIN0_1,AIN0_2" else bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" ",,ZIN0_1,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" ",,BIN0_1,BIN0_2" bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" ",,AIN0_1,AIN0_2" endif line.long 0x18 "EPFR10,Extended Pin Function Setting Register 10" sif (cpuis("MB9BF???T")) bitfld.long 0x18 31. " UEA24E ,Selects output for external bus Adress24" "Not produced,Produced" bitfld.long 0x18 30. " UEA23E ,Selects output for external bus Adress23" "Not produced,Produced" bitfld.long 0x18 29. " UEA22E ,Selects output for external bus Adress22" "Not produced,Produced" textline " " bitfld.long 0x18 28. " UEA21E ,Selects output for external bus Adress21" "Not produced,Produced" bitfld.long 0x18 27. " UEA20E ,Selects output for external bus Adress20" "Not produced,Produced" bitfld.long 0x18 26. " UEA19E ,Selects output for external bus Adress19" "Not produced,Produced" textline " " endif bitfld.long 0x18 25. " UEA18E ,Selects output for external bus Adress18" "Not produced,Produced" bitfld.long 0x18 24. " UEA17E ,Selects output for external bus Adress17" "Not produced,Produced" bitfld.long 0x18 23. " UEA16E ,Selects output for external bus Adress16" "Not produced,Produced" textline " " bitfld.long 0x18 22. " UEA15E ,Selects output for external bus Adress15" "Not produced,Produced" bitfld.long 0x18 21. " UEA14E ,Selects output for external bus Adress14" "Not produced,Produced" bitfld.long 0x18 20. " UEA13E ,Selects output for external bus Adress13" "Not produced,Produced" textline " " bitfld.long 0x18 19. " UEA12E ,Selects output for external bus Adress12" "Not produced,Produced" bitfld.long 0x18 18. " UEA11E ,Selects output for external bus Adress11" "Not produced,Produced" bitfld.long 0x18 17. " UEA10E ,Selects output for external bus Adress10" "Not produced,Produced" textline " " bitfld.long 0x18 16. " UEA09E ,Selects output for external bus Adress09" "Not produced,Produced" bitfld.long 0x18 15. " UEA08E ,Selects output for external bus Adress08" "Not produced,Produced" bitfld.long 0x18 14. " UEA00E ,Selects output for external bus Adress00" "Not produced,Produced" textline " " bitfld.long 0x18 13. " UECS7E ,Selects output for external bus CS7" "Not produced,Produced" bitfld.long 0x18 12. " UECS6E ,Selects output for external bus CS6" "Not produced,Produced" bitfld.long 0x18 11. " UECS5E ,Selects output for external bus CS5" "Not produced,Produced" textline " " bitfld.long 0x18 10. " UECS4E ,Selects output for external bus CS4" "Not produced,Produced" bitfld.long 0x18 9. " UECS3E ,Selects output for external bus CS3" "Not produced,Produced" bitfld.long 0x18 8. " UECS2E ,Selects output for external bus CS2" "Not produced,Produced" textline " " bitfld.long 0x18 7. " UECS1E ,Selects output for external bus CS1" "Not produced,Produced" bitfld.long 0x18 6. " UEFLSE ,Selects output for external bus NAND-Flash control signal" "Not produced,Produced" bitfld.long 0x18 5. " UEOEXE ,Selects output for external bus OEX" "Not produced,Produced" textline " " bitfld.long 0x18 4. " UEDQME ,Selects output for external bus DQM" "Not produced,Produced" bitfld.long 0x18 3. " UEWEXE ,Selects output for external bus WEX" "Not produced,Produced" bitfld.long 0x18 2. " UECLKE ,Selects output for external bus clock" "Not produced,Produced" textline " " bitfld.long 0x18 1. " UEDTHB ,Selects input/output for external bus data" "Not produced,Produced" bitfld.long 0x18 0. " UEDEFB ,Selects input/output for external bus signal" "Not produced,Produced" line.long 0x1C "EPFR11,Extended Pin Function Setting Register 11" bitfld.long 0x1C 25. " UERLC ,Selects relocation of the external bus pin" "0,1" bitfld.long 0x1C 24. " UED15B ,Selects output for external bus data 15" "Not produced,Produced" bitfld.long 0x1C 23. " UED14B ,Selects output for external bus data 14" "Not produced,Produced" textline " " bitfld.long 0x1C 22. " UED13B ,Selects output for external bus data 13" "Not produced,Produced" bitfld.long 0x1C 21. " UED12B ,Selects output for external bus data 12" "Not produced,Produced" bitfld.long 0x1C 20. " UED11B ,Selects output for external bus data 11" "Not produced,Produced" textline " " bitfld.long 0x1C 19. " UED10B ,Selects output for external bus data 10" "Not produced,Produced" bitfld.long 0x1C 18. " UED09B ,Selects output for external bus data 09" "Not produced,Produced" bitfld.long 0x1C 17. " UED08B ,Selects output for external bus data 08" "Not produced,Produced" textline " " bitfld.long 0x1C 16. " UED07B ,Selects output for external bus data 07" "Not produced,Produced" bitfld.long 0x1C 15. " UED06B ,Selects output for external bus data 06" "Not produced,Produced" bitfld.long 0x1C 14. " UED05B ,Selects output for external bus data 05" "Not produced,Produced" textline " " bitfld.long 0x1C 13. " UED04B ,Selects output for external bus data 04" "Not produced,Produced" bitfld.long 0x1C 12. " UED03B ,Selects output for external bus data 03" "Not produced,Produced" bitfld.long 0x1C 11. " UED02B ,Selects output for external bus data 02" "Not produced,Produced" textline " " bitfld.long 0x1C 10. " UED01B ,Selects output for external bus data 01" "Not produced,Produced" bitfld.long 0x1C 9. " UED00B ,Selects output for external bus data 00" "Not produced,Produced" bitfld.long 0x1C 8. " UEA07E ,Selects output for external bus address07" "Not produced,Produced" textline " " bitfld.long 0x1C 7. " UEA06E ,Selects output for external bus address06" "Not produced,Produced" bitfld.long 0x1C 6. " UEA05E ,Selects output for external bus address05" "Not produced,Produced" bitfld.long 0x1C 5. " UEA04E ,Selects output for external bus address04" "Not produced,Produced" textline " " bitfld.long 0x1C 4. " UEA03E ,Selects output for external bus address03" "Not produced,Produced" bitfld.long 0x1C 3. " UEA02E ,Selects output for external bus address02" "Not produced,Produced" bitfld.long 0x1C 2. " UEA01E ,Selects output for external bus address01" "Not produced,Produced" textline " " bitfld.long 0x1C 1. " UECS0E ,Selects output for external bus address00" "Not produced,Produced" bitfld.long 0x1C 0. " UEALEE ,Selects output for external bus ALE signal" "Not produced,Produced" line.long 0x20 "EPFR12,Extended Pin Function Setting Register 12" sif (cpuis("MB9BF???T")) bitfld.long 0x20 28.--29. " TIOB11S ,Selects input for TIOB11" "TIOB11_0,TIOB11_0,TIOB11_1,TIOB11_2" bitfld.long 0x20 26.--27. " TIOA11E ,Selects output for TIOA11" "Not produced,TIOA11_0,TIOA11_1,TIOA11_2" bitfld.long 0x20 24.--25. " TIOA11S ,Selects input for TIOA11" "TIOA11_0,TIOA11_0,TIOA11_1,TIOA11_2" textline " " bitfld.long 0x20 20.--21. " TIOB10S ,Selects input for TIOB10" "TIOB10_0,TIOB10_0,TIOB10_1,TIOB10_2" bitfld.long 0x20 18.--19. " TIOA10E ,Selects output for TIOA10" "Not produced,TIOA10_0,TIOA10_1,TIOA10_2" textline " " bitfld.long 0x20 12.--13. " TIOB9S ,Selects input for TIOB9" "TIOB9_0,TIOB9_0,TIOB9_1,TIOB9_2" bitfld.long 0x20 10.--11. " TIOA9E ,Selects output for TIOA9" "Not produced,TIOA9_0,TIOA9_1,TIOA9_2" bitfld.long 0x20 8.--9. " TIOA9S ,Selects input for TIOA9" "TIOA9_0,TIOA9_0,TIOA9_1,TIOA9_2" textline " " bitfld.long 0x20 4.--5. " TIOB8S ,Selects input for TIOB8" "TIOB8_0,TIOB8_0,TIOB8_1,TIOB8_2" bitfld.long 0x20 2.--3. " TIOA8E ,Selects output for TIOA8" "Not produced,TIOA8_0,TIOA8_1,TIOA8_2" else bitfld.long 0x20 28.--29. " TIOB11S ,Selects input for TIOB11" ",,,TIOB11_2" bitfld.long 0x20 26.--27. " TIOA11E ,Selects output for TIOA11" "Not produced,TIOA11_0,,TIOA11_2" bitfld.long 0x20 24.--25. " TIOA11S ,Selects input for TIOA11" "TIOA11_0,TIOA11_0,,TIOA11_2" textline " " bitfld.long 0x20 20.--21. " TIOB10S ,Selects input for TIOB10" ",,,TIOB10_2" bitfld.long 0x20 18.--19. " TIOA10E ,Selects output for TIOA10" "Not produced,TIOA10_0,,TIOA10_2" textline " " bitfld.long 0x20 12.--13. " TIOB9S ,Selects input for TIOB9" ",,,TIOB9_2" bitfld.long 0x20 10.--11. " TIOA9E ,Selects output for TIOA9" "Not produced,TIOA9_0,,TIOA9_2" bitfld.long 0x20 8.--9. " TIOA9S ,Selects input for TIOA9" "TIOA9_0,TIOA9_0,,TIOA9_2" textline " " bitfld.long 0x20 4.--5. " TIOB8S ,Selects input for TIOB8" ",,,TIOB8_2" bitfld.long 0x20 2.--3. " TIOA8E ,Selects output for TIOA8" "Not produced,TIOA8_0,,TIOA8_2" endif line.long 0x24 "EPFR13,Extended Pin Function Setting Register 13" sif (cpuis("MB9BF???T")) bitfld.long 0x24 28.--29. " TIOB15S ,Selects input for TIOB15" "TIOB15_0,TIOB15_0,TIOB15_1,TIOB15_2" bitfld.long 0x24 26.--27. " TIOA15E ,Selects output for TIOA15" "Not produced,TIOA15_0,TIOA15_1,TIOA15_2" bitfld.long 0x24 24.--25. " TIOA15S ,Selects input for TIOA15" "TIOA15_0,TIOA15_0,TIOA15_1,TIOA15_2" textline " " bitfld.long 0x24 20.--21. " TIOB14S ,Selects input for TIOB14" "TIOB14_0,TIOB14_0,TIOB14_1,TIOB14_2" bitfld.long 0x24 18.--19. " TIOA14E ,Selects output for TIOA14" "Not produced,TIOA14_0,TIOA14_1,TIOA14_2" textline " " bitfld.long 0x24 12.--13. " TIOB13S ,Selects input for TIOB13" "TIOB13_0,TIOB13_0,TIOB13_1,TIOB13_2" bitfld.long 0x24 10.--11. " TIOA13E ,Selects output for TIOA13" "Not produced,TIOA13_0,TIOA13_1,TIOA13_2" bitfld.long 0x24 8.--9. " TIOA13S ,Selects input for TIOA13" "TIOA13_0,TIOA13_0,TIOA13_1,TIOA13_2" textline " " bitfld.long 0x24 4.--5. " TIOB12S ,Selects input for TIOB12" "TIOB12_0,TIOB12_0,TIOB12_1,TIOB12_2" bitfld.long 0x24 2.--3. " TIOA12E ,Selects output for TIOA12" "Not produced,TIOA12_0,TIOA12_1,TIOA12_2" else bitfld.long 0x24 28.--29. " TIOB15S ,Selects input for TIOB15" "TIOB15_0,TIOB15_0,,TIOB15_2" bitfld.long 0x24 26.--27. " TIOA15E ,Selects output for TIOA15" "Not produced,TIOA15_0,,TIOA15_2" bitfld.long 0x24 24.--25. " TIOA15S ,Selects input for TIOA15" "TIOA15_0,TIOA15_0,,TIOA15_2" textline " " bitfld.long 0x24 20.--21. " TIOB14S ,Selects input for TIOB14" "TIOB14_0,TIOB14_0,,TIOB14_2" bitfld.long 0x24 18.--19. " TIOA14E ,Selects output for TIOA14" "Not produced,TIOA14_0,,TIOA14_2" textline " " bitfld.long 0x24 12.--13. " TIOB13S ,Selects input for TIOB13" ",,TIOB13_1,TIOB13_2" bitfld.long 0x24 10.--11. " TIOA13E ,Selects output for TIOA13" "Not produced,TIOA13_0,TIOA13_1,TIOA13_2" bitfld.long 0x24 8.--9. " TIOA13S ,Selects input for TIOA13" "TIOA13_0,TIOA13_0,TIOA13_1,TIOA13_2" textline " " bitfld.long 0x24 4.--5. " TIOB12S ,Selects input for TIOB12" ",,,TIOB12_2" bitfld.long 0x24 2.--3. " TIOA12E ,Selects output for TIOA12" "Not produced,TIOA12_0,,TIOA12_2" endif line.long 0x28 "EPFR14,Extended Pin Function Setting Register 14" sif (cpuis("MB9BF61??")) bitfld.long 0x28 28.--29. " E_SPLC ,Selects input interruption in standby of the Ethernet input pin" "Disabled,MII ch.0,RMII ch.0,RMII ch.1" bitfld.long 0x28 27. " E_PSE ,Selects output for PPS0_PPS1" "Not output,Output" bitfld.long 0x28 26. " E_CKE ,Selects output for E_COUT" "Not output,Output" textline " " bitfld.long 0x28 25. " E_MD1B ,Selects I/O for E_MDO1" "Not output,Output" bitfld.long 0x28 24. " E_MD0B ,Selects I/O for E_MDC0" "Not output,Output" textline " " bitfld.long 0x28 22. " E_MC0E ,Selects output for E_MDC0" "Not output,Output" textline " " bitfld.long 0x28 21. " E_TE1E ,Selects output for E_TXER0_TXEN1" "Not output,Output" bitfld.long 0x28 20. " E_TE0E ,Selects output for E_TXEN0" "Not output,Output" textline " " bitfld.long 0x28 19. " E_TD1E ,Selects output for E_TX02_TX10 E_TX03_TX11" "Not output,Output" bitfld.long 0x28 18. " E_TD0E ,Selects output for E_TX00 E_TX01" "Not output,Output" textline " " elif (cpuis("MB9BF21??")) bitfld.long 0x28 28.--29. " E_SPLC ,Selects input interruption in standby of the Ethernet input pin" "Disabled,MII ch.0,RMII ch.0,?..." bitfld.long 0x28 27. " E_PSE ,Selects output for PPS" "Not output,Output" bitfld.long 0x28 26. " E_CKE ,Selects output for E_COUT" "Not output,Output" textline " " bitfld.long 0x28 25. " E_MD1B ,Selects I/O for E_MDO" "Not output,Output" bitfld.long 0x28 24. " E_MD0B ,Selects I/O for E_MDC" "Not output,Output" textline " " bitfld.long 0x28 22. " E_MC0E ,Selects output for E_MDC0" "Not output,Output" textline " " bitfld.long 0x28 21. " E_TE1E ,Selects output for E_TXER" "Not output,Output" bitfld.long 0x28 20. " E_TE0E ,Selects output for E_TXEN" "Not output,Output" textline " " bitfld.long 0x28 19. " E_TD1E ,Selects output for E_TX02 E_TX03" "Not output,Output" bitfld.long 0x28 18. " E_TD0E ,Selects output for E_TX00 E_TX01" "Not output,Output" textline " " endif sif (cpuis("MB9BF???T")) bitfld.long 0x28 4.--5. " QZIN2S ,Selects input for QDU-ch.2 as ZIN" "ZIN2_0,ZIN2_0,ZIN2_1,ZIN2_2" bitfld.long 0x28 2.--3. " QBIN2S ,Selects input for QDU-ch.2 as BIN" "BIN2_0,BIN2_0,BIN2_1,BIN2_2" bitfld.long 0x28 0.--1. " QAIN2S ,Selects input for QDU-ch.2 as AIN" "AIN2_0,AIN2_0,AIN2_1,AIN2_2" else bitfld.long 0x28 4.--5. " QZIN2S ,Selects input for QDU-ch.2 as ZIN" "ZIN2_0,ZIN2_0,ZIN2_1,?..." bitfld.long 0x28 2.--3. " QBIN2S ,Selects input for QDU-ch.2 as BIN" "BIN2_0,BIN2_0,?..." bitfld.long 0x28 0.--1. " QAIN2S ,Selects input for QDU-ch.2 as AIN" "AIN2_0,AIN2_0,?..." endif line.long 0x2C "EPFR15,Extended Pin Function Setting Register 15" sif (cpuis("MB9BF???T")) bitfld.long 0x2C 30.--31. " EINT31S ,Selects input for EINT31" "INT31_0,INT31_0,INT31_1,?..." bitfld.long 0x2C 28.--29. " EINT30S ,Selects input for EINT30" "INT30_0,INT30_0,INT30_1,?..." bitfld.long 0x2C 26.--27. " EINT29S ,Selects input for EINT29" "INT29_0,INT29_0,INT29_1,?..." textline " " bitfld.long 0x2C 24.--25. " EINT28S ,Selects input for EINT28" "INT28_0,INT28_0,INT28_1,?..." bitfld.long 0x2C 22.--23. " EINT27S ,Selects input for EINT27" "INT27_0,INT27_0,INT27_1,?..." bitfld.long 0x2C 20.--21. " EINT26S ,Selects input for EINT26" "INT26_0,INT26_0,INT26_1,?..." textline " " bitfld.long 0x2C 18.--19. " EINT25S ,Selects input for EINT25" "INT25_0,INT25_0,INT25_1,?..." bitfld.long 0x2C 16.--17. " EINT24S ,Selects input for EINT24" "INT24_0,INT24_0,INT24_1,?..." bitfld.long 0x2C 14.--15. " EINT23S ,Selects input for EINT23" "INT23_0,INT23_0,INT23_1,?..." textline " " bitfld.long 0x2C 12.--13. " EINT22S ,Selects input for EINT22" "INT22_0,INT22_0,INT22_1,?..." bitfld.long 0x2C 10.--11. " EINT21S ,Selects input for EINT21" "INT21_0,INT21_0,INT21_1,?..." bitfld.long 0x2C 8.--9. " EINT20S ,Selects input for EINT20" "INT20_0,INT20_0,INT20_1,?..." textline " " bitfld.long 0x2C 6.--7. " EINT19S ,Selects input for EINT19" "INT19_0,INT19_0,INT19_1,?..." bitfld.long 0x2C 4.--5. " EINT18S ,Selects input for EINT18" "INT18_0,INT18_0,INT18_1,?..." bitfld.long 0x2C 2.--3. " EINT17S ,Selects input for EINT17" "INT17_0,INT17_0,INT17_1,?..." textline " " bitfld.long 0x2C 0.--1. " EINT16S ,Selects input for EINT16" "INT16_0,INT16_0,INT16_1,?..." else bitfld.long 0x2C 30.--31. " EINT31S ,Selects input for EINT31" ",,INT31_1,?..." bitfld.long 0x2C 28.--29. " EINT30S ,Selects input for EINT30" ",,INT30_1,?..." bitfld.long 0x2C 26.--27. " EINT29S ,Selects input for EINT29" ",,INT29_1,?..." textline " " bitfld.long 0x2C 24.--25. " EINT28S ,Selects input for EINT28" ",,INT28_1,?..." bitfld.long 0x2C 22.--23. " EINT27S ,Selects input for EINT27" ",,INT27_1,?..." bitfld.long 0x2C 20.--21. " EINT26S ,Selects input for EINT26" ",,INT26_1,?..." textline " " bitfld.long 0x2C 18.--19. " EINT25S ,Selects input for EINT25" ",,INT25_1,?..." bitfld.long 0x2C 16.--17. " EINT24S ,Selects input for EINT24" ",,INT24_1,?..." bitfld.long 0x2C 14.--15. " EINT23S ,Selects input for EINT23" ",,INT23_1,?..." textline " " bitfld.long 0x2C 12.--13. " EINT22S ,Selects input for EINT22" ",,INT22_1,?..." bitfld.long 0x2C 10.--11. " EINT21S ,Selects input for EINT21" ",,INT21_1,?..." bitfld.long 0x2C 8.--9. " EINT20S ,Selects input for EINT20" ",,INT20_1,?..." textline " " bitfld.long 0x2C 6.--7. " EINT19S ,Selects input for EINT19" ",,INT19_1,?..." bitfld.long 0x2C 4.--5. " EINT18S ,Selects input for EINT18" ",,INT18_1,?..." bitfld.long 0x2C 2.--3. " EINT17S ,Selects input for EINT17" ",,INT17_1,?..." textline " " bitfld.long 0x2C 0.--1. " EINT16S ,Selects input for EINT16" ",,INT16_1,?..." endif tree.end tree "Special Port Setting Register" group.long 0x580++0x3 line.long 0x0 "SPSR,Special Port Setting Register" sif (cpuis("MB9BF21??")||cpuis("MB9BF31??")||cpuis("MB9BF51??")||cpuis("MB9BF61??")) bitfld.long 0x00 5. " USB1C ,USB (ch.1) Pin Setting Register" "Not used,Used" bitfld.long 0x00 4. " USB0C ,USB (ch.0) Pin Setting Register" "Not used,Used" textline " " endif bitfld.long 0x00 2. " MAINXC ,Main Clock (Oscillation) Pin Setting Register" "Not used,Used" bitfld.long 0x00 0. " SUBXC ,Sub Clock (Oscillation) Pin Setting Register" "Not used,Used" tree.end tree "Port Pseudo Open Drain Setting Registers" group.long 0x700++0x3 line.long 0x00 "PZR0,Port Pseudo Open Drain Setting Register 0" bitfld.long 0x00 9. " P09 ,Pin 09" "High,Hi-Z" bitfld.long 0x00 8. " P08 ,Pin 08" "High,Hi-Z" bitfld.long 0x00 7. " P07 ,Pin 07" "High,Hi-Z" bitfld.long 0x00 6. " P06 ,Pin 06" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P05 ,Pin 05" "High,Hi-Z" bitfld.long 0x00 4. " P04 ,Pin 04" "High,Hi-Z" bitfld.long 0x00 3. " P03 ,Pin 03" "High,Hi-Z" bitfld.long 0x00 2. " P02 ,Pin 02" "High,Hi-Z" textline " " bitfld.long 0x00 1. " P01 ,Pin 01" "High,Hi-Z" bitfld.long 0x00 0. " P00 ,Pin 00" "High,Hi-Z" group.long 0x704++0x3 line.long 0x00 "PZR1,Port Pseudo Open Drain Setting Register 1" bitfld.long 0x00 15. " P1F ,Pin 1F" "High,Hi-Z" bitfld.long 0x00 14. " P1E ,Pin 1E" "High,Hi-Z" bitfld.long 0x00 13. " P1D ,Pin 1D" "High,Hi-Z" bitfld.long 0x00 12. " P1C ,Pin 1C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P1B ,Pin 1B" "High,Hi-Z" bitfld.long 0x00 10. " P1A ,Pin 1A" "High,Hi-Z" bitfld.long 0x00 9. " P19 ,Pin 19" "High,Hi-Z" bitfld.long 0x00 8. " P18 ,Pin 18" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P17 ,Pin 17" "High,Hi-Z" bitfld.long 0x00 6. " P16 ,Pin 16" "High,Hi-Z" bitfld.long 0x00 5. " P15 ,Pin 15" "High,Hi-Z" bitfld.long 0x00 4. " P14 ,Pin 14" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P13 ,Pin 13" "High,Hi-Z" bitfld.long 0x00 2. " P12 ,Pin 12" "High,Hi-Z" bitfld.long 0x00 1. " P11 ,Pin 11" "High,Hi-Z" bitfld.long 0x00 0. " P10 ,Pin 10" "High,Hi-Z" group.long 0x708++0x3 line.long 0x00 "PZR2,Port Pseudo Open Drain Setting Register 2" bitfld.long 0x00 9. " P29 ,Pin 29" "High,Hi-Z" bitfld.long 0x00 8. " P28 ,Pin 28" "High,Hi-Z" bitfld.long 0x00 7. " P27 ,Pin 27" "High,Hi-Z" bitfld.long 0x00 6. " P26 ,Pin 26" "High,Hi-Z" textline " " bitfld.long 0x00 5. " P25 ,Pin 25" "High,Hi-Z" bitfld.long 0x00 4. " P24 ,Pin 24" "High,Hi-Z" bitfld.long 0x00 3. " P23 ,Pin 23" "High,Hi-Z" bitfld.long 0x00 2. " P22 ,Pin 22" "High,Hi-Z" textline " " bitfld.long 0x00 1. " P21 ,Pin 21" "High,Hi-Z" bitfld.long 0x00 0. " P20 ,Pin 20" "High,Hi-Z" group.long 0x70C++0x3 line.long 0x00 "PZR3,Port Pseudo Open Drain Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "High,Hi-Z" bitfld.long 0x00 14. " P3E ,Pin 3E" "High,Hi-Z" bitfld.long 0x00 13. " P3D ,Pin 3D" "High,Hi-Z" bitfld.long 0x00 12. " P3C ,Pin 3C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P3B ,Pin 3B" "High,Hi-Z" bitfld.long 0x00 10. " P3A ,Pin 3A" "High,Hi-Z" bitfld.long 0x00 9. " P39 ,Pin 39" "High,Hi-Z" bitfld.long 0x00 8. " P38 ,Pin 38" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P37 ,Pin 37" "High,Hi-Z" bitfld.long 0x00 6. " P36 ,Pin 36" "High,Hi-Z" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x00 5. " P35 ,Pin 35" "High,Hi-Z" bitfld.long 0x00 4. " P34 ,Pin 34" "High,Hi-Z" bitfld.long 0x00 3. " P33 ,Pin 33" "High,Hi-Z" bitfld.long 0x00 2. " P32 ,Pin 32" "High,Hi-Z" textline " " bitfld.long 0x00 1. " P31 ,Pin 31" "High,Hi-Z" bitfld.long 0x00 0. " P30 ,Pin 30" "High,Hi-Z" endif group.long 0x710++0x3 line.long 0x00 "PZR4,Port Pseudo Open Drain Setting Register 4" bitfld.long 0x00 14. " P4E ,Pin 4E" "High,Hi-Z" bitfld.long 0x00 13. " P4D ,Pin 4D" "High,Hi-Z" bitfld.long 0x00 12. " P4C ,Pin 4C" "High,Hi-Z" bitfld.long 0x00 11. " P4B ,Pin 4B" "High,Hi-Z" textline " " bitfld.long 0x00 10. " P4A ,Pin 4A" "High,Hi-Z" bitfld.long 0x00 9. " P49 ,Pin 49" "High,Hi-Z" bitfld.long 0x00 8. " P48 ,Pin 48" "High,Hi-Z" bitfld.long 0x00 7. " P47 ,Pin 47" "High,Hi-Z" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "High,Hi-Z" bitfld.long 0x00 5. " P45 ,Pin 45" "High,Hi-Z" bitfld.long 0x00 4. " P44 ,Pin 44" "High,Hi-Z" bitfld.long 0x00 3. " P43 ,Pin 43" "High,Hi-Z" textline " " bitfld.long 0x00 2. " P42 ,Pin 42" "High,Hi-Z" bitfld.long 0x00 1. " P41 ,Pin 41" "High,Hi-Z" bitfld.long 0x00 0. " P40 ,Pin 40" "High,Hi-Z" group.long 0x714++0x3 line.long 0x00 "PZR5,Port Pseudo Open Drain Setting Register 5" sif (cpuis("MB9BF???T")) bitfld.long 0x00 13. " P5D ,Pin 5D" "High,Hi-Z" bitfld.long 0x00 12. " P5C ,Pin 5C" "High,Hi-Z" textline " " endif bitfld.long 0x00 11. " P5B ,Pin 5B" "High,Hi-Z" bitfld.long 0x00 10. " P5A ,Pin 5A" "High,Hi-Z" bitfld.long 0x00 9. " P59 ,Pin 59" "High,Hi-Z" bitfld.long 0x00 8. " P58 ,Pin 58" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P57 ,Pin 57" "High,Hi-Z" bitfld.long 0x00 6. " P56 ,Pin 56" "High,Hi-Z" bitfld.long 0x00 5. " P55 ,Pin 55" "High,Hi-Z" bitfld.long 0x00 4. " P54 ,Pin 54" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P53 ,Pin 53" "High,Hi-Z" bitfld.long 0x00 2. " P52 ,Pin 52" "High,Hi-Z" bitfld.long 0x00 1. " P51 ,Pin 51" "High,Hi-Z" bitfld.long 0x00 0. " P50 ,Pin 50" "High,Hi-Z" group.long 0x718++0x3 line.long 0x00 "PZR6,Port Pseudo Open Drain Setting Register 6" bitfld.long 0x00 2. " P62 ,Pin 62" "High,Hi-Z" bitfld.long 0x00 1. " P61 ,Pin 61" "High,Hi-Z" bitfld.long 0x00 0. " P60 ,Pin 60" "High,Hi-Z" group.long 0x71C++0x3 line.long 0x00 "PZR7,Port Pseudo Open Drain Setting Register 7" sif (cpuis("MB9BF???T")) bitfld.long 0x00 15. " P7F ,Pin 7F" "High,Hi-Z" bitfld.long 0x00 14. " P7E ,Pin 7E" "High,Hi-Z" bitfld.long 0x00 13. " P7D ,Pin 7D" "High,Hi-Z" bitfld.long 0x00 12. " P7C ,Pin 7C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P7B ,Pin 7B" "High,Hi-Z" textline " " endif bitfld.long 0x00 10. " P7A ,Pin 7A" "High,Hi-Z" bitfld.long 0x00 9. " P79 ,Pin 79" "High,Hi-Z" bitfld.long 0x00 8. " P78 ,Pin 78" "High,Hi-Z" bitfld.long 0x00 7. " P77 ,Pin 77" "High,Hi-Z" textline " " bitfld.long 0x00 6. " P76 ,Pin 76" "High,Hi-Z" bitfld.long 0x00 5. " P75 ,Pin 75" "High,Hi-Z" bitfld.long 0x00 4. " P74 ,Pin 74" "High,Hi-Z" bitfld.long 0x00 3. " P73 ,Pin 73" "High,Hi-Z" textline " " bitfld.long 0x00 2. " P72 ,Pin 72" "High,Hi-Z" bitfld.long 0x00 1. " P71 ,Pin 71" "High,Hi-Z" bitfld.long 0x00 0. " P70 ,Pin 70" "High,Hi-Z" group.long 0x720++0x3 line.long 0x00 "PZR8,Port Pseudo Open Drain Setting Register 8" bitfld.long 0x00 3. " P83 ,Pin 83" "High,Hi-Z" bitfld.long 0x00 2. " P82 ,Pin 82" "High,Hi-Z" bitfld.long 0x00 1. " P81 ,Pin 81" "High,Hi-Z" bitfld.long 0x00 0. " P80 ,Pin 80" "High,Hi-Z" sif (cpuis("MB9BF???T")) group.long 0x724++0x3 line.long 0x00 "PZR9,Port Pseudo Open Drain Setting Register 9" bitfld.long 0x00 15. " P9F ,Pin 9F" "High,Hi-Z" bitfld.long 0x00 14. " P9E ,Pin 9E" "High,Hi-Z" bitfld.long 0x00 13. " P9D ,Pin 9D" "High,Hi-Z" bitfld.long 0x00 12. " P9C ,Pin 9C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P9B ,Pin 9B" "High,Hi-Z" bitfld.long 0x00 10. " P9A ,Pin 9A" "High,Hi-Z" bitfld.long 0x00 9. " P99 ,Pin 99" "High,Hi-Z" bitfld.long 0x00 8. " P98 ,Pin 98" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P97 ,Pin 97" "High,Hi-Z" bitfld.long 0x00 6. " P96 ,Pin 96" "High,Hi-Z" bitfld.long 0x00 5. " P95 ,Pin 95" "High,Hi-Z" bitfld.long 0x00 4. " P94 ,Pin 94" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P93 ,Pin 93" "High,Hi-Z" bitfld.long 0x00 2. " P92 ,Pin 92" "High,Hi-Z" bitfld.long 0x00 1. " P91 ,Pin 91" "High,Hi-Z" bitfld.long 0x00 0. " P90 ,Pin 90" "High,Hi-Z" endif group.long 0x728++0x3 line.long 0x00 "PZRA,Port Pseudo Open Drain Setting Register A" bitfld.long 0x00 5. " PA5 ,Pin A5" "High,Hi-Z" bitfld.long 0x00 4. " PA4 ,Pin A4" "High,Hi-Z" textline " " bitfld.long 0x00 3. " PA3 ,Pin A3" "High,Hi-Z" bitfld.long 0x00 2. " PA2 ,Pin A2" "High,Hi-Z" bitfld.long 0x00 1. " PA1 ,Pin A1" "High,Hi-Z" bitfld.long 0x00 0. " PA0 ,Pin A0" "High,Hi-Z" sif (cpuis("MB9BF???T")) group.long 0x72C++0x3 line.long 0x00 "PZRB,Port Pseudo Open Drain Setting Register B" bitfld.long 0x00 7. " PB7 ,Pin B7" "High,Hi-Z" bitfld.long 0x00 6. " PB6 ,Pin B6" "High,Hi-Z" bitfld.long 0x00 5. " PB5 ,Pin B5" "High,Hi-Z" bitfld.long 0x00 4. " PB4 ,Pin B4" "High,Hi-Z" textline " " bitfld.long 0x00 3. " PB3 ,Pin B3" "High,Hi-Z" bitfld.long 0x00 2. " PB2 ,Pin B2" "High,Hi-Z" bitfld.long 0x00 1. " PB1 ,Pin B1" "High,Hi-Z" bitfld.long 0x00 0. " PB0 ,Pin B0" "High,Hi-Z" endif group.long 0x730++0x3 line.long 0x00 "PZRC,Port Pseudo Open Drain Setting Register C" bitfld.long 0x00 15. " PCF ,Pin CF" "High,Hi-Z" bitfld.long 0x00 14. " PCE ,Pin CE" "High,Hi-Z" bitfld.long 0x00 13. " PCD ,Pin CD" "High,Hi-Z" bitfld.long 0x00 12. " PCC ,Pin CC" "High,Hi-Z" textline " " bitfld.long 0x00 11. " PCB ,Pin CB" "High,Hi-Z" bitfld.long 0x00 10. " PCA ,Pin CA" "High,Hi-Z" bitfld.long 0x00 9. " PC9 ,Pin C9" "High,Hi-Z" bitfld.long 0x00 8. " PC8 ,Pin C8" "High,Hi-Z" textline " " bitfld.long 0x00 7. " PC7 ,Pin C7" "High,Hi-Z" bitfld.long 0x00 6. " PC6 ,Pin C6" "High,Hi-Z" bitfld.long 0x00 5. " PC5 ,Pin C5" "High,Hi-Z" bitfld.long 0x00 4. " PC4 ,Pin C4" "High,Hi-Z" textline " " bitfld.long 0x00 3. " PC3 ,Pin C3" "High,Hi-Z" bitfld.long 0x00 2. " PC2 ,Pin C2" "High,Hi-Z" bitfld.long 0x00 1. " PC1 ,Pin C1" "High,Hi-Z" bitfld.long 0x00 0. " PC0 ,Pin C0" "High,Hi-Z" group.long 0x734++0x3 line.long 0x00 "PZRD,Port Pseudo Open Drain Setting Register D" bitfld.long 0x00 3. " PD3 ,Pin D3" "High,Hi-Z" bitfld.long 0x00 2. " PD2 ,Pin D2" "High,Hi-Z" bitfld.long 0x00 1. " PD1 ,Pin D1" "High,Hi-Z" bitfld.long 0x00 0. " PD0 ,Pin D0" "High,Hi-Z" group.long 0x738++0x3 line.long 0x00 "PZRE,Port Pseudo Open Drain Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "High,Hi-Z" bitfld.long 0x00 2. " PE2 ,Pin E2" "High,Hi-Z" bitfld.long 0x00 1. " PE1 ,Pin E1" "High,Hi-Z" bitfld.long 0x00 0. " PE0 ,Pin E0" "High,Hi-Z" group.long 0x73C++0x3 line.long 0x00 "PZRF,Port Pseudo Open Drain Setting Register F" bitfld.long 0x00 6. " PF6 ,Pin F6" "High,Hi-Z" bitfld.long 0x00 5. " PF5 ,Pin F5" "High,Hi-Z" sif (cpuis("MB9BF???T")) textline " " bitfld.long 0x00 4. " PF4 ,Pin F4" "High,Hi-Z" bitfld.long 0x00 3. " PF3 ,Pin F3" "High,Hi-Z" bitfld.long 0x00 2. " PF2 ,Pin F2" "High,Hi-Z" bitfld.long 0x00 1. " PF1 ,Pin F1" "High,Hi-Z" textline " " bitfld.long 0x00 0. " PF0 ,Pin F0" "High,Hi-Z" endif tree.end width 12. elif (cpuis("MB9BF???N")||cpuis("MB9BF???R")) width 8. tree "Port Function Setting Registers" group.long 0x0++0x3 line.long 0x00 "PFR0,Port Function Setting Register 0" bitfld.long 0x00 15. " P0F ,Pin 0F" "GPIO,Input/Output" bitfld.long 0x00 14. " P0E ,Pin 0E" "GPIO,Input/Output" bitfld.long 0x00 13. " P0D ,Pin 0D" "GPIO,Input/Output" bitfld.long 0x00 12. " P0C ,Pin 0C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P0B ,Pin 0B" "GPIO,Input/Output" bitfld.long 0x00 10. " P0A ,Pin 0A" "GPIO,Input/Output" bitfld.long 0x00 9. " P09 ,Pin 09" "GPIO,Input/Output" bitfld.long 0x00 8. " P08 ,Pin 08" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P07 ,Pin 07" "GPIO,Input/Output" bitfld.long 0x00 6. " P06 ,Pin 06" "GPIO,Input/Output" bitfld.long 0x00 5. " P05 ,Pin 05" "GPIO,Input/Output" bitfld.long 0x00 4. " P04 ,Pin 04" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P03 ,Pin 03" "GPIO,Input/Output" bitfld.long 0x00 2. " P02 ,Pin 02" "GPIO,Input/Output" bitfld.long 0x00 1. " P01 ,Pin 01" "GPIO,Input/Output" bitfld.long 0x00 0. " P00 ,Pin 00" "GPIO,Input/Output" group.long 0x4++0x3 line.long 0x00 "PFR1,Port Function Setting Register 1" bitfld.long 0x00 15. " P1F ,Pin 1F" "GPIO,Input/Output" bitfld.long 0x00 14. " P1E ,Pin 1E" "GPIO,Input/Output" bitfld.long 0x00 13. " P1D ,Pin 1D" "GPIO,Input/Output" bitfld.long 0x00 12. " P1C ,Pin 1C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P1B ,Pin 1B" "GPIO,Input/Output" bitfld.long 0x00 10. " P1A ,Pin 1A" "GPIO,Input/Output" bitfld.long 0x00 9. " P19 ,Pin 19" "GPIO,Input/Output" bitfld.long 0x00 8. " P18 ,Pin 18" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P17 ,Pin 17" "GPIO,Input/Output" bitfld.long 0x00 6. " P16 ,Pin 16" "GPIO,Input/Output" bitfld.long 0x00 5. " P15 ,Pin 15" "GPIO,Input/Output" bitfld.long 0x00 4. " P14 ,Pin 14" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P13 ,Pin 13" "GPIO,Input/Output" bitfld.long 0x00 2. " P12 ,Pin 12" "GPIO,Input/Output" bitfld.long 0x00 1. " P11 ,Pin 11" "GPIO,Input/Output" bitfld.long 0x00 0. " P10 ,Pin 10" "GPIO,Input/Output" group.long 0x8++0x3 line.long 0x00 "PFR2,Port Function Setting Register 2" sif (cpuis("MB9BF???R")) bitfld.long 0x00 8. " P28 ,Pin 28" "GPIO,Input/Output" bitfld.long 0x00 7. " P27 ,Pin 27" "GPIO,Input/Output" bitfld.long 0x00 6. " P26 ,Pin 26" "GPIO,Input/Output" bitfld.long 0x00 5. " P25 ,Pin 25" "GPIO,Input/Output" textline " " bitfld.long 0x00 4. " P24 ,Pin 24" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 3. " P23 ,Pin 23" "GPIO,Input/Output" bitfld.long 0x00 2. " P22 ,Pin 22" "GPIO,Input/Output" bitfld.long 0x00 1. " P21 ,Pin 21" "GPIO,Input/Output" bitfld.long 0x00 0. " P20 ,Pin 20" "GPIO,Input/Output" group.long 0xC++0x3 line.long 0x00 "PFR3,Port Function Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "GPIO,Input/Output" bitfld.long 0x00 14. " P3E ,Pin 3E" "GPIO,Input/Output" bitfld.long 0x00 13. " P3D ,Pin 3D" "GPIO,Input/Output" bitfld.long 0x00 12. " P3C ,Pin 3C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P3B ,Pin 3B" "GPIO,Input/Output" bitfld.long 0x00 10. " P3A ,Pin 3A" "GPIO,Input/Output" bitfld.long 0x00 9. " P39 ,Pin 39" "GPIO,Input/Output" bitfld.long 0x00 8. " P38 ,Pin 38" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P37 ,Pin 37" "GPIO,Input/Output" bitfld.long 0x00 6. " P36 ,Pin 36" "GPIO,Input/Output" bitfld.long 0x00 5. " P35 ,Pin 35" "GPIO,Input/Output" bitfld.long 0x00 4. " P34 ,Pin 34" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P33 ,Pin 33" "GPIO,Input/Output" bitfld.long 0x00 2. " P32 ,Pin 32" "GPIO,Input/Output" bitfld.long 0x00 1. " P31 ,Pin 31" "GPIO,Input/Output" bitfld.long 0x00 0. " P30 ,Pin 30" "GPIO,Input/Output" group.long 0x10++0x3 line.long 0x00 "PFR4,Port Function Setting Register 4" bitfld.long 0x00 14. " P4E ,Pin 4E" "GPIO,Input/Output" bitfld.long 0x00 13. " P4D ,Pin 4D" "GPIO,Input/Output" bitfld.long 0x00 12. " P4C ,Pin 4C" "GPIO,Input/Output" bitfld.long 0x00 11. " P4B ,Pin 4B" "GPIO,Input/Output" textline " " bitfld.long 0x00 10. " P4A ,Pin 4A" "GPIO,Input/Output" bitfld.long 0x00 9. " P49 ,Pin 49" "GPIO,Input/Output" bitfld.long 0x00 8. " P48 ,Pin 48" "GPIO,Input/Output" bitfld.long 0x00 7. " P47 ,Pin 47" "GPIO,Input/Output" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "GPIO,Input/Output" bitfld.long 0x00 5. " P45 ,Pin 45" "GPIO,Input/Output" bitfld.long 0x00 4. " P44 ,Pin 44" "GPIO,Input/Output" bitfld.long 0x00 3. " P43 ,Pin 43" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P42 ,Pin 42" "GPIO,Input/Output" bitfld.long 0x00 1. " P41 ,Pin 41" "GPIO,Input/Output" bitfld.long 0x00 0. " P40 ,Pin 40" "GPIO,Input/Output" group.long 0x14++0x3 line.long 0x00 "PFR5,Port Function Setting Register 5" sif (cpuis("MB9BF???R")) bitfld.long 0x00 11. " P5B ,Pin 5B" "GPIO,Input/Output" bitfld.long 0x00 10. " P5A ,Pin 5A" "GPIO,Input/Output" bitfld.long 0x00 9. " P59 ,Pin 59" "GPIO,Input/Output" bitfld.long 0x00 8. " P58 ,Pin 58" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P57 ,Pin 57" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 6. " P56 ,Pin 56" "GPIO,Input/Output" bitfld.long 0x00 5. " P55 ,Pin 55" "GPIO,Input/Output" bitfld.long 0x00 4. " P54 ,Pin 54" "GPIO,Input/Output" bitfld.long 0x00 3. " P53 ,Pin 53" "GPIO,Input/Output" textline " " bitfld.long 0x00 2. " P52 ,Pin 52" "GPIO,Input/Output" bitfld.long 0x00 1. " P51 ,Pin 51" "GPIO,Input/Output" bitfld.long 0x00 0. " P50 ,Pin 50" "GPIO,Input/Output" group.long 0x18++0x3 line.long 0x00 "PFR6,Port Function Setting Register 6" sif (cpuis("MB9BF???R")) bitfld.long 0x00 8. " P68 ,Pin 68" "GPIO,Input/Output" bitfld.long 0x00 7. " P67 ,Pin 67" "GPIO,Input/Output" bitfld.long 0x00 6. " P66 ,Pin 66" "GPIO,Input/Output" bitfld.long 0x00 5. " P65 ,Pin 65" "GPIO,Input/Output" textline " " bitfld.long 0x00 4. " P64 ,Pin 64" "GPIO,Input/Output" textline " " endif bitfld.long 0x00 3. " P63 ,Pin 63" "GPIO,Input/Output" bitfld.long 0x00 2. " P62 ,Pin 62" "GPIO,Input/Output" bitfld.long 0x00 1. " P61 ,Pin 61" "GPIO,Input/Output" bitfld.long 0x00 0. " P60 ,Pin 60" "GPIO,Input/Output" sif (cpuis("MB9BF???R")) group.long 0x1C++0x3 line.long 0x00 "PFR7,Port Function Setting Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "GPIO,Input/Output" bitfld.long 0x00 3. " P73 ,Pin 73" "GPIO,Input/Output" bitfld.long 0x00 2. " P72 ,Pin 72" "GPIO,Input/Output" bitfld.long 0x00 1. " P71 ,Pin 71" "GPIO,Input/Output" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "GPIO,Input/Output" endif group.long 0x20++0x3 line.long 0x00 "PFR8,Port Function Setting Register 8" bitfld.long 0x00 1. " P81 ,Pin 81" "GPIO,Input/Output" bitfld.long 0x00 0. " P80 ,Pin 80" "GPIO,Input/Output" group.long 0x38++0x3 line.long 0x00 "PFRE,Port Function Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "GPIO,Input/Output" bitfld.long 0x00 2. " PE2 ,Pin E2" "GPIO,Input/Output" bitfld.long 0x00 0. " PE0 ,Pin E0" "GPIO,Input/Output" tree.end tree "Pull-up Setting Registers" group.long 0x100++0x3 line.long 0x0 "PCR0,Pull-up Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Disconnected,Connected" bitfld.long 0x0 14. " P0E ,Pin 0E" "Disconnected,Connected" bitfld.long 0x0 13. " P0D ,Pin 0D" "Disconnected,Connected" bitfld.long 0x0 12. " P0C ,Pin 0C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Disconnected,Connected" bitfld.long 0x0 10. " P0A ,Pin 0A" "Disconnected,Connected" bitfld.long 0x0 9. " P09 ,Pin 09" "Disconnected,Connected" bitfld.long 0x0 8. " P08 ,Pin 08" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Disconnected,Connected" bitfld.long 0x0 6. " P06 ,Pin 06" "Disconnected,Connected" bitfld.long 0x0 5. " P05 ,Pin 05" "Disconnected,Connected" bitfld.long 0x0 4. " P04 ,Pin 04" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Disconnected,Connected" bitfld.long 0x0 2. " P02 ,Pin 02" "Disconnected,Connected" bitfld.long 0x0 1. " P01 ,Pin 01" "Disconnected,Connected" bitfld.long 0x0 0. " P00 ,Pin 00" "Disconnected,Connected" group.long 0x104++0x3 line.long 0x0 "PCR1,Pull-up Setting Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Disconnected,Connected" bitfld.long 0x0 14. " P1E ,Pin 1E" "Disconnected,Connected" bitfld.long 0x0 13. " P1D ,Pin 1D" "Disconnected,Connected" bitfld.long 0x0 12. " P1C ,Pin 1C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Disconnected,Connected" bitfld.long 0x0 10. " P1A ,Pin 1A" "Disconnected,Connected" bitfld.long 0x0 9. " P19 ,Pin 19" "Disconnected,Connected" bitfld.long 0x0 8. " P18 ,Pin 18" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Disconnected,Connected" bitfld.long 0x0 6. " P16 ,Pin 16" "Disconnected,Connected" bitfld.long 0x0 5. " P15 ,Pin 15" "Disconnected,Connected" bitfld.long 0x0 4. " P14 ,Pin 14" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Disconnected,Connected" bitfld.long 0x0 2. " P12 ,Pin 12" "Disconnected,Connected" bitfld.long 0x0 1. " P11 ,Pin 11" "Disconnected,Connected" bitfld.long 0x0 0. " P10 ,Pin 10" "Disconnected,Connected" group.long 0x108++0x3 line.long 0x0 "PCR2,Pull-up Setting Register 2" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P28 ,Pin 28" "Disconnected,Connected" bitfld.long 0x0 7. " P27 ,Pin 27" "Disconnected,Connected" bitfld.long 0x0 6. " P26 ,Pin 26" "Disconnected,Connected" bitfld.long 0x0 5. " P25 ,Pin 25" "Disconnected,Connected" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Disconnected,Connected" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Disconnected,Connected" bitfld.long 0x0 2. " P22 ,Pin 22" "Disconnected,Connected" bitfld.long 0x0 1. " P21 ,Pin 21" "Disconnected,Connected" bitfld.long 0x0 0. " P20 ,Pin 20" "Disconnected,Connected" group.long 0x10C++0x3 line.long 0x0 "PCR3,Pull-up Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Disconnected,Connected" bitfld.long 0x0 14. " P3E ,Pin 3E" "Disconnected,Connected" bitfld.long 0x0 13. " P3D ,Pin 3D" "Disconnected,Connected" bitfld.long 0x0 12. " P3C ,Pin 3C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Disconnected,Connected" bitfld.long 0x0 10. " P3A ,Pin 3A" "Disconnected,Connected" bitfld.long 0x0 9. " P39 ,Pin 39" "Disconnected,Connected" bitfld.long 0x0 8. " P38 ,Pin 38" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Disconnected,Connected" bitfld.long 0x0 6. " P36 ,Pin 36" "Disconnected,Connected" bitfld.long 0x0 5. " P35 ,Pin 35" "Disconnected,Connected" bitfld.long 0x0 4. " P34 ,Pin 34" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Disconnected,Connected" bitfld.long 0x0 2. " P32 ,Pin 32" "Disconnected,Connected" bitfld.long 0x0 1. " P31 ,Pin 31" "Disconnected,Connected" bitfld.long 0x0 0. " P30 ,Pin 30" "Disconnected,Connected" group.long 0x110++0x3 line.long 0x0 "PCR4,Pull-up Setting Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Disconnected,Connected" bitfld.long 0x0 13. " P4D ,Pin 4D" "Disconnected,Connected" bitfld.long 0x0 12. " P4C ,Pin 4C" "Disconnected,Connected" bitfld.long 0x0 11. " P4B ,Pin 4B" "Disconnected,Connected" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Disconnected,Connected" bitfld.long 0x0 9. " P49 ,Pin 49" "Disconnected,Connected" bitfld.long 0x0 8. " P48 ,Pin 48" "Disconnected,Connected" bitfld.long 0x0 7. " P47 ,Pin 47" "Disconnected,Connected" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Disconnected,Connected" bitfld.long 0x0 5. " P45 ,Pin 45" "Disconnected,Connected" bitfld.long 0x0 4. " P44 ,Pin 44" "Disconnected,Connected" bitfld.long 0x0 3. " P43 ,Pin 43" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Disconnected,Connected" bitfld.long 0x0 1. " P41 ,Pin 41" "Disconnected,Connected" bitfld.long 0x0 0. " P40 ,Pin 40" "Disconnected,Connected" group.long 0x114++0x3 line.long 0x0 "PCR5,Pull-up Setting Register 5" sif (cpuis("MB9BF???R")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Disconnected,Connected" bitfld.long 0x0 10. " P5A ,Pin 5A" "Disconnected,Connected" bitfld.long 0x0 9. " P59 ,Pin 59" "Disconnected,Connected" bitfld.long 0x0 8. " P58 ,Pin 58" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Disconnected,Connected" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Disconnected,Connected" bitfld.long 0x0 5. " P55 ,Pin 55" "Disconnected,Connected" bitfld.long 0x0 4. " P54 ,Pin 54" "Disconnected,Connected" bitfld.long 0x0 3. " P53 ,Pin 53" "Disconnected,Connected" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Disconnected,Connected" bitfld.long 0x0 1. " P51 ,Pin 51" "Disconnected,Connected" bitfld.long 0x0 0. " P50 ,Pin 50" "Disconnected,Connected" group.long 0x118++0x3 line.long 0x0 "PCR6,Pull-up Setting Register 6" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P68 ,Pin 68" "Disconnected,Connected" bitfld.long 0x0 7. " P67 ,Pin 67" "Disconnected,Connected" bitfld.long 0x0 6. " P66 ,Pin 66" "Disconnected,Connected" bitfld.long 0x0 5. " P65 ,Pin 65" "Disconnected,Connected" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Disconnected,Connected" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Disconnected,Connected" bitfld.long 0x0 2. " P62 ,Pin 62" "Disconnected,Connected" bitfld.long 0x0 1. " P61 ,Pin 61" "Disconnected,Connected" bitfld.long 0x0 0. " P60 ,Pin 60" "Disconnected,Connected" sif (cpuis("MB9BF???R")) group.long 0x11C++0x3 line.long 0x0 "PCR7,Pull-up Setting Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Disconnected,Connected" bitfld.long 0x0 3. " P73 ,Pin 73" "Disconnected,Connected" bitfld.long 0x0 2. " P72 ,Pin 72" "Disconnected,Connected" bitfld.long 0x0 1. " P71 ,Pin 71" "Disconnected,Connected" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Disconnected,Connected" endif group.long 0x138++0x3 line.long 0x0 "PCRE,Pull-up Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Disconnected,Connected" bitfld.long 0x0 2. " PE2 ,Pin E2" "Disconnected,Connected" bitfld.long 0x0 0. " PE0 ,Pin E0" "Disconnected,Connected" tree.end tree "Port input/output Direction Setting Registers" group.long 0x200++0x3 line.long 0x0 "DDR0,Port input/output Direction Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Input,Output" bitfld.long 0x0 14. " P0E ,Pin 0E" "Input,Output" bitfld.long 0x0 13. " P0D ,Pin 0D" "Input,Output" bitfld.long 0x0 12. " P0C ,Pin 0C" "Input,Output" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Input,Output" bitfld.long 0x0 10. " P0A ,Pin 0A" "Input,Output" bitfld.long 0x0 9. " P09 ,Pin 09" "Input,Output" bitfld.long 0x0 8. " P08 ,Pin 08" "Input,Output" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Input,Output" bitfld.long 0x0 6. " P06 ,Pin 06" "Input,Output" bitfld.long 0x0 5. " P05 ,Pin 05" "Input,Output" bitfld.long 0x0 4. " P04 ,Pin 04" "Input,Output" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Input,Output" bitfld.long 0x0 2. " P02 ,Pin 02" "Input,Output" bitfld.long 0x0 1. " P01 ,Pin 01" "Input,Output" bitfld.long 0x0 0. " P00 ,Pin 00" "Input,Output" group.long 0x204++0x3 line.long 0x0 "DDR1,Port input/output Direction Setting Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Input,Output" bitfld.long 0x0 14. " P1E ,Pin 1E" "Input,Output" bitfld.long 0x0 13. " P1D ,Pin 1D" "Input,Output" bitfld.long 0x0 12. " P1C ,Pin 1C" "Input,Output" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Input,Output" bitfld.long 0x0 10. " P1A ,Pin 1A" "Input,Output" bitfld.long 0x0 9. " P19 ,Pin 19" "Input,Output" bitfld.long 0x0 8. " P18 ,Pin 18" "Input,Output" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Input,Output" bitfld.long 0x0 6. " P16 ,Pin 16" "Input,Output" bitfld.long 0x0 5. " P15 ,Pin 15" "Input,Output" bitfld.long 0x0 4. " P14 ,Pin 14" "Input,Output" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Input,Output" bitfld.long 0x0 2. " P12 ,Pin 12" "Input,Output" bitfld.long 0x0 1. " P11 ,Pin 11" "Input,Output" bitfld.long 0x0 0. " P10 ,Pin 10" "Input,Output" group.long 0x208++0x3 line.long 0x0 "DDR2,Port input/output Direction Setting Register 2" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P28 ,Pin 28" "Input,Output" bitfld.long 0x0 7. " P27 ,Pin 27" "Input,Output" bitfld.long 0x0 6. " P26 ,Pin 26" "Input,Output" bitfld.long 0x0 5. " P25 ,Pin 25" "Input,Output" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Input,Output" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Input,Output" bitfld.long 0x0 2. " P22 ,Pin 22" "Input,Output" bitfld.long 0x0 1. " P21 ,Pin 21" "Input,Output" bitfld.long 0x0 0. " P20 ,Pin 20" "Input,Output" group.long 0x20C++0x3 line.long 0x0 "DDR3,Port input/output Direction Setting Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Input,Output" bitfld.long 0x0 14. " P3E ,Pin 3E" "Input,Output" bitfld.long 0x0 13. " P3D ,Pin 3D" "Input,Output" bitfld.long 0x0 12. " P3C ,Pin 3C" "Input,Output" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Input,Output" bitfld.long 0x0 10. " P3A ,Pin 3A" "Input,Output" bitfld.long 0x0 9. " P39 ,Pin 39" "Input,Output" bitfld.long 0x0 8. " P38 ,Pin 38" "Input,Output" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Input,Output" bitfld.long 0x0 6. " P36 ,Pin 36" "Input,Output" bitfld.long 0x0 5. " P35 ,Pin 35" "Input,Output" bitfld.long 0x0 4. " P34 ,Pin 34" "Input,Output" textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Input,Output" bitfld.long 0x0 2. " P32 ,Pin 32" "Input,Output" bitfld.long 0x0 1. " P31 ,Pin 31" "Input,Output" bitfld.long 0x0 0. " P30 ,Pin 30" "Input,Output" group.long 0x210++0x3 line.long 0x0 "DDR4,Port input/output Direction Setting Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Input,Output" bitfld.long 0x0 13. " P4D ,Pin 4D" "Input,Output" bitfld.long 0x0 12. " P4C ,Pin 4C" "Input,Output" bitfld.long 0x0 11. " P4B ,Pin 4B" "Input,Output" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Input,Output" bitfld.long 0x0 9. " P49 ,Pin 49" "Input,Output" bitfld.long 0x0 8. " P48 ,Pin 48" "Input,Output" bitfld.long 0x0 7. " P47 ,Pin 47" "Input,Output" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Input,Output" bitfld.long 0x0 5. " P45 ,Pin 45" "Input,Output" bitfld.long 0x0 4. " P44 ,Pin 44" "Input,Output" bitfld.long 0x0 3. " P43 ,Pin 43" "Input,Output" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Input,Output" bitfld.long 0x0 1. " P41 ,Pin 41" "Input,Output" bitfld.long 0x0 0. " P40 ,Pin 40" "Input,Output" group.long 0x214++0x3 line.long 0x0 "DDR5,Port input/output Direction Setting Register 5" sif (cpuis("MB9BF???R")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Input,Output" bitfld.long 0x0 10. " P5A ,Pin 5A" "Input,Output" bitfld.long 0x0 9. " P59 ,Pin 59" "Input,Output" bitfld.long 0x0 8. " P58 ,Pin 58" "Input,Output" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Input,Output" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Input,Output" bitfld.long 0x0 5. " P55 ,Pin 55" "Input,Output" bitfld.long 0x0 4. " P54 ,Pin 54" "Input,Output" bitfld.long 0x0 3. " P53 ,Pin 53" "Input,Output" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Input,Output" bitfld.long 0x0 1. " P51 ,Pin 51" "Input,Output" bitfld.long 0x0 0. " P50 ,Pin 50" "Input,Output" group.long 0x218++0x3 line.long 0x0 "DDR6,Port input/output Direction Setting Register 6" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P68 ,Pin 68" "Input,Output" bitfld.long 0x0 7. " P67 ,Pin 67" "Input,Output" bitfld.long 0x0 6. " P66 ,Pin 66" "Input,Output" bitfld.long 0x0 5. " P65 ,Pin 65" "Input,Output" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Input,Output" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Input,Output" bitfld.long 0x0 2. " P62 ,Pin 62" "Input,Output" bitfld.long 0x0 1. " P61 ,Pin 61" "Input,Output" bitfld.long 0x0 0. " P60 ,Pin 60" "Input,Output" sif (cpuis("MB9BF???R")) group.long 0x21C++0x3 line.long 0x0 "DDR7,Port input/output Direction Setting Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Input,Output" bitfld.long 0x0 3. " P73 ,Pin 73" "Input,Output" bitfld.long 0x0 2. " P72 ,Pin 72" "Input,Output" bitfld.long 0x0 1. " P71 ,Pin 71" "Input,Output" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Input,Output" endif group.long 0x220++0x3 line.long 0x0 "DDR8,Port input/output Direction Setting Register 8" bitfld.long 0x0 1. " P81 ,Pin 81" "Input,Output" bitfld.long 0x0 0. " P80 ,Pin 80" "Input,Output" group.long 0x238++0x3 line.long 0x0 "DDRE,Port input/output Direction Setting Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Input,Output" bitfld.long 0x0 2. " PE2 ,Pin E2" "Input,Output" bitfld.long 0x0 0. " PE0 ,Pin E0" "Input,Output" tree.end tree "Port Input Data Registers" rgroup.long 0x300++0x3 line.long 0x0 "PDIR0,Port Input Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" bitfld.long 0x0 14. " P0E ,Pin 0E" "Low,High" bitfld.long 0x0 13. " P0D ,Pin 0D" "Low,High" bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" rgroup.long 0x304++0x3 line.long 0x0 "PDIR1,Port Input Data Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x0 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x0 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x0 12. " P1C ,Pin 1C" "Low,High" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x0 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x0 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" rgroup.long 0x308++0x3 line.long 0x0 "PDIR2,Port Input Data Register 2" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x0 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x0 6. " P26 ,Pin 26" "Low,High" bitfld.long 0x0 5. " P25 ,Pin 25" "Low,High" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Low,High" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x0 0. " P20 ,Pin 20" "Low,High" rgroup.long 0x30C++0x3 line.long 0x0 "PDIR3,Port Input Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" bitfld.long 0x0 8. " P38 ,Pin 38" "Low,High" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Low,High" bitfld.long 0x0 6. " P36 ,Pin 36" "Low,High" bitfld.long 0x0 5. " P35 ,Pin 35" "Low,High" bitfld.long 0x0 4. " P34 ,Pin 34" "Low,High" textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" rgroup.long 0x310++0x3 line.long 0x0 "PDIR4,Port Input Data Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x0 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x0 4. " P44 ,Pin 44" "Low,High" bitfld.long 0x0 3. " P43 ,Pin 43" "Low,High" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x0 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x0 0. " P40 ,Pin 40" "Low,High" rgroup.long 0x314++0x3 line.long 0x0 "PDIR5,Port Input Data Register 5" sif (cpuis("MB9BF???R")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x0 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x0 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x0 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Low,High" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x0 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x0 4. " P54 ,Pin 54" "Low,High" bitfld.long 0x0 3. " P53 ,Pin 53" "Low,High" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" rgroup.long 0x318++0x3 line.long 0x0 "PDIR6,Port Input Data Register 6" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P68 ,Pin 68" "Low,High" bitfld.long 0x0 7. " P67 ,Pin 67" "Low,High" bitfld.long 0x0 6. " P66 ,Pin 66" "Low,High" bitfld.long 0x0 5. " P65 ,Pin 65" "Low,High" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Low,High" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Low,High" bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" sif (cpuis("MB9BF???R")) rgroup.long 0x31C++0x3 line.long 0x0 "PDIR7,Port Input Data Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x0 3. " P73 ,Pin 73" "Low,High" bitfld.long 0x0 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x0 1. " P71 ,Pin 71" "Low,High" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Low,High" endif rgroup.long 0x320++0x3 line.long 0x0 "PDIR8,Port Input Data Register 8" bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" rgroup.long 0x338++0x3 line.long 0x0 "PDIRE,Port Input Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" tree.end tree "Port Output Data Registers" group.long 0x400++0x3 line.long 0x0 "PDOR0,Port Output Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" bitfld.long 0x0 14. " P0E ,Pin 0E" "Low,High" bitfld.long 0x0 13. " P0D ,Pin 0D" "Low,High" bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" group.long 0x404++0x3 line.long 0x0 "PDOR1,Port Output Data Register 1" bitfld.long 0x0 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x0 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x0 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x0 12. " P1C ,Pin 1C" "Low,High" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x0 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x0 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x0 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x0 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x0 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x0 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x0 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x0 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x0 0. " P10 ,Pin 10" "Low,High" group.long 0x408++0x3 line.long 0x0 "PDOR2,Port Output Data Register 2" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x0 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x0 6. " P26 ,Pin 26" "Low,High" bitfld.long 0x0 5. " P25 ,Pin 25" "Low,High" textline " " bitfld.long 0x0 4. " P24 ,Pin 24" "Low,High" textline " " endif bitfld.long 0x0 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x0 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x0 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x0 0. " P20 ,Pin 20" "Low,High" group.long 0x40C++0x3 line.long 0x0 "PDOR3,Port Output Data Register 3" bitfld.long 0x0 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0x0 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0x0 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0x0 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0x0 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0x0 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0x0 9. " P39 ,Pin 39" "Low,High" bitfld.long 0x0 8. " P38 ,Pin 38" "Low,High" textline " " bitfld.long 0x0 7. " P37 ,Pin 37" "Low,High" bitfld.long 0x0 6. " P36 ,Pin 36" "Low,High" bitfld.long 0x0 5. " P35 ,Pin 35" "Low,High" bitfld.long 0x0 4. " P34 ,Pin 34" "Low,High" textline " " bitfld.long 0x0 3. " P33 ,Pin 33" "Low,High" bitfld.long 0x0 2. " P32 ,Pin 32" "Low,High" bitfld.long 0x0 1. " P31 ,Pin 31" "Low,High" bitfld.long 0x0 0. " P30 ,Pin 30" "Low,High" group.long 0x410++0x3 line.long 0x0 "PDOR4,Port Output Data Register 4" bitfld.long 0x0 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x0 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x0 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x0 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x0 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x0 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x0 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x0 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x0 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x0 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x0 4. " P44 ,Pin 44" "Low,High" bitfld.long 0x0 3. " P43 ,Pin 43" "Low,High" textline " " bitfld.long 0x0 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x0 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x0 0. " P40 ,Pin 40" "Low,High" group.long 0x414++0x3 line.long 0x0 "PDOR5,Port Output Data Register 5" sif (cpuis("MB9BF???R")) bitfld.long 0x0 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x0 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x0 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x0 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x0 7. " P57 ,Pin 57" "Low,High" textline " " endif bitfld.long 0x0 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x0 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x0 4. " P54 ,Pin 54" "Low,High" bitfld.long 0x0 3. " P53 ,Pin 53" "Low,High" textline " " bitfld.long 0x0 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x0 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x0 0. " P50 ,Pin 50" "Low,High" group.long 0x418++0x3 line.long 0x0 "PDOR6,Port Output Data Register 6" sif (cpuis("MB9BF???R")) bitfld.long 0x0 8. " P68 ,Pin 68" "Low,High" bitfld.long 0x0 7. " P67 ,Pin 67" "Low,High" bitfld.long 0x0 6. " P66 ,Pin 66" "Low,High" bitfld.long 0x0 5. " P65 ,Pin 65" "Low,High" textline " " bitfld.long 0x0 4. " P64 ,Pin 64" "Low,High" textline " " endif bitfld.long 0x0 3. " P63 ,Pin 63" "Low,High" bitfld.long 0x0 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x0 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x0 0. " P60 ,Pin 60" "Low,High" sif (cpuis("MB9BF???R")) group.long 0x41C++0x3 line.long 0x0 "PDOR7,Port Output Data Register 7" bitfld.long 0x0 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x0 3. " P73 ,Pin 73" "Low,High" bitfld.long 0x0 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x0 1. " P71 ,Pin 71" "Low,High" textline " " bitfld.long 0x0 0. " P70 ,Pin 70" "Low,High" endif group.long 0x420++0x3 line.long 0x0 "PDOR8,Port Output Data Register 8" bitfld.long 0x0 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x0 0. " P80 ,Pin 80" "Low,High" group.long 0x438++0x3 line.long 0x0 "PDORE,Port Output Data Register E" bitfld.long 0x0 3. " PE3 ,Pin E3" "Low,High" bitfld.long 0x0 2. " PE2 ,Pin E2" "Low,High" bitfld.long 0x0 0. " PE0 ,Pin E0" "Low,High" tree.end tree "Analog Input Setting Register" group.long 0x500++0x3 line.long 0x0 "ADE,Analog Input Setting Register" bitfld.long 0x0 15. " P1F ,Pin 1F" "Digital I/O,Analog IN" bitfld.long 0x0 14. " P1E ,Pin 1E" "Digital I/O,Analog IN" bitfld.long 0x0 13. " P1D ,Pin 1D" "Digital I/O,Analog IN" bitfld.long 0x0 12. " P1C ,Pin 1C" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Digital I/O,Analog IN" bitfld.long 0x0 10. " P1A ,Pin 1A" "Digital I/O,Analog IN" bitfld.long 0x0 9. " P19 ,Pin 19" "Digital I/O,Analog IN" bitfld.long 0x0 8. " P18 ,Pin 18" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Digital I/O,Analog IN" bitfld.long 0x0 6. " P16 ,Pin 16" "Digital I/O,Analog IN" bitfld.long 0x0 5. " P15 ,Pin 15" "Digital I/O,Analog IN" bitfld.long 0x0 4. " P14 ,Pin 14" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Digital I/O,Analog IN" bitfld.long 0x0 2. " P12 ,Pin 12" "Digital I/O,Analog IN" bitfld.long 0x0 1. " P11 ,Pin 11" "Digital I/O,Analog IN" bitfld.long 0x0 0. " P10 ,Pin 10" "Digital I/O,Analog IN" tree.end tree "Extended Pin Function Setting Register" group.long 0x600++0xF line.long 0x0 "EPFR00,Extended Pin Function Setting Register 00" bitfld.long 0x00 25. " TRC1E ,Select whether to use two pins of TRACED2 and TRACED3" "Not used,Used" bitfld.long 0x00 24. " TRC0E ,Select whether to use three pins of TRACECLK, TRACED0, and TRACED1" "Not used,Used" bitfld.long 0x00 17. " JTAGEN1S ,Select whether to use two pins of TRSTX and TDI" "Not used,Used" bitfld.long 0x00 16. " JTAGEN0S ,Select whether to use three pins of TCK, TMS, and TDO" "Not used,Used" textline " " sif (cpuis("MB9BF31?R")||cpuis("MB9BF51?R")) bitfld.long 0x00 9. " USBP0E ,Selects whether to produce output D+ resistor control signal (HCONTX) for USBch.0" "Not produced,Produced" textline " " endif bitfld.long 0x00 6.--7. " SUBOUTE ,Selects sub clock divide output" "Not executed,SUBOUT_0,SUBOUT_1,SUBOUT_2" bitfld.long 0x00 4.--5. " RTCCOE ,Selects a RTC clock output" "Not executed,RTCCOE_0,RTCCOE_1,RTCCOE_2" bitfld.long 0x00 1.--2. " CROUTE ,Selects internal high-speed CR oscillation output" "Not produced,CROUT_0,CROUT_1,?..." bitfld.long 0x00 0. " NMIS ,Select whether to use the NMIX pin" "Not used,Used" line.long 0x4 "EPFR01,Extended Pin Function Setting Register 01" bitfld.long 0x04 29.--31. " IC03S ,IC03 Input Select Bit" "IC03_0,IC03_0,IC03_1,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x04 26.--28. " IS02S ,IC02 Input Select Bit" "IC02_0,IC02_0,IC02_1,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x04 23.--25. " IC01S ,IC01 Input Select Bit" "IC01_0,IC01_0,IC01_1,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x04 20.--22. " IC00S ,IC00 Input Select Bit" "IC00_0,IC00_0,IC00_1,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " bitfld.long 0x04 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "FRCK0_0,FRCK0_0,FRCK0_1,FRCK0_2" bitfld.long 0x04 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,DTTIX0_1,?..." bitfld.long 0x04 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" textline " " sif (cpuis("MB9BF???R")) bitfld.long 0x04 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,RTO05_1,?..." bitfld.long 0x04 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,RTO04_1,?..." bitfld.long 0x04 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,RTO03_1,?..." bitfld.long 0x04 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,RTO02_1,?..." textline " " bitfld.long 0x04 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,RTO01_1,?..." bitfld.long 0x04 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,RTO00_1,?..." else bitfld.long 0x04 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,?..." bitfld.long 0x04 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,?..." bitfld.long 0x04 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,?..." bitfld.long 0x04 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,?..." textline " " bitfld.long 0x04 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,?..." bitfld.long 0x04 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,?..." endif line.long 0x8 "EPFR02,Extended Pin Function Setting Register 02" bitfld.long 0x08 29.--31. " IC13S ,IC13 Input Select Bit" "IC13_0,IC13_0,IC13_1,,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x08 26.--28. " IS12S ,IC12 Input Select Bit" "IC12_0,IC12_0,IC12_1,,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x08 23.--25. " IC11S ,IC11 Input Select Bit" "IC11_0,IC11_0,IC11_1,,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x08 20.--22. " IC10S ,IC10 Input Select Bit" "IC10_0,IC10_0,IC10_1,,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " bitfld.long 0x08 18.--19. " FRCK1S ,FRCK1 Input Select Bit" "FRCK1_0,FRCK1_0,FRCK1_1,?..." bitfld.long 0x08 16.--17. " DTTI1S ,DTTIX1 Input Select Bit" "DTTIX1_0,DTTIX1_0,DTTIX1_1,?..." bitfld.long 0x08 12. " DTTI1C ,DTTIX1 Function Select Bit" "Not switched,Switched" textline " " bitfld.long 0x08 10.--11. " RTO15E ,RTO15E Output Select Bit" "Not produced,RTO15_0,RTO15_1,?..." bitfld.long 0x08 8.--9. " RTO14E ,RTO14E Output Select Bit" "Not produced,RTO14_0,RTO14_1,?..." bitfld.long 0x08 6.--7. " RTO13E ,RTO13E Output Select Bit" "Not produced,RTO13_0,RTO13_1,?..." bitfld.long 0x08 4.--5. " RTO012E ,RTO12E Output Select Bit" "Not produced,RTO12_0,RTO12_1,?..." textline " " bitfld.long 0x08 2.--3. " RTO11E ,RTO11E Output Select Bit" "Not produced,RTO11_0,RTO11_1,?..." bitfld.long 0x08 0.--1. " RTO10E ,RTO10E Output Select Bit" "Not produced,RTO10_0,RTO10_1,?..." line.long 0xC "EPFR03,Extended Pin Function Setting Register 03" bitfld.long 0x0C 29.--31. " IC23S ,IC23 Input Select Bit" "IC23_0,IC23_0,IC23_1,,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x0C 26.--28. " IS22S ,IC22 Input Select Bit" "IC22_0,IC22_0,IC22_1,,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x0C 23.--25. " IC21S ,IC21 Input Select Bit" "IC21_0,IC21_0,IC21_1,,MFSch.1LSYN,MFSch.5LSYN,?..." bitfld.long 0x0C 20.--22. " IC20S ,IC20 Input Select Bit" "IC20_0,IC20_0,IC20_1,,MFSch.0LSYN,MFSch.4LSYN,?..." textline " " bitfld.long 0x0C 18.--19. " FRCK2S ,FRCK2 Input Select Bit" "FRCK2_0,FRCK2_0,FRCK2_1,?..." bitfld.long 0x0C 16.--17. " DTTI2S ,DTTIX2 Input Select Bit" "DTTIX2_0,DTTIX2_0,DTTIX2_1,?..." bitfld.long 0x0C 12. " DTTI2C ,DTTIX2 Function Select Bit" "Not switched,Switched" textline " " sif (cpuis("MB9BF???R")) bitfld.long 0x0C 10.--11. " RTO25E ,RTO25E Output Select Bit" "Not produced,RTO25_0,RTO25_1,?..." bitfld.long 0x0C 8.--9. " RTO24E ,RTO24E Output Select Bit" "Not produced,RTO24_0,RTO24_1,?..." bitfld.long 0x0C 6.--7. " RTO23E ,RTO23E Output Select Bit" "Not produced,RTO23_0,RTO23_1,?..." bitfld.long 0x0C 4.--5. " RTO022E ,RTO22E Output Select Bit" "Not produced,RTO22_0,RTO22_1,?..." textline " " bitfld.long 0x0C 2.--3. " RTO21E ,RTO21E Output Select Bit" "Not produced,RTO21_0,RTO21_1,?..." bitfld.long 0x0C 0.--1. " RTO20E ,RTO20E Output Select Bit" "Not produced,RTO20_0,RTO20_1,?..." else bitfld.long 0x0C 10.--11. " RTO25E ,RTO25E Output Select Bit" "Not produced,,RTO25_1,?..." bitfld.long 0x0C 8.--9. " RTO24E ,RTO24E Output Select Bit" "Not produced,,RTO24_1,?..." bitfld.long 0x0C 6.--7. " RTO23E ,RTO23E Output Select Bit" "Not produced,,RTO23_1,?..." bitfld.long 0x0C 4.--5. " RTO022E ,RTO22E Output Select Bit" "Not produced,,RTO22_1,?..." textline " " bitfld.long 0x0C 2.--3. " RTO21E ,RTO21E Output Select Bit" "Not produced,,RTO21_1,?..." bitfld.long 0x0C 0.--1. " RTO20E ,RTO20E Output Select Bit" "Not produced,,RTO20_1,?..." endif group.long 0x610++0x1F line.long 0x0 "EPFR04,Extended Pin Function Setting Register 04" bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,TIOB3_1,TIOB3_2" bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,TIOA3_0,TIOA3_1,TIOA3_2" bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" "TIOA3_0,TIOA3_0,TIOA3_1,TIOA3_2" textline " " bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2" bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,TIOA2_0,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" "TIOA2_0,TIOA2_0,TIOA2_1,TIOA2_2" textline " " bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,TIOB1_1,TIOB1_2" bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,TIOA1_0,TIOA1_1,TIOA1_2" bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" "TIOA1_0,TIOA1_0,TIOA1_1,TIOA1_2" textline " " bitfld.long 0x00 4.--6. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2,?..." bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,TIOA0_0,TIOA0_1,TIOA0_2" line.long 0x4 "EPFR05,Extended Pin Function Setting Register 05" sif (cpuis("MB9BF???R")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" "TIOB7_0,TIOB7_0,TIOB7_1,TIOB7_2" bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,TIOA7_0,TIOA7_1,TIOA7_2" bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" "TIOA7_0,TIOA7_0,TIOA7_1,TIOA7_2" textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" "TIOB6_0,TIOB6_0,TIOB6_1,TIOB6_2" bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,TIOA6_0,TIOA6_1,TIOA6_2" else bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,?..." bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,?..." bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,?..." textline " " bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" ",,TIOB6_1,?..." bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,,TIOA6_1,?..." endif textline " " bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,TIOB5_1,TIOB5_2" bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,TIOA5_0,TIOA5_1,TIOA5_2" bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" "TIOA5_0,TIOA5_0,TIOA5_1,TIOA5_2" textline " " sif (cpuis("MB9BF???R")) bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,TIOB4_2" bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,TIOA4_2" else bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,?..." bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,?..." endif line.long 0x8 "EPFR06,Extended Pin Function Setting Register 06" sif (cpuis("MB9BF???R")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,INT15_2" bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" ",,INT14_1,INT14_2" bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" ",,INT13_1,INT13_2" bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" ",,INT12_1,INT12_2" textline " " bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" ",,INT11_1,INT11_2" bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" ",,INT10_1,INT10_2" bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" ",,INT09_1,INT09_2" else bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" ",,INT15_1,?..." bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" ",,INT14_1,?..." bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" ",,INT13_1,?..." bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" ",,INT12_1,?..." textline " " bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" ",,INT11_1,?..." bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" ",,INT10_1,?..." bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" ",,INT09_1,?..." endif textline " " bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" ",,INT08_1,INT08_2" bitfld.long 0x08 14.--15. " EINT07S ,External Interrupt Input 7 Select Bit" ",,,INT07_2" bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" ",,INT06_1,INT06_2" bitfld.long 0x08 10.--11. " EINT05S ,External Interrupt Input 5 Select Bit" "INT05_0,INT05_0,INT05_1,INT05_2" textline " " bitfld.long 0x08 8.--9. " EINT04S ,External Interrupt Input 4 Select Bit" "INT04_0,INT04_0,INT04_1,INT04_2" bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" "INT03_0,INT03_0,INT03_1,INT03_2" textline " " sif (cpuis("MB9BF???R")) bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,INT02_2" bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,INT01_2" else bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,?..." bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,?..." endif textline " " bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,INT00_1,INT00_2" line.long 0xC "EPFR07,Extended Pin Function Setting Register 07" sif (cpuis("MB9BF???R")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "SCK3_0/Not produced,SCK3_0/SCK3_0,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "SOT3_0/Not produced,SOT3_0/SOT3_0,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" "SIN3_0,SIN3_0,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "SCK2_0/Not produced,SCK2_0/SCK2_0,SCK2_1/SCK2_1,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "SOT2_0/Not produced,SOT2_0/SOT2_0,SOT2_1/SOT2_1,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" "SIN2_0,SIN2_0,SIN2_1,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "SCK1_0/Not produced,SCK1_0/SCK1_0,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "SOT1_0/Not produced,SOT1_0/SOT1_0,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" "SIN1_0,SIN1_0,SIN1_1,?..." else bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "/Not produced,,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "/Not produced,,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" ",SIN3_0,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "/Not produced,,,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "/Not produced,,,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" ",,,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "/Not produced,,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "/Not produced,,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" "SIN1_0,SIN1_0,SIN1_1,?..." endif textline " " bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,SCK0_1/SCK0_1,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,SOT0_1/SOT0_1,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,SIN0_1,?..." line.long 0x10 "EPFR08,Extended Pin Function Setting Register 08" sif (cpuis("MB9BF???R")) bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "SCK7_0/Not produced,SCK7_0/SCK7_0,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "SOT7_0/Not produced,SOT7_0/SOT7_0,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" "SIN7_0,SIN7_0,SIN7_1,?..." else bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "/Not produced,,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "/Not produced,,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" ",,SIN7_1,?..." endif textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,SIN6_1,?..." textline " " sif (cpuis("MB9BF???R")) bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,SCK5_1/SCK5_1,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,SOT5_1/SOT5_1,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,SIN5_1,SIN5_2" else bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,SIN5_1,SIN5_2" endif textline " " bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,SCK4_1/SCK4_1,SCK4_2/SCK4_2" bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,SOT4_1/SOT4_1,SOT4_2/SOT4_2" bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,SIN4_1,SIN4_2" textline " " bitfld.long 0x10 2.--3. " CTS4S ,CTS4S Input Select Bit" "CTS4_0,CTS4_0,CTS4_1,CTS4_2" bitfld.long 0x10 0.--1. " RTS4E ,RTS4E Output Select Bit" "Not produced,RTS4_0,RTS4_1,RTS4_2" line.long 0x14 "EPFR09,Extended Pin Function Setting Register 09" sif (cpuis("MB9BF41?R")||cpuis("MB9BF51?R")) bitfld.long 0x14 30.--31. " CTX1E ,Select output for CAN TX1" "Not produced,TX1_0,TX1_1,TX1_2" bitfld.long 0x14 28.--29. " CRX1S ,Select input for CAN RX1" "RX1_0,RX1_0,RX1_1,RX1_2" bitfld.long 0x14 26.--27. " CTX0E ,Select output for CAN TX0" "Not produced,TX0_0,TX0_1,TX0_2" bitfld.long 0x14 24.--25. " CRX0S ,Select input for CAN RX0" "RX0_0,RX0_0,RX0_1,RX0_2" elif (cpuis("MB9BF41?N")||cpuis("MB9BF51?N")) bitfld.long 0x14 30.--31. " CTX1E ,Select output for CAN TX1" "Not produced,,,TX1_2" bitfld.long 0x14 28.--29. " CRX1S ,Select input for CAN RX1" ",,,RX1_2" bitfld.long 0x14 26.--27. " CTX0E ,Select output for CAN TX0" "Not produced,,TX0_1,TX0_2" bitfld.long 0x14 24.--25. " CRX0S ,Select input for CAN RX0" ",,RX0_1,RX0_2" endif textline " " sif (cpuis("MB9BF???R")) bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." else bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." endif textline " " bitfld.long 0x14 10.--11. " QZIN1S ,Select input for QPRC ZIN1" ",,ZIN1_1,ZIN1_2" bitfld.long 0x14 8.--9. " QBIN1S ,Select input for QPRC BIN1" ",,BIN1_1,BIN1_2" bitfld.long 0x14 6.--7. " QAIN1S ,Select input for QPRC AIN1" ",,AIN1_1,AIN1_2" textline " " bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" "BIN0_0,BIN0_0,BIN0_1,BIN0_2" bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" "AIN0_0,AIN0_0,AIN0_1,AIN0_2" line.long 0x18 "EPFR10,Extended Pin Function Setting Register 10" bitfld.long 0x18 31. " UEA24E ,Selects output for external bus Adress24" "Not produced,Produced" bitfld.long 0x18 30. " UEA23E ,Selects output for external bus Adress23" "Not produced,Produced" bitfld.long 0x18 29. " UEA22E ,Selects output for external bus Adress22" "Not produced,Produced" textline " " bitfld.long 0x18 28. " UEA21E ,Selects output for external bus Adress21" "Not produced,Produced" bitfld.long 0x18 27. " UEA20E ,Selects output for external bus Adress20" "Not produced,Produced" bitfld.long 0x18 26. " UEA19E ,Selects output for external bus Adress19" "Not produced,Produced" textline " " bitfld.long 0x18 25. " UEA18E ,Selects output for external bus Adress18" "Not produced,Produced" bitfld.long 0x18 24. " UEA17E ,Selects output for external bus Adress17" "Not produced,Produced" bitfld.long 0x18 23. " UEA16E ,Selects output for external bus Adress16" "Not produced,Produced" textline " " bitfld.long 0x18 22. " UEA15E ,Selects output for external bus Adress15" "Not produced,Produced" bitfld.long 0x18 21. " UEA14E ,Selects output for external bus Adress14" "Not produced,Produced" bitfld.long 0x18 20. " UEA13E ,Selects output for external bus Adress13" "Not produced,Produced" textline " " bitfld.long 0x18 19. " UEA12E ,Selects output for external bus Adress12" "Not produced,Produced" bitfld.long 0x18 18. " UEA11E ,Selects output for external bus Adress11" "Not produced,Produced" bitfld.long 0x18 17. " UEA10E ,Selects output for external bus Adress10" "Not produced,Produced" textline " " bitfld.long 0x18 16. " UEA09E ,Selects output for external bus Adress09" "Not produced,Produced" bitfld.long 0x18 15. " UEA08E ,Selects output for external bus Adress08" "Not produced,Produced" bitfld.long 0x18 14. " UEA00E ,Selects output for external bus Adress00" "Not produced,Produced" textline " " bitfld.long 0x18 13. " UECS7E ,Selects output for external bus CS7" "Not produced,Produced" bitfld.long 0x18 12. " UECS6E ,Selects output for external bus CS6" "Not produced,Produced" bitfld.long 0x18 11. " UECS5E ,Selects output for external bus CS5" "Not produced,Produced" textline " " bitfld.long 0x18 10. " UECS4E ,Selects output for external bus CS4" "Not produced,Produced" bitfld.long 0x18 9. " UECS3E ,Selects output for external bus CS3" "Not produced,Produced" bitfld.long 0x18 8. " UECS2E ,Selects output for external bus CS2" "Not produced,Produced" textline " " bitfld.long 0x18 7. " UECS1E ,Selects output for external bus CS1" "Not produced,Produced" bitfld.long 0x18 6. " UEFLSE ,Selects output for external bus NAND-Flash control signal" "Not produced,Produced" bitfld.long 0x18 5. " UEOEXE ,Selects output for external bus OEX" "Not produced,Produced" textline " " bitfld.long 0x18 4. " UEDQME ,Selects output for external bus DQM" "Not produced,Produced" bitfld.long 0x18 3. " UEWEXE ,Selects output for external bus WEX" "Not produced,Produced" bitfld.long 0x18 2. " UECLKE ,Selects output for external bus clock" "Not produced,Produced" textline " " bitfld.long 0x18 1. " UEDTHB ,Selects input/output for external bus data" "Not produced,Produced" bitfld.long 0x18 0. " UEDEFB ,Selects input/output for external bus signal" "Not produced,Produced" line.long 0x1C "EPFR11,Extended Pin Function Setting Register 11" bitfld.long 0x1C 25. " UERLC ,Selects relocation ofthe external bus pin" "0,1" bitfld.long 0x1C 24. " UED15B ,Selects input/output for external bus data 15" "Not produced,Produced" bitfld.long 0x1C 23. " UED14B ,Selects output for external bus data 14" "Not produced,Produced" textline " " bitfld.long 0x1C 22. " UED13B ,Selects output for external bus data 13" "Not produced,Produced" bitfld.long 0x1C 21. " UED12B ,Selects output for external bus data 12" "Not produced,Produced" bitfld.long 0x1C 20. " UED11B ,Selects output for external bus data 11" "Not produced,Produced" textline " " bitfld.long 0x1C 19. " UED10B ,Selects output for external bus data 10" "Not produced,Produced" bitfld.long 0x1C 18. " UED09B ,Selects output for external bus data 09" "Not produced,Produced" bitfld.long 0x1C 17. " UED08B ,Selects output for external bus data 08" "Not produced,Produced" textline " " bitfld.long 0x1C 16. " UED07B ,Selects output for external bus data 07" "Not produced,Produced" bitfld.long 0x1C 15. " UED06B ,Selects output for external bus data 06" "Not produced,Produced" bitfld.long 0x1C 14. " UED05B ,Selects output for external bus data 05" "Not produced,Produced" textline " " bitfld.long 0x1C 13. " UED04B ,Selects output for external bus data 04" "Not produced,Produced" bitfld.long 0x1C 12. " UED03B ,Selects output for external bus data 03" "Not produced,Produced" bitfld.long 0x1C 11. " UED02B ,Selects output for external bus data 02" "Not produced,Produced" textline " " bitfld.long 0x1C 10. " UED01B ,Selects output for external bus data 01" "Not produced,Produced" bitfld.long 0x1C 9. " UED00B ,Selects output for external bus data 00" "Not produced,Produced" bitfld.long 0x1C 8. " UEA07E ,Selects output for external bus address 07" "Not produced,Produced" textline " " bitfld.long 0x1C 7. " UEA06E ,Selects output for external bus address 06" "Not produced,Produced" bitfld.long 0x1C 6. " UEA05E ,Selects output for external bus address 05" "Not produced,Produced" bitfld.long 0x1C 5. " UEA04E ,Selects output for external bus address 04" "Not produced,Produced" textline " " bitfld.long 0x1C 4. " UEA03E ,Selects output for external bus address 03" "Not produced,Produced" bitfld.long 0x1C 3. " UEA02E ,Selects output for external bus address 02" "Not produced,Produced" bitfld.long 0x1C 2. " UEA01E ,Selects output for external bus address 01" "Not produced,Produced" textline " " bitfld.long 0x1C 1. " UECS0E ,Selects output for external bus address 00" "Not produced,Produced" bitfld.long 0x1C 0. " UEALEE ,Selects output for external bus ALE signal" "Not produced,Produced" group.long 0x38++0x3 line.long 0x00 "EPFR14,Extended Pin Function Setting Register 14" sif (cpuis("MB9BF???R")) bitfld.long 0x00 4.--5. " QZIN2S ,Selects input for QDU-ch.2 as ZIN" "ZIN2_0,ZIN2_0,ZIN2_1,ZIN2_2" textline " " endif bitfld.long 0x00 2.--3. " QBIN2S ,Selects input for QDU-ch.2 as BIN" "BIN2_0,BIN2_0,BIN2_1,BIN2_2" bitfld.long 0x00 0.--1. " QAIN2S ,Selects input for QDU-ch.2 as AIN" "AIN2_0,AIN2_0,AIN2_1,AIN2_2" tree.end tree "Special Port Setting Register" group.long 0x580++0x3 line.long 0x0 "SPSR,Special Port Setting Register" bitfld.long 0x00 5. " USB1C ,USB (ch.1) Pin Setting Register" "Not used,Used" bitfld.long 0x00 4. " USB0C ,USB (ch.0) Pin Setting Register" "Not used,Used" bitfld.long 0x00 2. " MAINXC ,Main Clock (Oscillation) Pin Setting Register" "Not used,Used" bitfld.long 0x00 0. " SUBXC ,Sub Clock (Oscillation) Pin Setting Register" "Not used,Used" tree.end tree "Port Pseudo Open Drain Setting Registers" group.long 0x700++0x3 line.long 0x00 "PZR0,Port Pseudo Open Drain Setting Register 0" bitfld.long 0x00 15. " P0F ,Pin 0F" "High,Hi-Z" bitfld.long 0x00 14. " P0E ,Pin 0E" "High,Hi-Z" bitfld.long 0x00 13. " P0D ,Pin 0D" "High,Hi-Z" bitfld.long 0x00 12. " P0C ,Pin 0C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P0B ,Pin 0B" "High,Hi-Z" bitfld.long 0x00 10. " P0A ,Pin 0A" "High,Hi-Z" bitfld.long 0x00 9. " P09 ,Pin 09" "High,Hi-Z" bitfld.long 0x00 8. " P08 ,Pin 08" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P07 ,Pin 07" "High,Hi-Z" bitfld.long 0x00 6. " P06 ,Pin 06" "High,Hi-Z" bitfld.long 0x00 5. " P05 ,Pin 05" "High,Hi-Z" bitfld.long 0x00 4. " P04 ,Pin 04" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P03 ,Pin 03" "High,Hi-Z" bitfld.long 0x00 2. " P02 ,Pin 02" "High,Hi-Z" bitfld.long 0x00 1. " P01 ,Pin 01" "High,Hi-Z" bitfld.long 0x00 0. " P00 ,Pin 00" "High,Hi-Z" group.long 0x704++0x3 line.long 0x00 "PZR1,Port Pseudo Open Drain Setting Register 1" bitfld.long 0x00 15. " P1F ,Pin 1F" "High,Hi-Z" bitfld.long 0x00 14. " P1E ,Pin 1E" "High,Hi-Z" bitfld.long 0x00 13. " P1D ,Pin 1D" "High,Hi-Z" bitfld.long 0x00 12. " P1C ,Pin 1C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P1B ,Pin 1B" "High,Hi-Z" bitfld.long 0x00 10. " P1A ,Pin 1A" "High,Hi-Z" bitfld.long 0x00 9. " P19 ,Pin 19" "High,Hi-Z" bitfld.long 0x00 8. " P18 ,Pin 18" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P17 ,Pin 17" "High,Hi-Z" bitfld.long 0x00 6. " P16 ,Pin 16" "High,Hi-Z" bitfld.long 0x00 5. " P15 ,Pin 15" "High,Hi-Z" bitfld.long 0x00 4. " P14 ,Pin 14" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P13 ,Pin 13" "High,Hi-Z" bitfld.long 0x00 2. " P12 ,Pin 12" "High,Hi-Z" bitfld.long 0x00 1. " P11 ,Pin 11" "High,Hi-Z" bitfld.long 0x00 0. " P10 ,Pin 10" "High,Hi-Z" group.long 0x708++0x3 line.long 0x00 "PZR2,Port Pseudo Open Drain Setting Register 2" sif (cpuis("MB9BF???R")) bitfld.long 0x00 8. " P28 ,Pin 28" "High,Hi-Z" bitfld.long 0x00 7. " P27 ,Pin 27" "High,Hi-Z" bitfld.long 0x00 6. " P26 ,Pin 26" "High,Hi-Z" bitfld.long 0x00 5. " P25 ,Pin 25" "High,Hi-Z" textline " " bitfld.long 0x00 4. " P24 ,Pin 24" "High,Hi-Z" textline " " endif bitfld.long 0x00 3. " P23 ,Pin 23" "High,Hi-Z" bitfld.long 0x00 2. " P22 ,Pin 22" "High,Hi-Z" bitfld.long 0x00 1. " P21 ,Pin 21" "High,Hi-Z" bitfld.long 0x00 0. " P20 ,Pin 20" "High,Hi-Z" group.long 0x70C++0x3 line.long 0x00 "PZR3,Port Pseudo Open Drain Setting Register 3" bitfld.long 0x00 15. " P3F ,Pin 3F" "High,Hi-Z" bitfld.long 0x00 14. " P3E ,Pin 3E" "High,Hi-Z" bitfld.long 0x00 13. " P3D ,Pin 3D" "High,Hi-Z" bitfld.long 0x00 12. " P3C ,Pin 3C" "High,Hi-Z" textline " " bitfld.long 0x00 11. " P3B ,Pin 3B" "High,Hi-Z" bitfld.long 0x00 10. " P3A ,Pin 3A" "High,Hi-Z" bitfld.long 0x00 9. " P39 ,Pin 39" "High,Hi-Z" bitfld.long 0x00 8. " P38 ,Pin 38" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P37 ,Pin 37" "High,Hi-Z" bitfld.long 0x00 6. " P36 ,Pin 36" "High,Hi-Z" bitfld.long 0x00 5. " P35 ,Pin 35" "High,Hi-Z" bitfld.long 0x00 4. " P34 ,Pin 34" "High,Hi-Z" textline " " bitfld.long 0x00 3. " P33 ,Pin 33" "High,Hi-Z" bitfld.long 0x00 2. " P32 ,Pin 32" "High,Hi-Z" bitfld.long 0x00 1. " P31 ,Pin 31" "High,Hi-Z" bitfld.long 0x00 0. " P30 ,Pin 30" "High,Hi-Z" group.long 0x710++0x3 line.long 0x00 "PZR4,Port Pseudo Open Drain Setting Register 4" bitfld.long 0x00 14. " P4E ,Pin 4E" "High,Hi-Z" bitfld.long 0x00 13. " P4D ,Pin 4D" "High,Hi-Z" bitfld.long 0x00 12. " P4C ,Pin 4C" "High,Hi-Z" bitfld.long 0x00 11. " P4B ,Pin 4B" "High,Hi-Z" textline " " bitfld.long 0x00 10. " P4A ,Pin 4A" "High,Hi-Z" bitfld.long 0x00 9. " P49 ,Pin 49" "High,Hi-Z" bitfld.long 0x00 8. " P48 ,Pin 48" "High,Hi-Z" bitfld.long 0x00 7. " P47 ,Pin 47" "High,Hi-Z" textline " " bitfld.long 0x00 6. " P46 ,Pin 46" "High,Hi-Z" bitfld.long 0x00 5. " P45 ,Pin 45" "High,Hi-Z" bitfld.long 0x00 4. " P44 ,Pin 44" "High,Hi-Z" bitfld.long 0x00 3. " P43 ,Pin 43" "High,Hi-Z" textline " " bitfld.long 0x00 2. " P42 ,Pin 42" "High,Hi-Z" bitfld.long 0x00 1. " P41 ,Pin 41" "High,Hi-Z" bitfld.long 0x00 0. " P40 ,Pin 40" "High,Hi-Z" group.long 0x714++0x3 line.long 0x00 "PZR5,Port Pseudo Open Drain Setting Register 5" sif (cpuis("MB9BF???R")) bitfld.long 0x00 11. " P5B ,Pin 5B" "High,Hi-Z" bitfld.long 0x00 10. " P5A ,Pin 5A" "High,Hi-Z" bitfld.long 0x00 9. " P59 ,Pin 59" "High,Hi-Z" bitfld.long 0x00 8. " P58 ,Pin 58" "High,Hi-Z" textline " " bitfld.long 0x00 7. " P57 ,Pin 57" "High,Hi-Z" textline " " endif bitfld.long 0x00 6. " P56 ,Pin 56" "High,Hi-Z" bitfld.long 0x00 5. " P55 ,Pin 55" "High,Hi-Z" bitfld.long 0x00 4. " P54 ,Pin 54" "High,Hi-Z" bitfld.long 0x00 3. " P53 ,Pin 53" "High,Hi-Z" textline " " bitfld.long 0x00 2. " P52 ,Pin 52" "High,Hi-Z" bitfld.long 0x00 1. " P51 ,Pin 51" "High,Hi-Z" bitfld.long 0x00 0. " P50 ,Pin 50" "High,Hi-Z" group.long 0x718++0x3 line.long 0x00 "PZR6,Port Pseudo Open Drain Setting Register 6" sif (cpuis("MB9BF???R")) bitfld.long 0x00 8. " P68 ,Pin 68" "High,Hi-Z" bitfld.long 0x00 7. " P67 ,Pin 67" "High,Hi-Z" bitfld.long 0x00 6. " P66 ,Pin 66" "High,Hi-Z" bitfld.long 0x00 5. " P65 ,Pin 65" "High,Hi-Z" textline " " bitfld.long 0x00 4. " P64 ,Pin 64" "High,Hi-Z" textline " " endif bitfld.long 0x00 3. " P63 ,Pin 63" "High,Hi-Z" bitfld.long 0x00 2. " P62 ,Pin 62" "High,Hi-Z" bitfld.long 0x00 1. " P61 ,Pin 61" "High,Hi-Z" bitfld.long 0x00 0. " P60 ,Pin 60" "High,Hi-Z" sif (cpuis("MB9BF???R")) group.long 0x71C++0x3 line.long 0x00 "PZR7,Port Pseudo Open Drain Setting Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "High,Hi-Z" bitfld.long 0x00 3. " P73 ,Pin 73" "High,Hi-Z" bitfld.long 0x00 2. " P72 ,Pin 72" "High,Hi-Z" bitfld.long 0x00 1. " P71 ,Pin 71" "High,Hi-Z" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "High,Hi-Z" endif group.long 0x720++0x3 line.long 0x00 "PZR8,Port Pseudo Open Drain Setting Register 8" bitfld.long 0x00 1. " P81 ,Pin 81" "High,Hi-Z" bitfld.long 0x00 0. " P80 ,Pin 80" "High,Hi-Z" group.long 0x738++0x3 line.long 0x00 "PZRE,Port Pseudo Open Drain Setting Register E" bitfld.long 0x00 3. " PE3 ,Pin E3" "High,Hi-Z" bitfld.long 0x00 2. " PE2 ,Pin E2" "High,Hi-Z" bitfld.long 0x00 0. " PE0 ,Pin E0" "High,Hi-Z" tree.end width 12. else width 8. tree "Port Function Setting Registers" group.long 0x0++0x13 line.long 0x0 "PFR0,Port Function Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "GPIO,Input/Output" bitfld.long 0x0 14. " P0E ,Pin 0E" "GPIO,Input/Output" bitfld.long 0x0 13. " P0D ,Pin 0D" "GPIO,Input/Output" bitfld.long 0x0 12. " P0C ,Pin 0C" "GPIO,Input/Output" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "GPIO,Input/Output" bitfld.long 0x0 10. " P0A ,Pin 0A" "GPIO,Input/Output" bitfld.long 0x0 9. " P09 ,Pin 09" "GPIO,Input/Output" bitfld.long 0x0 8. " P08 ,Pin 08" "GPIO,Input/Output" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "GPIO,Input/Output" bitfld.long 0x0 6. " P06 ,Pin 06" "GPIO,Input/Output" bitfld.long 0x0 5. " P05 ,Pin 05" "GPIO,Input/Output" bitfld.long 0x0 4. " P04 ,Pin 04" "GPIO,Input/Output" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "GPIO,Input/Output" bitfld.long 0x0 2. " P02 ,Pin 02" "GPIO,Input/Output" bitfld.long 0x0 1. " P01 ,Pin 01" "GPIO,Input/Output" bitfld.long 0x0 0. " P00 ,Pin 00" "GPIO,Input/Output" line.long 0x4 "PFR1,Port Function Setting Register 1" bitfld.long 0x4 15. " P1F ,Pin 1F" "GPIO,Input/Output" bitfld.long 0x4 14. " P1E ,Pin 1E" "GPIO,Input/Output" bitfld.long 0x4 13. " P1D ,Pin 1D" "GPIO,Input/Output" bitfld.long 0x4 12. " P1C ,Pin 1C" "GPIO,Input/Output" textline " " bitfld.long 0x4 11. " P1B ,Pin 1B" "GPIO,Input/Output" bitfld.long 0x4 10. " P1A ,Pin 1A" "GPIO,Input/Output" bitfld.long 0x4 9. " P19 ,Pin 19" "GPIO,Input/Output" bitfld.long 0x4 8. " P18 ,Pin 18" "GPIO,Input/Output" textline " " bitfld.long 0x4 7. " P17 ,Pin 17" "GPIO,Input/Output" bitfld.long 0x4 6. " P16 ,Pin 16" "GPIO,Input/Output" bitfld.long 0x4 5. " P15 ,Pin 15" "GPIO,Input/Output" bitfld.long 0x4 4. " P14 ,Pin 14" "GPIO,Input/Output" textline " " bitfld.long 0x4 3. " P13 ,Pin 13" "GPIO,Input/Output" bitfld.long 0x4 2. " P12 ,Pin 12" "GPIO,Input/Output" bitfld.long 0x4 1. " P11 ,Pin 11" "GPIO,Input/Output" bitfld.long 0x4 0. " P10 ,Pin 10" "GPIO,Input/Output" line.long 0x8 "PFR2,Port Function Setting Register 2" bitfld.long 0x8 15. " P2F ,Pin 2F" "GPIO,Input/Output" bitfld.long 0x8 14. " P2E ,Pin 2E" "GPIO,Input/Output" bitfld.long 0x8 13. " P2D ,Pin 2D" "GPIO,Input/Output" bitfld.long 0x8 12. " P2C ,Pin 2C" "GPIO,Input/Output" textline " " bitfld.long 0x8 11. " P2B ,Pin 2B" "GPIO,Input/Output" bitfld.long 0x8 10. " P2A ,Pin 2A" "GPIO,Input/Output" bitfld.long 0x8 9. " P29 ,Pin 29" "GPIO,Input/Output" bitfld.long 0x8 8. " P28 ,Pin 28" "GPIO,Input/Output" textline " " bitfld.long 0x8 7. " P27 ,Pin 27" "GPIO,Input/Output" bitfld.long 0x8 6. " P26 ,Pin 26" "GPIO,Input/Output" bitfld.long 0x8 5. " P25 ,Pin 25" "GPIO,Input/Output" bitfld.long 0x8 4. " P24 ,Pin 24" "GPIO,Input/Output" textline " " bitfld.long 0x8 3. " P23 ,Pin 23" "GPIO,Input/Output" bitfld.long 0x8 2. " P22 ,Pin 22" "GPIO,Input/Output" bitfld.long 0x8 1. " P21 ,Pin 21" "GPIO,Input/Output" bitfld.long 0x8 0. " P20 ,Pin 20" "GPIO,Input/Output" line.long 0xC "PFR3,Port Function Setting Register 3" bitfld.long 0xC 15. " P3F ,Pin 3F" "GPIO,Input/Output" bitfld.long 0xC 14. " P3E ,Pin 3E" "GPIO,Input/Output" bitfld.long 0xC 13. " P3D ,Pin 3D" "GPIO,Input/Output" bitfld.long 0xC 12. " P3C ,Pin 3C" "GPIO,Input/Output" textline " " bitfld.long 0xC 11. " P3B ,Pin 3B" "GPIO,Input/Output" bitfld.long 0xC 10. " P3A ,Pin 3A" "GPIO,Input/Output" bitfld.long 0xC 9. " P39 ,Pin 39" "GPIO,Input/Output" bitfld.long 0xC 8. " P38 ,Pin 38" "GPIO,Input/Output" textline " " bitfld.long 0xC 7. " P37 ,Pin 37" "GPIO,Input/Output" bitfld.long 0xC 6. " P36 ,Pin 36" "GPIO,Input/Output" bitfld.long 0xC 5. " P35 ,Pin 35" "GPIO,Input/Output" bitfld.long 0xC 4. " P34 ,Pin 34" "GPIO,Input/Output" textline " " bitfld.long 0xC 3. " P33 ,Pin 33" "GPIO,Input/Output" bitfld.long 0xC 2. " P32 ,Pin 32" "GPIO,Input/Output" bitfld.long 0xC 1. " P31 ,Pin 31" "GPIO,Input/Output" bitfld.long 0xC 0. " P30 ,Pin 30" "GPIO,Input/Output" line.long 0x10 "PFR4,Port Function Setting Register 4" bitfld.long 0x10 15. " P4F ,Pin 4F" "GPIO,Input/Output" bitfld.long 0x10 14. " P4E ,Pin 4E" "GPIO,Input/Output" bitfld.long 0x10 13. " P4D ,Pin 4D" "GPIO,Input/Output" bitfld.long 0x10 12. " P4C ,Pin 4C" "GPIO,Input/Output" textline " " bitfld.long 0x10 11. " P4B ,Pin 4B" "GPIO,Input/Output" bitfld.long 0x10 10. " P4A ,Pin 4A" "GPIO,Input/Output" bitfld.long 0x10 9. " P49 ,Pin 49" "GPIO,Input/Output" bitfld.long 0x10 8. " P48 ,Pin 48" "GPIO,Input/Output" textline " " bitfld.long 0x10 7. " P47 ,Pin 47" "GPIO,Input/Output" bitfld.long 0x10 6. " P46 ,Pin 46" "GPIO,Input/Output" bitfld.long 0x10 5. " P45 ,Pin 45" "GPIO,Input/Output" bitfld.long 0x10 4. " P44 ,Pin 44" "GPIO,Input/Output" textline " " bitfld.long 0x10 3. " P43 ,Pin 43" "GPIO,Input/Output" bitfld.long 0x10 2. " P42 ,Pin 42" "GPIO,Input/Output" bitfld.long 0x10 1. " P41 ,Pin 41" "GPIO,Input/Output" bitfld.long 0x10 0. " P40 ,Pin 40" "GPIO,Input/Output" sif (cpuis("MB9?F?0?R")) group.long 0x14++0x7 line.long 0x0 "PFR5,Port Function Setting Register 5" bitfld.long 0x00 15. " P5F ,Pin 5F" "GPIO,Input/Output" bitfld.long 0x00 14. " P5E ,Pin 5E" "GPIO,Input/Output" bitfld.long 0x00 13. " P5D ,Pin 5D" "GPIO,Input/Output" bitfld.long 0x00 12. " P5C ,Pin 5C" "GPIO,Input/Output" textline " " bitfld.long 0x00 11. " P5B ,Pin 5B" "GPIO,Input/Output" bitfld.long 0x00 10. " P5A ,Pin 5A" "GPIO,Input/Output" bitfld.long 0x00 9. " P59 ,Pin 59" "GPIO,Input/Output" bitfld.long 0x00 8. " P58 ,Pin 58" "GPIO,Input/Output" textline " " bitfld.long 0x00 7. " P57 ,Pin 57" "GPIO,Input/Output" bitfld.long 0x00 6. " P56 ,Pin 56" "GPIO,Input/Output" bitfld.long 0x00 5. " P55 ,Pin 55" "GPIO,Input/Output" bitfld.long 0x00 4. " P54 ,Pin 54" "GPIO,Input/Output" textline " " bitfld.long 0x00 3. " P53 ,Pin 53" "GPIO,Input/Output" bitfld.long 0x00 2. " P52 ,Pin 52" "GPIO,Input/Output" bitfld.long 0x00 1. " P51 ,Pin 51" "GPIO,Input/Output" bitfld.long 0x00 0. " P50 ,Pin 50" "GPIO,Input/Output" line.long 0x04 "PFR6,Port Function Setting Register 6" bitfld.long 0x04 3. " P63 ,Pin 63" "GPIO,Input/Output" bitfld.long 0x04 2. " P62 ,Pin 62" "GPIO,Input/Output" bitfld.long 0x04 1. " P61 ,Pin 61" "GPIO,Input/Output" bitfld.long 0x04 0. " P60 ,Pin 60" "GPIO,Input/Output" endif tree.end tree "Pull-up Setting Registers" group.long 0x100++0x1B line.long 0x0 "PCR0,Pull-up Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Disabled,Enabled" bitfld.long 0x0 14. " P0E ,Pin 0E" "Disconnected,Connected" bitfld.long 0x0 13. " P0D ,Pin 0D" "Disconnected,Connected" bitfld.long 0x0 12. " P0C ,Pin 0C" "Disconnected,Connected" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Disconnected,Connected" bitfld.long 0x0 10. " P0A ,Pin 0A" "Disconnected,Connected" bitfld.long 0x0 9. " P09 ,Pin 09" "Disconnected,Connected" bitfld.long 0x0 8. " P08 ,Pin 08" "Disconnected,Connected" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Disconnected,Connected" bitfld.long 0x0 6. " P06 ,Pin 06" "Disconnected,Connected" bitfld.long 0x0 5. " P05 ,Pin 05" "Disconnected,Connected" bitfld.long 0x0 4. " P04 ,Pin 04" "Disconnected,Connected" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Disconnected,Connected" bitfld.long 0x0 2. " P02 ,Pin 02" "Disconnected,Connected" bitfld.long 0x0 1. " P01 ,Pin 01" "Disconnected,Connected" bitfld.long 0x0 0. " P00 ,Pin 00" "Disconnected,Connected" line.long 0x4 "PCR1,Pull-up Setting Register 1" bitfld.long 0x4 15. " P1F ,Pin 1F" "Disconnected,Connected" bitfld.long 0x4 14. " P1E ,Pin 1E" "Disconnected,Connected" bitfld.long 0x4 13. " P1D ,Pin 1D" "Disconnected,Connected" bitfld.long 0x4 12. " P1C ,Pin 1C" "Disconnected,Connected" textline " " bitfld.long 0x4 11. " P1B ,Pin 1B" "Disconnected,Connected" bitfld.long 0x4 10. " P1A ,Pin 1A" "Disconnected,Connected" bitfld.long 0x4 9. " P19 ,Pin 19" "Disconnected,Connected" bitfld.long 0x4 8. " P18 ,Pin 18" "Disconnected,Connected" textline " " bitfld.long 0x4 7. " P17 ,Pin 17" "Disconnected,Connected" bitfld.long 0x4 6. " P16 ,Pin 16" "Disconnected,Connected" bitfld.long 0x4 5. " P15 ,Pin 15" "Disconnected,Connected" bitfld.long 0x4 4. " P14 ,Pin 14" "Disconnected,Connected" textline " " bitfld.long 0x4 3. " P13 ,Pin 13" "Disconnected,Connected" bitfld.long 0x4 2. " P12 ,Pin 12" "Disconnected,Connected" bitfld.long 0x4 1. " P11 ,Pin 11" "Disconnected,Connected" bitfld.long 0x4 0. " P10 ,Pin 10" "Disconnected,Connected" line.long 0x8 "PCR2,Pull-up Setting Register 2" sif (cpuis("MB9?F?0?R")) bitfld.long 0x8 8. " P28 ,Pin 28" "Disconnected,Connected" bitfld.long 0x8 7. " P27 ,Pin 27" "Disconnected,Connected" bitfld.long 0x8 6. " P26 ,Pin 26" "Disconnected,Connected" bitfld.long 0x8 5. " P25 ,Pin 25" "Disconnected,Connected" textline " " bitfld.long 0x8 4. " P24 ,Pin 24" "Disconnected,Connected" textline " " endif bitfld.long 0x8 3. " P23 ,Pin 23" "Disconnected,Connected" bitfld.long 0x8 2. " P22 ,Pin 22" "Disconnected,Connected" bitfld.long 0x8 1. " P21 ,Pin 21" "Disconnected,Connected" bitfld.long 0x8 0. " P20 ,Pin 20" "Disconnected,Connected" line.long 0xC "PCR3,Pull-up Setting Register 3" bitfld.long 0xC 15. " P3F ,Pin 3F" "Disconnected,Connected" bitfld.long 0xC 14. " P3E ,Pin 3E" "Disconnected,Connected" bitfld.long 0xC 13. " P3D ,Pin 3D" "Disconnected,Connected" bitfld.long 0xC 12. " P3C ,Pin 3C" "Disconnected,Connected" textline " " bitfld.long 0xC 11. " P3B ,Pin 3B" "Disconnected,Connected" bitfld.long 0xC 10. " P3A ,Pin 3A" "Disconnected,Connected" bitfld.long 0xC 9. " P39 ,Pin 39" "Disconnected,Connected" bitfld.long 0xC 8. " P38 ,Pin 38" "Disconnected,Connected" textline " " bitfld.long 0xC 7. " P37 ,Pin 37" "Disconnected,Connected" bitfld.long 0xC 6. " P36 ,Pin 36" "Disconnected,Connected" bitfld.long 0xC 5. " P35 ,Pin 35" "Disconnected,Connected" bitfld.long 0xC 4. " P34 ,Pin 34" "Disconnected,Connected" textline " " bitfld.long 0xC 3. " P33 ,Pin 33" "Disconnected,Connected" bitfld.long 0xC 2. " P32 ,Pin 32" "Disconnected,Connected" bitfld.long 0xC 1. " P31 ,Pin 31" "Disconnected,Connected" bitfld.long 0xC 0. " P30 ,Pin 30" "Disconnected,Connected" line.long 0x10 "PCR4,Pull-up Setting Register 4" bitfld.long 0x10 14. " P4E ,Pin 4E" "Disconnected,Connected" bitfld.long 0x10 13. " P4D ,Pin 4D" "Disconnected,Connected" bitfld.long 0x10 12. " P4C ,Pin 4C" "Disconnected,Connected" bitfld.long 0x10 11. " P4B ,Pin 4B" "Disconnected,Connected" textline " " bitfld.long 0x10 10. " P4A ,Pin 4A" "Disconnected,Connected" bitfld.long 0x10 9. " P49 ,Pin 49" "Disconnected,Connected" bitfld.long 0x10 8. " P48 ,Pin 48" "Disconnected,Connected" bitfld.long 0x10 7. " P47 ,Pin 47" "Disconnected,Connected" textline " " bitfld.long 0x10 6. " P46 ,Pin 46" "Disconnected,Connected" bitfld.long 0x10 5. " P45 ,Pin 45" "Disconnected,Connected" bitfld.long 0x10 4. " P44 ,Pin 44" "Disconnected,Connected" bitfld.long 0x10 3. " P43 ,Pin 43" "Disconnected,Connected" textline " " bitfld.long 0x10 2. " P42 ,Pin 42" "Disconnected,Connected" bitfld.long 0x10 1. " P41 ,Pin 41" "Disconnected,Connected" bitfld.long 0x10 0. " P40 ,Pin 40" "Disconnected,Connected" line.long 0x14 "PCR5,Pull-up Setting Register 5" sif (cpuis("MB9?F?0?R")) bitfld.long 0x14 11. " P5B ,Pin 5B" "Disconnected,Connected" bitfld.long 0x14 10. " P5A ,Pin 5A" "Disconnected,Connected" bitfld.long 0x14 9. " P59 ,Pin 59" "Disconnected,Connected" bitfld.long 0x14 8. " P58 ,Pin 58" "Disconnected,Connected" textline " " bitfld.long 0x14 7. " P57 ,Pin 57" "Disconnected,Connected" textline " " endif bitfld.long 0x14 6. " P56 ,Pin 56" "Disconnected,Connected" bitfld.long 0x14 5. " P55 ,Pin 55" "Disconnected,Connected" bitfld.long 0x14 4. " P54 ,Pin 54" "Disconnected,Connected" bitfld.long 0x14 3. " P53 ,Pin 53" "Disconnected,Connected" textline " " bitfld.long 0x14 2. " P52 ,Pin 52" "Disconnected,Connected" bitfld.long 0x14 1. " P51 ,Pin 51" "Disconnected,Connected" bitfld.long 0x14 0. " P50 ,Pin 50" "Disconnected,Connected" line.long 0x18 "PCR6,Pull-up Setting Register 6" sif (cpuis("MB9?F?0?R")) bitfld.long 0x18 8. " P78 ,Pin 88" "Disconnected,Connected" bitfld.long 0x18 7. " P87 ,Pin 87" "Disconnected,Connected" bitfld.long 0x18 6. " P86 ,Pin 86" "Disconnected,Connected" bitfld.long 0x18 5. " P85 ,Pin 85" "Disconnected,Connected" textline " " bitfld.long 0x18 4. " P84 ,Pin 84" "Disconnected,Connected" textline " " endif bitfld.long 0x18 3. " P63 ,Pin 63" "Disconnected,Connected" bitfld.long 0x18 2. " P62 ,Pin 62" "Disconnected,Connected" bitfld.long 0x18 1. " P61 ,Pin 61" "Disconnected,Connected" bitfld.long 0x18 0. " P60 ,Pin 60" "Disconnected,Connected" sif (cpuis("MB9?F?0?R")) group.long 0x11C++0x3 line.long 0x00 "PCR7,Pull-up Setting Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "Disconnected,Connected" bitfld.long 0x00 3. " P73 ,Pin 73" "Disconnected,Connected" bitfld.long 0x00 2. " P72 ,Pin 72" "Disconnected,Connected" bitfld.long 0x00 1. " P71 ,Pin 71" "Disconnected,Connected" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "Disconnected,Connected" endif tree.end tree "Port input/output Direction Setting Registers" group.long 0x200++0x1B line.long 0x0 "DDR0,Port input/output Direction Setting Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Input,Output" bitfld.long 0x0 14. " P0E ,Pin 0E" "Input,Output" bitfld.long 0x0 13. " P0D ,Pin 0D" "Input,Output" bitfld.long 0x0 12. " P0C ,Pin 0C" "Input,Output" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Input,Output" bitfld.long 0x0 10. " P0A ,Pin 0A" "Input,Output" bitfld.long 0x0 9. " P09 ,Pin 09" "Input,Output" bitfld.long 0x0 8. " P08 ,Pin 08" "Input,Output" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Input,Output" bitfld.long 0x0 6. " P06 ,Pin 06" "Input,Output" bitfld.long 0x0 5. " P05 ,Pin 05" "Input,Output" bitfld.long 0x0 4. " P04 ,Pin 04" "Input,Output" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Input,Output" bitfld.long 0x0 2. " P02 ,Pin 02" "Input,Output" bitfld.long 0x0 1. " P01 ,Pin 01" "Input,Output" bitfld.long 0x0 0. " P00 ,Pin 00" "Input,Output" line.long 0x4 "DDR1,Port input/output Direction Setting Register 1" bitfld.long 0x4 15. " P1F ,Pin 1F" "Input,Output" bitfld.long 0x4 14. " P1E ,Pin 1E" "Input,Output" bitfld.long 0x4 13. " P1D ,Pin 1D" "Input,Output" bitfld.long 0x4 12. " P1C ,Pin 1C" "Input,Output" textline " " bitfld.long 0x4 11. " P1B ,Pin 1B" "Input,Output" bitfld.long 0x4 10. " P1A ,Pin 1A" "Input,Output" bitfld.long 0x4 9. " P19 ,Pin 19" "Input,Output" bitfld.long 0x4 8. " P18 ,Pin 18" "Input,Output" textline " " bitfld.long 0x4 7. " P17 ,Pin 17" "Input,Output" bitfld.long 0x4 6. " P16 ,Pin 16" "Input,Output" bitfld.long 0x4 5. " P15 ,Pin 15" "Input,Output" bitfld.long 0x4 4. " P14 ,Pin 14" "Input,Output" textline " " bitfld.long 0x4 3. " P13 ,Pin 13" "Input,Output" bitfld.long 0x4 2. " P12 ,Pin 12" "Input,Output" bitfld.long 0x4 1. " P11 ,Pin 11" "Input,Output" bitfld.long 0x4 0. " P10 ,Pin 10" "Input,Output" line.long 0x8 "DDR2,Port input/output Direction Setting Register 2" sif (cpuis("MB9?F?0?R")) bitfld.long 0x8 8. " P28 ,Pin 28" "Input,Output" bitfld.long 0x8 7. " P27 ,Pin 27" "Input,Output" bitfld.long 0x8 6. " P26 ,Pin 26" "Input,Output" bitfld.long 0x8 5. " P25 ,Pin 25" "Input,Output" textline " " bitfld.long 0x8 4. " P24 ,Pin 24" "Input,Output" textline " " endif bitfld.long 0x8 3. " P23 ,Pin 23" "Input,Output" bitfld.long 0x8 2. " P22 ,Pin 22" "Input,Output" bitfld.long 0x8 1. " P21 ,Pin 21" "Input,Output" bitfld.long 0x8 0. " P20 ,Pin 20" "Input,Output" line.long 0xC "DDR3,Port input/output Direction Setting Register 3" bitfld.long 0xC 15. " P3F ,Pin 3F" "Input,Output" bitfld.long 0xC 14. " P3E ,Pin 3E" "Input,Output" bitfld.long 0xC 13. " P3D ,Pin 3D" "Input,Output" bitfld.long 0xC 12. " P3C ,Pin 3C" "Input,Output" textline " " bitfld.long 0xC 11. " P3B ,Pin 3B" "Input,Output" bitfld.long 0xC 10. " P3A ,Pin 3A" "Input,Output" bitfld.long 0xC 9. " P39 ,Pin 39" "Input,Output" bitfld.long 0xC 8. " P38 ,Pin 38" "Input,Output" textline " " bitfld.long 0xC 7. " P37 ,Pin 37" "Input,Output" bitfld.long 0xC 6. " P36 ,Pin 36" "Input,Output" bitfld.long 0xC 5. " P35 ,Pin 35" "Input,Output" bitfld.long 0xC 4. " P34 ,Pin 34" "Input,Output" textline " " bitfld.long 0xC 3. " P33 ,Pin 33" "Input,Output" bitfld.long 0xC 2. " P32 ,Pin 32" "Input,Output" bitfld.long 0xC 1. " P31 ,Pin 31" "Input,Output" bitfld.long 0xC 0. " P30 ,Pin 30" "Input,Output" line.long 0x10 "DDR4,Port input/output Direction Setting Register 4" bitfld.long 0x10 14. " P4E ,Pin 4E" "Input,Output" bitfld.long 0x10 13. " P4D ,Pin 4D" "Input,Output" bitfld.long 0x10 12. " P4C ,Pin 4C" "Input,Output" bitfld.long 0x10 11. " P4B ,Pin 4B" "Input,Output" textline " " bitfld.long 0x10 10. " P4A ,Pin 4A" "Input,Output" bitfld.long 0x10 9. " P49 ,Pin 49" "Input,Output" bitfld.long 0x10 8. " P48 ,Pin 48" "Input,Output" bitfld.long 0x10 7. " P47 ,Pin 47" "Input,Output" textline " " bitfld.long 0x10 6. " P46 ,Pin 46" "Input,Output" bitfld.long 0x10 5. " P45 ,Pin 45" "Input,Output" bitfld.long 0x10 4. " P44 ,Pin 44" "Input,Output" bitfld.long 0x10 3. " P43 ,Pin 43" "Input,Output" textline " " bitfld.long 0x10 2. " P42 ,Pin 42" "Input,Output" bitfld.long 0x10 1. " P41 ,Pin 41" "Input,Output" bitfld.long 0x10 0. " P40 ,Pin 40" "Input,Output" line.long 0x14 "DDR5,Port input/output Direction Setting Register 5" sif (cpuis("MB9?F?0?R")) bitfld.long 0x14 11. " P5B ,Pin 5B" "Input,Output" bitfld.long 0x14 10. " P5A ,Pin 5A" "Input,Output" bitfld.long 0x14 9. " P59 ,Pin 59" "Input,Output" bitfld.long 0x14 8. " P58 ,Pin 58" "Input,Output" textline " " bitfld.long 0x14 7. " P57 ,Pin 57" "Input,Output" textline " " endif bitfld.long 0x14 6. " P56 ,Pin 56" "Input,Output" bitfld.long 0x14 5. " P55 ,Pin 55" "Input,Output" bitfld.long 0x14 4. " P54 ,Pin 54" "Input,Output" bitfld.long 0x14 3. " P53 ,Pin 53" "Input,Output" textline " " bitfld.long 0x14 2. " P52 ,Pin 52" "Input,Output" bitfld.long 0x14 1. " P51 ,Pin 51" "Input,Output" bitfld.long 0x14 0. " P50 ,Pin 50" "Input,Output" line.long 0x18 "DDR6,Port input/output Direction Setting Register 6" sif (cpuis("MB9?F?0?R")) bitfld.long 0x18 8. " P78 ,Pin 88" "Input,Output" bitfld.long 0x18 7. " P87 ,Pin 87" "Input,Output" bitfld.long 0x18 6. " P86 ,Pin 86" "Input,Output" bitfld.long 0x18 5. " P85 ,Pin 85" "Input,Output" textline " " bitfld.long 0x18 4. " P84 ,Pin 84" "Input,Output" textline " " endif bitfld.long 0x18 3. " P63 ,Pin 63" "Input,Output" bitfld.long 0x18 2. " P62 ,Pin 62" "Input,Output" bitfld.long 0x18 1. " P61 ,Pin 61" "Input,Output" bitfld.long 0x18 0. " P60 ,Pin 60" "Input,Output" sif (cpuis("MB9?F?0?R")) group.long 0x21C++0x3 line.long 0x00 "DDR7,Port input/output Direction Setting Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "Input,Output" bitfld.long 0x00 3. " P73 ,Pin 73" "Input,Output" bitfld.long 0x00 2. " P72 ,Pin 72" "Input,Output" bitfld.long 0x00 1. " P71 ,Pin 71" "Input,Output" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "Input,Output" endif tree.end tree "Port Input Data Registers" rgroup.long 0x300++0x1B line.long 0x0 "PDIR0,Port Input Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" bitfld.long 0x0 14. " P0E ,Pin 0E" "Low,High" bitfld.long 0x0 13. " P0D ,Pin 0D" "Low,High" bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" line.long 0x4 "PDIR1,Port Input Data Register 1" bitfld.long 0x4 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x4 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x4 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x4 12. " P1C ,Pin 1C" "Low,High" textline " " bitfld.long 0x4 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x4 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x4 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x4 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x4 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x4 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x4 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x4 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x4 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x4 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x4 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x4 0. " P10 ,Pin 10" "Low,High" line.long 0x8 "PDIR2,Port Input Data Register 2" sif (cpuis("MB9?F?0?R")) bitfld.long 0x8 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x8 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x8 6. " P26 ,Pin 26" "Low,High" bitfld.long 0x8 5. " P25 ,Pin 25" "Low,High" textline " " bitfld.long 0x8 4. " P24 ,Pin 24" "Low,High" textline " " endif bitfld.long 0x8 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x8 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x8 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x8 0. " P20 ,Pin 20" "Low,High" line.long 0xC "PDIR3,Port Input Data Register 3" bitfld.long 0xC 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0xC 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0xC 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0xC 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0xC 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0xC 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0xC 9. " P39 ,Pin 39" "Low,High" bitfld.long 0xC 8. " P38 ,Pin 38" "Low,High" textline " " bitfld.long 0xC 7. " P37 ,Pin 37" "Low,High" bitfld.long 0xC 6. " P36 ,Pin 36" "Low,High" bitfld.long 0xC 5. " P35 ,Pin 35" "Low,High" bitfld.long 0xC 4. " P34 ,Pin 34" "Low,High" textline " " bitfld.long 0xC 3. " P33 ,Pin 33" "Low,High" bitfld.long 0xC 2. " P32 ,Pin 32" "Low,High" bitfld.long 0xC 1. " P31 ,Pin 31" "Low,High" bitfld.long 0xC 0. " P30 ,Pin 30" "Low,High" line.long 0x10 "PDIR4,Port Input Data Register 4" bitfld.long 0x10 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x10 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x10 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x10 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x10 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x10 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x10 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x10 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x10 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x10 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x10 4. " P44 ,Pin 44" "Low,High" bitfld.long 0x10 3. " P43 ,Pin 43" "Low,High" textline " " bitfld.long 0x10 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x10 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x10 0. " P40 ,Pin 40" "Low,High" line.long 0x14 "PDIR5,Port Input Data Register 5" sif (cpuis("MB9?F?0?R")) bitfld.long 0x14 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x14 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x14 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x14 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x14 7. " P57 ,Pin 57" "Low,High" textline " " endif bitfld.long 0x14 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x14 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x14 4. " P54 ,Pin 54" "Low,High" bitfld.long 0x14 3. " P53 ,Pin 53" "Low,High" textline " " bitfld.long 0x14 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x14 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x14 0. " P50 ,Pin 50" "Low,High" line.long 0x18 "PDIR6,Port Input Data Register 6" sif (cpuis("MB9?F?0?R")) bitfld.long 0x18 8. " P78 ,Pin 88" "Low,High" bitfld.long 0x18 7. " P87 ,Pin 87" "Low,High" bitfld.long 0x18 6. " P86 ,Pin 86" "Low,High" bitfld.long 0x18 5. " P85 ,Pin 85" "Low,High" textline " " bitfld.long 0x18 4. " P84 ,Pin 84" "Low,High" textline " " endif bitfld.long 0x18 3. " P63 ,Pin 63" "Low,High" bitfld.long 0x18 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x18 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x18 0. " P60 ,Pin 60" "Low,High" sif (cpuis("MB9?F?0?R")) rgroup.long 0x31C++0x3 line.long 0x00 "PDIR7,Port Input Data Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x00 3. " P73 ,Pin 73" "Low,High" bitfld.long 0x00 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x00 1. " P71 ,Pin 71" "Low,High" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "Low,High" endif tree.end tree "Port Output Data Registers" group.long 0x400++0x1B line.long 0x0 "PDOR0,Port Output Data Register 0" bitfld.long 0x0 15. " P0F ,Pin 0F" "Low,High" bitfld.long 0x0 14. " P0E ,Pin 0E" "Low,High" bitfld.long 0x0 13. " P0D ,Pin 0D" "Low,High" bitfld.long 0x0 12. " P0C ,Pin 0C" "Low,High" textline " " bitfld.long 0x0 11. " P0B ,Pin 0B" "Low,High" bitfld.long 0x0 10. " P0A ,Pin 0A" "Low,High" bitfld.long 0x0 9. " P09 ,Pin 09" "Low,High" bitfld.long 0x0 8. " P08 ,Pin 08" "Low,High" textline " " bitfld.long 0x0 7. " P07 ,Pin 07" "Low,High" bitfld.long 0x0 6. " P06 ,Pin 06" "Low,High" bitfld.long 0x0 5. " P05 ,Pin 05" "Low,High" bitfld.long 0x0 4. " P04 ,Pin 04" "Low,High" textline " " bitfld.long 0x0 3. " P03 ,Pin 03" "Low,High" bitfld.long 0x0 2. " P02 ,Pin 02" "Low,High" bitfld.long 0x0 1. " P01 ,Pin 01" "Low,High" bitfld.long 0x0 0. " P00 ,Pin 00" "Low,High" line.long 0x4 "PDOR1,Port Output Data Register 1" bitfld.long 0x4 15. " P1F ,Pin 1F" "Low,High" bitfld.long 0x4 14. " P1E ,Pin 1E" "Low,High" bitfld.long 0x4 13. " P1D ,Pin 1D" "Low,High" bitfld.long 0x4 12. " P1C ,Pin 1C" "Low,High" textline " " bitfld.long 0x4 11. " P1B ,Pin 1B" "Low,High" bitfld.long 0x4 10. " P1A ,Pin 1A" "Low,High" bitfld.long 0x4 9. " P19 ,Pin 19" "Low,High" bitfld.long 0x4 8. " P18 ,Pin 18" "Low,High" textline " " bitfld.long 0x4 7. " P17 ,Pin 17" "Low,High" bitfld.long 0x4 6. " P16 ,Pin 16" "Low,High" bitfld.long 0x4 5. " P15 ,Pin 15" "Low,High" bitfld.long 0x4 4. " P14 ,Pin 14" "Low,High" textline " " bitfld.long 0x4 3. " P13 ,Pin 13" "Low,High" bitfld.long 0x4 2. " P12 ,Pin 12" "Low,High" bitfld.long 0x4 1. " P11 ,Pin 11" "Low,High" bitfld.long 0x4 0. " P10 ,Pin 10" "Low,High" line.long 0x8 "PDOR2,Port Output Data Register 2" sif (cpuis("MB9?F?0?R")) bitfld.long 0x8 8. " P28 ,Pin 28" "Low,High" bitfld.long 0x8 7. " P27 ,Pin 27" "Low,High" bitfld.long 0x8 6. " P26 ,Pin 26" "Low,High" bitfld.long 0x8 5. " P25 ,Pin 25" "Low,High" textline " " bitfld.long 0x8 4. " P24 ,Pin 24" "Low,High" textline " " endif bitfld.long 0x8 3. " P23 ,Pin 23" "Low,High" bitfld.long 0x8 2. " P22 ,Pin 22" "Low,High" bitfld.long 0x8 1. " P21 ,Pin 21" "Low,High" bitfld.long 0x8 0. " P20 ,Pin 20" "Low,High" line.long 0xC "PDOR3,Port Output Data Register 3" bitfld.long 0xC 15. " P3F ,Pin 3F" "Low,High" bitfld.long 0xC 14. " P3E ,Pin 3E" "Low,High" bitfld.long 0xC 13. " P3D ,Pin 3D" "Low,High" bitfld.long 0xC 12. " P3C ,Pin 3C" "Low,High" textline " " bitfld.long 0xC 11. " P3B ,Pin 3B" "Low,High" bitfld.long 0xC 10. " P3A ,Pin 3A" "Low,High" bitfld.long 0xC 9. " P39 ,Pin 39" "Low,High" bitfld.long 0xC 8. " P38 ,Pin 38" "Low,High" textline " " bitfld.long 0xC 7. " P37 ,Pin 37" "Low,High" bitfld.long 0xC 6. " P36 ,Pin 36" "Low,High" bitfld.long 0xC 5. " P35 ,Pin 35" "Low,High" bitfld.long 0xC 4. " P34 ,Pin 34" "Low,High" textline " " bitfld.long 0xC 3. " P33 ,Pin 33" "Low,High" bitfld.long 0xC 2. " P32 ,Pin 32" "Low,High" bitfld.long 0xC 1. " P31 ,Pin 31" "Low,High" bitfld.long 0xC 0. " P30 ,Pin 30" "Low,High" line.long 0x10 "PDOR4,Port Output Data Register 4" bitfld.long 0x10 14. " P4E ,Pin 4E" "Low,High" bitfld.long 0x10 13. " P4D ,Pin 4D" "Low,High" bitfld.long 0x10 12. " P4C ,Pin 4C" "Low,High" bitfld.long 0x10 11. " P4B ,Pin 4B" "Low,High" textline " " bitfld.long 0x10 10. " P4A ,Pin 4A" "Low,High" bitfld.long 0x10 9. " P49 ,Pin 49" "Low,High" bitfld.long 0x10 8. " P48 ,Pin 48" "Low,High" bitfld.long 0x10 7. " P47 ,Pin 47" "Low,High" textline " " bitfld.long 0x10 6. " P46 ,Pin 46" "Low,High" bitfld.long 0x10 5. " P45 ,Pin 45" "Low,High" bitfld.long 0x10 4. " P44 ,Pin 44" "Low,High" bitfld.long 0x10 3. " P43 ,Pin 43" "Low,High" textline " " bitfld.long 0x10 2. " P42 ,Pin 42" "Low,High" bitfld.long 0x10 1. " P41 ,Pin 41" "Low,High" bitfld.long 0x10 0. " P40 ,Pin 40" "Low,High" line.long 0x14 "PDOR5,Port Output Data Register 5" sif (cpuis("MB9?F?0?R")) bitfld.long 0x14 11. " P5B ,Pin 5B" "Low,High" bitfld.long 0x14 10. " P5A ,Pin 5A" "Low,High" bitfld.long 0x14 9. " P59 ,Pin 59" "Low,High" bitfld.long 0x14 8. " P58 ,Pin 58" "Low,High" textline " " bitfld.long 0x14 7. " P57 ,Pin 57" "Low,High" textline " " endif bitfld.long 0x14 6. " P56 ,Pin 56" "Low,High" bitfld.long 0x14 5. " P55 ,Pin 55" "Low,High" bitfld.long 0x14 4. " P54 ,Pin 54" "Low,High" bitfld.long 0x14 3. " P53 ,Pin 53" "Low,High" textline " " bitfld.long 0x14 2. " P52 ,Pin 52" "Low,High" bitfld.long 0x14 1. " P51 ,Pin 51" "Low,High" bitfld.long 0x14 0. " P50 ,Pin 50" "Low,High" line.long 0x18 "PDOR6,Port Output Data Register 6" sif (cpuis("MB9?F?0?R")) bitfld.long 0x18 8. " P78 ,Pin 88" "Low,High" bitfld.long 0x18 7. " P87 ,Pin 87" "Low,High" bitfld.long 0x18 6. " P86 ,Pin 86" "Low,High" bitfld.long 0x18 5. " P85 ,Pin 85" "Low,High" textline " " bitfld.long 0x18 4. " P84 ,Pin 84" "Low,High" textline " " endif bitfld.long 0x18 3. " P63 ,Pin 63" "Low,High" bitfld.long 0x18 2. " P62 ,Pin 62" "Low,High" bitfld.long 0x18 1. " P61 ,Pin 61" "Low,High" bitfld.long 0x18 0. " P60 ,Pin 60" "Low,High" sif (cpuis("MB9?F?0?R")) group.long 0x41C++0x3 line.long 0x00 "PDOR7,Port Output Data Register 7" bitfld.long 0x00 4. " P74 ,Pin 74" "Low,High" bitfld.long 0x00 3. " P73 ,Pin 73" "Low,High" bitfld.long 0x00 2. " P72 ,Pin 72" "Low,High" bitfld.long 0x00 1. " P71 ,Pin 71" "Low,High" textline " " bitfld.long 0x00 0. " P70 ,Pin 70" "Low,High" endif group.long 0x420++0x3 line.long 0x00 "PDOR8,Port Output Data Register 8" bitfld.long 0x00 1. " P81 ,Pin 81" "Low,High" bitfld.long 0x00 0. " P80 ,Pin 80" "Low,High" tree.end tree "Analog Input Setting Register" group.long 0x500++0x3 line.long 0x0 "ADE,Analog Input Setting Register" bitfld.long 0x0 15. " P1F ,Pin 1F" "Digital I/O,Analog IN" bitfld.long 0x0 14. " P1E ,Pin 1E" "Digital I/O,Analog IN" bitfld.long 0x0 13. " P1D ,Pin 1D" "Digital I/O,Analog IN" bitfld.long 0x0 12. " P1C ,Pin 1C" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 11. " P1B ,Pin 1B" "Digital I/O,Analog IN" bitfld.long 0x0 10. " P1A ,Pin 1A" "Digital I/O,Analog IN" bitfld.long 0x0 9. " P19 ,Pin 19" "Digital I/O,Analog IN" bitfld.long 0x0 8. " P18 ,Pin 18" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 7. " P17 ,Pin 17" "Digital I/O,Analog IN" bitfld.long 0x0 6. " P16 ,Pin 16" "Digital I/O,Analog IN" bitfld.long 0x0 5. " P15 ,Pin 15" "Digital I/O,Analog IN" bitfld.long 0x0 4. " P14 ,Pin 14" "Digital I/O,Analog IN" textline " " bitfld.long 0x0 3. " P13 ,Pin 13" "Digital I/O,Analog IN" bitfld.long 0x0 2. " P12 ,Pin 12" "Digital I/O,Analog IN" bitfld.long 0x0 1. " P11 ,Pin 11" "Digital I/O,Analog IN" bitfld.long 0x0 0. " P10 ,Pin 10" "Digital I/O,Analog IN" tree.end tree "Extended Pin Function Setting Register" group.long 0x600++0xB line.long 0x0 "EPFR00,Extended Pin Function Setting Register 00" bitfld.long 0x00 25. " TRC1E ,Select whether to use two pins of TRACED2 and TRACED3" "Not used,Used" bitfld.long 0x00 24. " TRC0E ,Select whether to use three pins of TRACECLK, TRACED0, and TRACED1" "Not used,Used" bitfld.long 0x00 17. " JTAGEN1S ,Select whether to use two pins of TRSTX and TDI" "Not used,Used" textline " " bitfld.long 0x00 16. " JTAGEN0S ,Select whether to use three pins of TCK, TMS, and TDO" "Not used,Used" bitfld.long 0x00 9. " USBP0E ,Selects whether to produce output D+ resistor control signal (HCONTX) for USBch.0." "Not produced,Produced" bitfld.long 0x00 1. " CROUTE ,Selects whether to produce internal high-speed CR oscillation output" "Not produced,Produced" textline " " bitfld.long 0x00 0. " NMIS ,Select whether to use the NMIX pin" "Not used,Used" line.long 0x4 "EPFR01,Extended Pin Function Setting Register 01" bitfld.long 0x04 29.--31. " IC03S ,IC03 Input Select Bit" "IC03_0,IC03_0,IC03_1,IC03_2,MFSch.3LSYN,MFSch.7LSYN,,CRTRIM" bitfld.long 0x04 26.--28. " IS02S ,IC02 Input Select Bit" "IC02_0,IC02_0,Uses IC02_1,IC02_2,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x04 23.--25. " IC01S ,IC01 Input Select Bit" "IC01_0,IC01_0,IC01_1,IC01_2,MFSch.1LSYN,MFSch.5LSYN,?..." textline " " bitfld.long 0x04 20.--22. " IC00S ,IC00 Input Select Bit" "IC00_0,IC00_0,IC00_1,IC00_2,MFSch.0LSYN,MFSch.4LSYN,?..." bitfld.long 0x04 18.--19. " FRCK0S ,FRCK0 Input Select Bit" "FRCK0_0,FRCK0_0,FRCK0_1,FRCK0_2" bitfld.long 0x04 16.--17. " DTTI0S ,DTTIX0 Input Select Bit" "DTTIX0_0,DTTIX0_0,DTTIX0_1,?..." textline " " bitfld.long 0x04 12. " DTTI0C ,DTTIX0 Function Select Bit" "Not switched,Switched" bitfld.long 0x04 10.--11. " RTO05E ,RTO05E Output Select Bit" "Not produced,RTO05_0,RTO05_1,?..." bitfld.long 0x04 8.--9. " RTO04E ,RTO04E Output Select Bit" "Not produced,RTO04_0,RTO04_1,?..." textline " " bitfld.long 0x04 6.--7. " RTO03E ,RTO03E Output Select Bit" "Not produced,RTO03_0,RTO03_1,?..." bitfld.long 0x04 4.--5. " RTO02E ,RTO02E Output Select Bit" "Not produced,RTO02_0,RTO02_1,?..." bitfld.long 0x04 2.--3. " RTO01E ,RTO01E Output Select Bit" "Not produced,RTO01_0,RTO01_1,?..." textline " " bitfld.long 0x04 0.--1. " RTO00E ,RTO00E Output Select Bit" "Not produced,RTO00_0,RTO00_1,?..." line.long 0x8 "EPFR02,Extended Pin Function Setting Register 02" bitfld.long 0x08 29.--31. " IC13S ,IC13 Input Select Bit" "IC13_0,IC13_0,IC13_1,,MFSch.3LSYN,MFSch.7LSYN,?..." bitfld.long 0x08 26.--28. " IS12S ,IC12 Input Select Bit" "IC12_0,IC12_0,Uses IC12_1,,MFSch.2LSYN,MFSch.6LSYN,?..." bitfld.long 0x08 23.--25. " IC11S ,IC11 Input Select Bit" "IC11_0,IC11_0,IC11_1,,MFSch.1LSYN,MFSch.5LSYN,?..." textline " " bitfld.long 0x08 20.--22. " IC10S ,IC10 Input Select Bit" "IC10_0,IC10_0,IC10_1,,MFSch.0LSYN,MFSch.4LSYN,?..." bitfld.long 0x08 18.--19. " FRCK1S ,FRCK1 Input Select Bit" "FRCK1_0,FRCK1_0,FRCK1_1,?..." bitfld.long 0x08 16.--17. " DTTI1S ,DTTIX1 Input Select Bit" "DTTIX1_0,DTTIX1_0,DTTIX1_1,?..." textline " " bitfld.long 0x08 12. " DTTI1C ,DTTIX1 Function Select Bit" "Not switched,Switched" bitfld.long 0x08 10.--11. " RTO15E ,RTO15E Output Select Bit" "Not produced,RTO15_0,RTO15_1,?..." bitfld.long 0x08 8.--9. " RTO14E ,RTO14E Output Select Bit" "Not produced,RTO14_0,RTO14_1,?..." textline " " bitfld.long 0x08 6.--7. " RTO13E ,RTO13E Output Select Bit" "Not produced,RTO13_0,RTO13_1,?..." bitfld.long 0x08 4.--5. " RTO012E ,RTO12E Output Select Bit" "Not produced,RTO12_0,RTO12_1,?..." bitfld.long 0x08 2.--3. " RTO11E ,RTO11E Output Select Bit" "Not produced,RTO11_0,RTO11_1,?..." textline " " bitfld.long 0x08 0.--1. " RTO10E ,RTO10E Output Select Bit" "Not produced,RTO01_0,RTO01_1,?..." group.long 0x610++0x1B line.long 0x0 "EPFR04,Extended Pin Function Setting Register 04" bitfld.long 0x00 28.--29. " TIOB3S ,TIOB3 Input Select Bit" "TIOB3_0,TIOB3_0,TIOB3_1,TIOB3_2" bitfld.long 0x00 26.--27. " TIOA3E ,TIOA3E Output Select Bit" "Not produced,TIOA3_0,TIOA3_1,TIOA3_2" bitfld.long 0x00 24.--25. " TIOA3S ,TIOA3 Input Select Bit" "TIOA3_0,TIOA3_0,TIOA3_1,TIOA3_2" textline " " bitfld.long 0x00 20.--21. " TIOB2S ,TIOB2 Input Select Bit" "TIOB2_0,TIOB2_0,TIOB2_1,TIOB2_2" bitfld.long 0x00 18.--19. " TIOA2E ,TIOA2E Output Select Bit" "Not produced,TIOA2_0,TIOA2_1,TIOA2_2" bitfld.long 0x00 16.--17. " TIOA2S ,TIOA2 Input Select Bit" "TIOA2_0,TIOA2_0,TIOA2_1,TIOA2_2" textline " " bitfld.long 0x00 12.--13. " TIOB1S ,TIOB1 Input Select Bit" "TIOB1_0,TIOB1_0,TIOB1_1,TIOB1_2" bitfld.long 0x00 10.--11. " TIOA1E ,TIOA1E Output Select Bit" "Not produced,TIOA1_0,TIOA1_1,TIOA1_2" bitfld.long 0x00 8.--9. " TIOA1S ,TIOA1 Input Select Bit" "TIOA1_0,TIOA1_0,TIOA1_1,TIOA1_2" textline " " bitfld.long 0x00 4.--5. " TIOB0S ,TIOB0 Input Select Bit" "TIOB0_0,TIOB0_0,TIOB0_1,TIOB0_2" bitfld.long 0x00 2.--3. " TIOA0E ,TIOA0E Output Select Bit" "Not produced,TIOA0_0,TIOA0_1,TIOA0_2" line.long 0x4 "EPFR05,Extended Pin Function Setting Register 05" sif (cpuis("MB9?F?0?R")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" "TIOB7_0,TIOB7_0,TIOB7_1,TIOB7_2" bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,TIOA7_0,TIOA7_1,TIOA7_2" bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" "TIOA7_0,TIOA7_0,TIOA7_1,TIOA7_2" textline " " elif (cpuis("MB9?F?0?N")) bitfld.long 0x04 28.--29. " TIOB7S ,TIOB7 Input Select Bit" ",,TIOB7_1,?..." bitfld.long 0x04 26.--27. " TIOA7E ,TIOA7E Output Select Bit" "Not produced,,TIOA7_1,?..." bitfld.long 0x04 24.--25. " TIOA7S ,TIOA7 Input Select Bit" ",,TIOA7_1,?..." textline " " endif bitfld.long 0x04 20.--21. " TIOB6S ,TIOB6 Input Select Bit" "TIOB6_0,TIOB6_0,TIOB6_1,TIOB6_2" bitfld.long 0x04 18.--19. " TIOA6E ,TIOA6E Output Select Bit" "Not produced,TIOA6_0,TIOA6_1,TIOA6_2" bitfld.long 0x04 16.--17. " TIOA6S ,TIOA6 Input Select Bit" "TIOA6_0,TIOA6_0,TIOA6_1,TIOA6_2" textline " " bitfld.long 0x04 12.--13. " TIOB5S ,TIOB5 Input Select Bit" "TIOB5_0,TIOB5_0,TIOB5_1,TIOB5_2" bitfld.long 0x04 10.--11. " TIOA5E ,TIOA5E Output Select Bit" "Not produced,TIOA5_0,TIOA5_1,TIOA5_2" bitfld.long 0x04 8.--9. " TIOA5S ,TIOA5 Input Select Bit" "TIOA5_0,TIOA5_0,TIOA5_1,TIOA5_2" sif (cpuis("MB9?F?0?R")) textline " " bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,TIOB4_2" bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,TIOA4_2" elif (cpuis("MB9?F?0?N")) textline " " bitfld.long 0x04 4.--5. " TIOB4S ,TIOB4 Input Select Bit" "TIOB4_0,TIOB4_0,TIOB4_1,?..." bitfld.long 0x04 2.--3. " TIOA4E ,TIOA4E Output Select Bit" "Not produced,TIOA4_0,TIOA4_1,?..." endif line.long 0x8 "EPFR06,Extended Pin Function Setting Register 06" sif (cpuis("MB9?F?0?R")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" "INT15_0,INT15_0,INT15_1,INT15_2" bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" "INT14_0,INT14_0,INT14_1,INT14_2" bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" "INT13_0,INT13_0,INT13_1,INT13_2" textline " " bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" "INT12_0,INT12_0,INT12_1,INT12_2" bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" "INT11_0,INT11_0,INT11_1,INT11_2" bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" "INT10_0,INT10_0,INT10_1,INT10_2" textline " " bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" "INT09_0,INT09_0,INT09_1,INT09_2" textline " " elif (cpuis("MB9?F?0?N")) bitfld.long 0x08 30.--31. " EINT15S ,External Interrupt Input 15 Select Bit" "INT15_0,INT15_0,INT15_1,?..." bitfld.long 0x08 28.--29. " EINT14S ,External Interrupt Input 14 Select Bit" "INT14_0,INT14_0,INT14_1,?..." bitfld.long 0x08 26.--27. " EINT13S ,External Interrupt Input 13 Select Bit" "INT13_0,INT13_0,INT13_1,?..." textline " " bitfld.long 0x08 24.--25. " EINT12S ,External Interrupt Input 12 Select Bit" "INT12_0,INT12_0,INT12_1,?..." bitfld.long 0x08 22.--23. " EINT11S ,External Interrupt Input 11 Select Bit" "INT11_0,INT11_0,INT11_1,?..." bitfld.long 0x08 20.--21. " EINT10S ,External Interrupt Input 10 Select Bit" "INT10_0,INT10_0,INT10_1,?..." textline " " bitfld.long 0x08 18.--19. " EINT09S ,External Interrupt Input 9 Select Bit" "INT09_0,INT09_0,INT09_1,?..." textline " " endif bitfld.long 0x08 16.--17. " EINT08S ,External Interrupt Input 8 Select Bit" "INT08_0,INT08_0,INT08_1,INT08_2" bitfld.long 0x08 14.--15. " EINT07S ,External Interrupt Input 7 Select Bit" "INT07_0,INT07_0,INT07_1,INT07_2" bitfld.long 0x08 12.--13. " EINT06S ,External Interrupt Input 6 Select Bit" "INT06_0,INT06_0,INT06_1,INT06_2" textline " " bitfld.long 0x08 10.--11. " EINT05S ,External Interrupt Input 5 Select Bit" "INT05_0,INT05_0,INT05_1,INT05_2" bitfld.long 0x08 8.--9. " EINT04S ,External Interrupt Input 4 Select Bit" "INT04_0,INT04_0,INT04_1,INT04_2" bitfld.long 0x08 6.--7. " EINT03S ,External Interrupt Input 3 Select Bit" "INT03_0,INT03_0,INT03_1,INT03_2" textline " " sif (cpuis("MB9?F?0?R")) bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,INT02_2" bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,INT01_2" textline " " elif (cpuis("MB9?F?0?N")) bitfld.long 0x08 4.--5. " EINT02S ,External Interrupt Input 2 Select Bit" "INT02_0,INT02_0,INT02_1,?..." bitfld.long 0x08 2.--3. " EINT01S ,External Interrupt Input 1 Select Bit" "INT01_0,INT01_0,INT01_1,?..." textline " " endif bitfld.long 0x08 0.--1. " EINT00S ,External Interrupt Input 0 Select Bit" "INT00_0,INT00_0,INT00_1,INT00_2" line.long 0xC "EPFR07,Extended Pin Function Setting Register 07" sif (cpuis("MB9?F?0?R")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" "SCK3_0/Not produced,SCK3_0/SCK3_0,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" "SOT3_0/Not produced,SOT3_0/SOT3_0,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" "SIN3_0,SIN3_0,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" "SCK2_0/Not produced,SCK2_0/SCK2_0,SCK2_1/SCK2_1,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" "SOT2_0/Not produced,SOT2_0/SOT2_0,SOT2_1/SOT2_1,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" "SIN2_0,SIN2_0,SIN2_1,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" "SCK1_0/Not produced,SCK1_0/SCK1_0,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" "SOT1_0/Not produced,SOT1_0/SOT1_0,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" "SIN1_0,SIN1_0,SIN1_1,?..." textline " " elif (cpuis("MB9?F?0?N")) bitfld.long 0x0C 26.--27. " SCK3B ,SCK3 Input/Output Select Bit" ",,SCK3_1/SCK3_1,SCK3_2/SCK3_2" bitfld.long 0x0C 24.--25. " SOT3B ,SOT3B Input/Output Select Bit" ",,SOT3_1/SOT3_1,SOT3_2/SOT3_2" bitfld.long 0x0C 22.--23. " SIN3S ,SIN3S Input Select Bit" ",,SIN3_1,SIN3_2" textline " " bitfld.long 0x0C 20.--21. " SCK2B ,SCK2 Input/Output Select Bit" ",,,SCK2_2/SCK2_2" bitfld.long 0x0C 18.--19. " SOT2B ,SOT2B Input/Output Select Bit" ",,,SOT2_2/SOT2_2" bitfld.long 0x0C 16.--17. " SIN2S ,SIN2S Input Select Bit" ",,,SIN2_2" textline " " bitfld.long 0x0C 14.--15. " SCK1B ,SCK1 Input/Output Select Bit" ",,SCK1_1/SCK1_1,?..." bitfld.long 0x0C 12.--13. " SOT1B ,SOT1B Input/Output Select Bit" ",,SOT1_1/SOT1_1,?..." bitfld.long 0x0C 10.--11. " SIN1S ,SIN1S Input Select Bit" ",,SIN1_1,?..." textline " " endif bitfld.long 0x0C 8.--9. " SCK0B ,SCK0 Input/Output Select Bit" "SCK0_0/Not produced,SCK0_0/SCK0_0,SCK0_1/SCK0_1,?..." bitfld.long 0x0C 6.--7. " SOT0B ,SOT0B Input/Output Select Bit" "SOT0_0/Not produced,SOT0_0/SOT0_0,SOT0_1/SOT0_1,?..." bitfld.long 0x0C 4.--5. " SIN0S ,SIN0S Input Select Bit" "SIN0_0,SIN0_0,SIN0_1,?..." line.long 0x10 "EPFR08,Extended Pin Function Setting Register 08" sif (cpuis("MB9?F?0?R")) bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" "SCK7_0/Not produced,SCK7_0/SCK7_0,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" "SOT7_0/Not produced,SOT7_0/SOT7_0,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" "SIN7_0,SIN7_0,SIN7_1,SIN7_2" textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,SIN6_1,?..." textline " " bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,SCK5_1/SCK5_1,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,SOT5_1/SOT5_1,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,SIN5_1,SIN5_2" textline " " elif (cpuis("MB9?F?0?N")) bitfld.long 0x10 26.--27. " SCK7B ,SCK7 Input/Output Select Bit" ",,SCK7_1/SCK7_1,?..." bitfld.long 0x10 24.--25. " SOT7B ,SOT7B Input/Output Select Bit" ",,SOT7_1/SOT7_1,?..." bitfld.long 0x10 22.--23. " SIN7S ,SIN7S Input Select Bit" ",,SIN7_1,?..." textline " " bitfld.long 0x10 20.--21. " SCK6B ,SCK6 Input/Output Select Bit" "SCK6_0/Not produced,SCK6_0/SCK6_0,SCK6_1/SCK6_1,?..." bitfld.long 0x10 18.--19. " SOT6B ,SOT6B Input/Output Select Bit" "SOT6_0/Not produced,SOT6_0/SOT6_0,SOT6_1/SOT6_1,?..." bitfld.long 0x10 16.--17. " SIN6S ,SIN6S Input Select Bit" "SIN6_0,SIN6_0,SIN6_1,?..." textline " " bitfld.long 0x10 14.--15. " SCK5B ,SCK5 Input/Output Select Bit" "SCK5_0/Not produced,SCK5_0/SCK5_0,,SCK5_2/SCK5_2" bitfld.long 0x10 12.--13. " SOT5B ,SOT5B Input/Output Select Bit" "SOT5_0/Not produced,SOT5_0/SOT5_0,,SOT5_2/SOT5_2" bitfld.long 0x10 10.--11. " SIN5S ,SIN5S Input Select Bit" "SIN5_0,SIN5_0,SIN5_1,SIN5_2" textline " " endif bitfld.long 0x10 8.--9. " SCK4B ,SCK4 Input/Output Select Bit" "SCK4_0/Not produced,SCK4_0/SCK4_0,SCK4_1/SCK4_1,SCK4_2/SCK4_2" bitfld.long 0x10 6.--7. " SOT4B ,SOT4B Input/Output Select Bit" "SOT4_0/Not produced,SOT4_0/SOT4_0,SOT4_1/SOT4_1,SOT4_2/SOT4_2" bitfld.long 0x10 4.--5. " SIN4S ,SIN4S Input Select Bit" "SIN4_0,SIN4_0,SIN4_1,SIN4_2" textline " " bitfld.long 0x10 2.--3. " CTS4S ,CTS4S Input Select Bit" "CTS4_0,CTS4_0,CTS4_1,CTS4_2" bitfld.long 0x10 0.--1. " RTS4E ,RTS4E Output Select Bit" "Not produced,RTS4_0,RTS4_1,RTS4_2" line.long 0x14 "EPFR09,Extended Pin Function Setting Register 09" sif (cpuis("MB9?F?0?R")) bitfld.long 0x14 30.--31. " CTX1E ,Select output for CAN TX1" "Not produced,TX1_0,TX1_1,TX1_2" bitfld.long 0x14 28.--29. " CRX1S ,Select input for CAN RX1" "RX1_0,RX1_0,RX1_1,RX1_2" bitfld.long 0x14 26.--27. " CTX0E ,Select output for CAN TX0" "Not produced,TX0_0,TX0_1,TX0_2" textline " " bitfld.long 0x14 24.--25. " CRX0S ,Select input for CAN RX0" "RX0_0,RX0_0,RX0_1,RX0_2" bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." textline " " bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,ADTG_4,ADTG_5,ADTG_6,ADTG_7,ADTG_8,?..." textline " " elif (cpuis("MB9?F?0?N")) bitfld.long 0x14 30.--31. " CTX1E ,Select output for CAN TX1" ",,,TX1_2" bitfld.long 0x14 28.--29. " CRX1S ,Select input for CAN RX1" ",,,RX1_2" bitfld.long 0x14 26.--27. " CTX0E ,Select output for CAN TX0" ",,TX0_1,TX0_2" textline " " bitfld.long 0x14 24.--25. " CRX0S ,Select input for CAN RX0" ",,RX0_1,RX0_2" bitfld.long 0x14 20.--23. " ADTRG2S ,ADTRG2 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." bitfld.long 0x14 16.--19. " ADTRG1S ,ADTRG1 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." textline " " bitfld.long 0x14 12.--15. " ADTRG0S ,ADTRG0 Input Select Bit" "ADTG_0,ADTG_0,ADTG_1,ADTG_2,ADTG_3,,ADTG_5,ADTG_6,ADTG_7,?..." textline " " endif bitfld.long 0x14 10.--11. " QZIN1S ,Select input for QPRC ZIN1" ",,ZIN1_1,ZIN1_2" bitfld.long 0x14 8.--9. " QBIN1S ,Select input for QPRC BIN1" ",,BIN1_1,BIN1_2" textline " " bitfld.long 0x14 6.--7. " QAIN1S ,Select input for QPRC AIN1" ",,AIN1_1,AIN1_2" bitfld.long 0x14 4.--5. " QZIN0S ,Select input for QPRC ZIN0" "ZIN0_0,ZIN0_0,ZIN0_1,ZIN0_2" bitfld.long 0x14 2.--3. " QBIN0S ,Select input for QPRC BIN0" "BIN0_0,BIN0_0,BIN0_1,BIN0_2" textline " " bitfld.long 0x14 0.--1. " QAIN0S ,Select input for QPRC AIN0" "AIN0_0,AIN0_0,AIN0_1,AIN0_2" line.long 0x18 "EPFR10,Extended Pin Function Setting Register 10" bitfld.long 0x18 31. " UEA24E ,Selects output for external bus Adress24" "Not produced,Produced" bitfld.long 0x18 30. " UEA23E ,Selects output for external bus Adress23" "Not produced,Produced" bitfld.long 0x18 29. " UEA22E ,Selects output for external bus Adress22" "Not produced,Produced" textline " " bitfld.long 0x18 28. " UEA21E ,Selects output for external bus Adress21" "Not produced,Produced" bitfld.long 0x18 27. " UEA20E ,Selects output for external bus Adress20" "Not produced,Produced" bitfld.long 0x18 26. " UEA19E ,Selects output for external bus Adress19" "Not produced,Produced" textline " " bitfld.long 0x18 25. " UEA18E ,Selects output for external bus Adress18" "Not produced,Produced" bitfld.long 0x18 24. " UEA17E ,Selects output for external bus Adress17" "Not produced,Produced" bitfld.long 0x18 23. " UEA16E ,Selects output for external bus Adress16" "Not produced,Produced" textline " " bitfld.long 0x18 22. " UEA15E ,Selects output for external bus Adress15" "Not produced,Produced" bitfld.long 0x18 21. " UEA14E ,Selects output for external bus Adress14" "Not produced,Produced" bitfld.long 0x18 20. " UEA13E ,Selects output for external bus Adress13" "Not produced,Produced" textline " " bitfld.long 0x18 19. " UEA12E ,Selects output for external bus Adress12" "Not produced,Produced" bitfld.long 0x18 18. " UEA11E ,Selects output for external bus Adress11" "Not produced,Produced" bitfld.long 0x18 17. " UEA10E ,Selects output for external bus Adress10" "Not produced,Produced" textline " " bitfld.long 0x18 16. " UEA09E ,Selects output for external bus Adress09" "Not produced,Produced" bitfld.long 0x18 15. " UEA08E ,Selects output for external bus Adress08" "Not produced,Produced" bitfld.long 0x18 14. " UEA00E ,Selects output for external bus Adress00" "Not produced,Produced" textline " " bitfld.long 0x18 13. " UECS7E ,Selects output for external bus CS7" "Not produced,Produced" bitfld.long 0x18 12. " UECS6E ,Selects output for external bus CS6" "Not produced,Produced" bitfld.long 0x18 11. " UECS5E ,Selects output for external bus CS5" "Not produced,Produced" textline " " bitfld.long 0x18 10. " UECS4E ,Selects output for external bus CS4" "Not produced,Produced" bitfld.long 0x18 9. " UECS3E ,Selects output for external bus CS3" "Not produced,Produced" bitfld.long 0x18 8. " UECS2E ,Selects output for external bus CS2" "Not produced,Produced" textline " " bitfld.long 0x18 7. " UECS1E ,Selects output for external bus CS1" "Not produced,Produced" bitfld.long 0x18 6. " UEFLSE ,Selects output for external bus NAND-Flash control signal" "Not produced,Produced" bitfld.long 0x18 5. " UEOEXE ,Selects output for external bus OEX" "Not produced,Produced" textline " " bitfld.long 0x18 4. " UEDQME ,Selects output for external bus DQM" "Not produced,Produced" bitfld.long 0x18 3. " UEWEXE ,Selects output for external bus WEX" "Not produced,Produced" bitfld.long 0x18 2. " TESTB ,TESTB Test Bit" "No effect,Disabled" textline " " bitfld.long 0x18 1. " UEDTHB ,Selects input/output for external bus data" "Not produced,Produced" bitfld.long 0x18 0. " UEDEFB ,Selects input/output for external bus signal" "Not produced,Produced" tree.end tree "Special Port Setting Register" group.long 0x580++0x3 line.long 0x0 "SPSR,Special Port Setting Register" bitfld.long 0x00 4. " USB0C ,USB (ch.0) Pin Setting Register" "Not used,Used" bitfld.long 0x00 2. " MAINXC ,Main Clock (Oscillation) Pin Setting Register" "Not used,Used" bitfld.long 0x00 0. " SUBXC ,Sub Clock (Oscillation) Pin Setting Register" "Not used,Used" tree.end width 12. endif tree.end tree.open "Watchdog Timer" tree "Hardware Watchdog Timer" base ad:0x40011000 width 9. group.long 0x00++0x03 line.long 0x00 "WDG_LDR,Hardware Watchdog Timer Load Register" rgroup.long 0x04++0x03 line.long 0x00 "WDG_VLR,Hardware Watchdog Timer Value Register" group.byte 0x08++0x00 line.byte 0x00 "WDG_CTL,Hardware Watchdog Timer Control Register" bitfld.byte 0x00 1. " RESEN ,Hardware watchdog timer reset enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " INTEN ,Hardware watchdog interrupt and counter enable bit" "Disabled,Enabled" group.byte 0x0C++0x00 line.byte 0x00 "WDG_ICL,Hardware Watchdog Timer Clear Register" rgroup.byte 0x10++0x00 line.byte 0x00 "WDG_RIS,Hardware watchdog timer interrupt status register" bitfld.byte 0x00 0. " RIS ,Hardware watchdog interrupt status bit" "Not generated,Generated" group.long 0xC00++0x03 line.long 0x00 "WDG_LCK,Hardware Watchdog Timer Lock Register" width 0xb tree.end tree "Software Watchdog Timer" base ad:0x40012000 width 13. group.long 0x00++0x03 line.long 0x00 "WDOGLOAD,Software watchdog timer load register" rgroup.long 0x04++0x03 line.long 0x00 "WDOGVALUE,Software watchdog timer value register" group.byte 0x08++0x00 line.byte 0x00 "WDOGCONTROL,Software watchdog timer control register" bitfld.byte 0x00 1. " RESEN ,Reset enable bit of the software watchdog" "Disabled,Enabled" bitfld.byte 0x00 0. " INTEN ,Interrupt and counter enable bit of the software watchdog" "Disabled,Enabled" group.long 0x0C++0x03 line.long 0x00 "WDOGINTCLR,Software watchdog timer clear register" rgroup.byte 0x10++0x00 line.byte 0x00 "WDOGRIS,Software watchdog timer interrupt status register" bitfld.byte 0x00 0. " RIS ,Software watchdog interrupt status bit" "Not generated,Generated" group.long 0xC00++0x03 line.long 0x00 "WDOGLOCK,Software watchdog timer lock register" width 0xb tree.end tree.end sif (!cpuis("MB9AF13??")&&!cpuis("MB9AFA3??")&&!cpuis("MB9AFAA1L")&&!cpuis("MB9AFAA2L")&&!cpuis("MB9AFAA1M")&&!cpuis("MB9AFAA2M")&&!cpuis("MB9AFAA1N")&&!cpuis("MB9AFAA2N")&&!cpuis("MB9AF1A1L")&&!cpuis("MB9AF1A1M")&&!cpuis("MB9AF1A1N")&&!cpuis("MB9AF1A2L")&&!cpuis("MB9AF1A2M")&&!cpuis("MB9AF1A2N")) tree "Dual Timer Register" tree "Timer 1" base ad:0x40015000 width 15. group.long 0x00++0x03 line.long 0x00 "TIMER1LOAD,Load Register" rgroup.long 0x04++0x03 line.long 0x00 "TIMER1VALUE,Value Register" group.long 0x08++0x03 line.long 0x00 "TIMER1CONTROL,Control Register" bitfld.long 0x00 7. " TIMEREN ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " TIMERMODE ,Mode bit" "Free-running,Periodic" bitfld.long 0x00 5. " INTENABLE ,Interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " TIMERPRE ,Prescale bit" "/1,/16,/256,?..." bitfld.long 0x00 1. " TIMERSIZE ,Counter size bit" "16-bit,32-bit" bitfld.long 0x00 0. " ONESHOT ,One-shot mode bit" "Wrapping,One-shot" wgroup.long 0x0C++0x03 line.long 0x00 "TIMER1INTCLR,Interrupt Clear Register" rgroup.long 0x10++0x07 line.long 0x00 "TIMER1RIS,Interrupt Status Register" bitfld.long 0x00 0. " TIMER1RIS ,Interrupt Status Register bit" "Not generated,Generated" line.long 0x04 "TIMER1MIS,Masked Interrupt Status Register" bitfld.long 0x04 0. " TIMER1MIS ,Masked Interrupt Status bit" "Not generated,Generated" if (((d.l(ad:0x40015000+0x08))&0x40)==0x00)||(((d.l(ad:0x40015000+0x08))&0x01)==0x01) hgroup.long 0x18++0x03 hide.long 0x00 "TIMER1BGLOAD,Background Load Register" else group.long 0x18++0x03 line.long 0x00 "TIMER1BGLOAD,Background Load Register" endif width 0xb tree.end tree "Timer 2" base ad:0x40015020 width 15. group.long 0x00++0x03 line.long 0x00 "TIMER2LOAD,Load Register" rgroup.long 0x04++0x03 line.long 0x00 "TIMER2VALUE,Value Register" group.long 0x08++0x03 line.long 0x00 "TIMER2CONTROL,Control Register" bitfld.long 0x00 7. " TIMEREN ,Enable bit" "Disabled,Enabled" bitfld.long 0x00 6. " TIMERMODE ,Mode bit" "Free-running,Periodic" bitfld.long 0x00 5. " INTENABLE ,Interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--3. " TIMERPRE ,Prescale bit" "/1,/16,/256,?..." bitfld.long 0x00 1. " TIMERSIZE ,Counter size bit" "16-bit,32-bit" bitfld.long 0x00 0. " ONESHOT ,One-shot mode bit" "Wrapping,One-shot" wgroup.long 0x0C++0x03 line.long 0x00 "TIMER2INTCLR,Interrupt Clear Register" rgroup.long 0x10++0x07 line.long 0x00 "TIMER2RIS,Interrupt Status Register" bitfld.long 0x00 0. " TIMER2RIS ,Interrupt Status Register bit" "Not generated,Generated" line.long 0x04 "TIMER2MIS,Masked Interrupt Status Register" bitfld.long 0x04 0. " TIMER2MIS ,Masked Interrupt Status bit" "Not generated,Generated" if (((d.l(ad:0x40015020+0x08))&0x40)==0x00)||(((d.l(ad:0x40015020+0x08))&0x01)==0x01) hgroup.long 0x18++0x03 hide.long 0x00 "TIMER2BGLOAD,Background Load Register" else group.long 0x18++0x03 line.long 0x00 "TIMER2BGLOAD,Background Load Register" endif width 0xb tree.end tree.end endif sif (!cpuis("MB9AF131L")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF132L")&&!cpuis("MB9AF131N")&&!cpuis("MB9AF131M")&&!cpuis("MB9AF132N")&&!cpuis("MB9AF132M")&&!cpuis("MB9AF131K")&&!cpuis("MB9AFA31L")&&!cpuis("MB9AFA31M")&&!cpuis("MB9AFA31N")&&!cpuis("MB9AFA32L")&&!cpuis("MB9AFA32M")&&!cpuis("MB9AFA32N")&&!cpuis("MB9AF1A1L")&&!cpuis("MB9AF1A1M")&&!cpuis("MB9AF1A1N")&&!cpuis("MB9AF1A2L")&&!cpuis("MB9AF1A2M")&&!cpuis("MB9AF1A2N")&&!cpuis("MB9AFAA1L")&&!cpuis("MB9AFAA1M")&&!cpuis("MB9AFAA1N")&&!cpuis("MB9AFAA2L")&&!cpuis("MB9AFAA2M")&&!cpuis("MB9AFAA2N")&&!cpuis("MB9AF121K")&&!cpuis("MB9AF121L")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")&&!cpuis("MB9BF121J")) tree "Watch Counter" base ad:0x4003A000 width 9. if (((d.w(ad:0x4003A000+0x2))&0xC)==0x0) group.word 0x10++0x1 line.word 0x0 "CLK_SEL,Clock Selection Register" bitfld.word 0x00 8. " SEL_OUT ,Output clock selection bit" "2^12/FCL,2^22/FCL" bitfld.word 0x00 0. " SEL_IN ,Input clock selection bit" "Sub,Main" elif (((d.w(ad:0x4003A000+0x2))&0xC)==0x4) group.word 0x10++0x1 line.word 0x0 "CLK_SEL,Clock Selection Register" bitfld.word 0x00 8. " SEL_OUT ,Output clock selection bit" "2^13/FCL,2^23/FCL" bitfld.word 0x00 0. " SEL_IN ,Input clock selection bit" "Sub,Main" elif (((d.w(ad:0x4003A000+0x2))&0xC)==0x8) group.word 0x10++0x1 line.word 0x0 "CLK_SEL,Clock Selection Register" bitfld.word 0x00 8. " SEL_OUT ,Output clock selection bit" "2^14/FCL,2^24/FCL" bitfld.word 0x00 0. " SEL_IN ,Input clock selection bit" "Sub,Main" else group.word 0x10++0x1 line.word 0x0 "CLK_SEL,Clock Selection Register" bitfld.word 0x00 8. " SEL_OUT ,Output clock selection bit" "2^15/FCL,2^25/FCL" bitfld.word 0x00 0. " SEL_IN ,Input clock selection bit" "Sub,Main" endif group.byte 0x14++0x0 line.byte 0x0 "CLK_EN,Division Clock Enable Register" bitfld.byte 0x00 1. " CLK_EN_R ,Division clock enable read bit" "Stopped,Started" bitfld.byte 0x00 0. " CLK_EN ,Division clock enable bit" "Disabled,Enabled" rgroup.byte 0x0++0x0 line.byte 0x0 "WCRD,Watch Counter Read Register" bitfld.byte 0x00 0.--5. " CTR[5:0] ,Counter read bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1++0x0 line.byte 0x0 "WCRL,Watch Counter Reload Register" bitfld.byte 0x00 0.--5. " RLC[5:0] ,Counter reload value setting bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((d.l(ad:0x4003A000+0x02))&0x80)==0x00)&&(((d.l(ad:0x4003A000+0x02))&0x40)==0x00) group.byte 0x02++0x00 line.byte 0x0 "WCCR,Watch Counter Control Register" bitfld.byte 0x00 7. " WCEN ,Watch counter operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " WCOP ,Watch counter operating state flag" "Stopped,Active" bitfld.byte 0x00 2.--3. " CS[1:0] ,Count clock select bits" "WCCK0,WCCK1,WCCK2,WCCK3" bitfld.byte 0x00 1. " WCIE ,Interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " WCIF ,Interrupt request flag bit" "Cleared,No effect" else group.byte 0x02++0x00 line.byte 0x0 "WCCR,Watch Counter Control Register" bitfld.byte 0x00 7. " WCEN ,Watch counter operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " WCOP ,Watch counter operating state flag" "Stopped,Active" rbitfld.byte 0x00 2.--3. " CS[1:0] ,Count clock select bits" "WCCK0,WCCK1,WCCK2,WCCK3" bitfld.byte 0x00 1. " WCIE ,Interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " WCIF ,Interrupt request flag bit" "Cleared,No effect" endif width 12. tree.end endif sif (cpuis("MB9AF13?K")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF11?K")||cpuis("MB9AF31?K")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AF?3?L")||cpuis("MB9AF?3?M")||cpuis("MB9AF?3?N")||cpuis("MB9BF32??")||cpuis("MB9BF52??")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF12??")||cpuis("MB9AF?21K")||cpuis("MB9AF?21L")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9AFAA??")||cpuis("MB9AF1A??")) tree "RTC (Real Time Clock)" base ad:0x4003B000 width 10. tree "RTC Count Block" group.long 0x00++0x0b line.long 0x00 "WTCR1,Control Register 1" bitfld.long 0x00 31. " INTCRIE ,Year/month/date/hour/minute/second/day of the week counter value read completion interrupt enable" "Disabled,Enabled" bitfld.long 0x00 30. " INTERIE ,Time rewrite error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " INTALIE ,Alarm interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " INTTMIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " INTHIE ,1-hour interrupt enable" "Disabled,Enabled" bitfld.long 0x00 26. " INTMIE ,1-minute interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " INTSIE ,1-second interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " INTSSIE ,0.5-second interrupt enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTCRI ,Year/month/date/hour/minute/second/day of the week counter value read completion interrupt flag [read/write]" "No interrupt/Cleared,Interrupt/No Effect" bitfld.long 0x00 22. " INTERI ,Time rewrite error interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" bitfld.long 0x00 21. " INTALI ,Alarm interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" textline " " bitfld.long 0x00 20. " INTTMI ,Timer interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" bitfld.long 0x00 19. " INTHI ,1-hour interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" bitfld.long 0x00 18. " INTMI ,1-minute interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" textline " " bitfld.long 0x00 17. " INTSI ,1-second interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" bitfld.long 0x00 16. " INTSSI ,0.5-second interrupt flag" "No interrupt/Cleared,Interrupt/No Effect" textline " " bitfld.long 0x00 12. " YEN ,Alarm year register enable" "Disabled,Enabled" bitfld.long 0x00 11. " MOEN ,Alarm month register enable" "Disabled,Enabled" bitfld.long 0x00 10. " DEN ,Alarm date register enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HEN ,Alarm hour register enable" "Disabled,Enabled" bitfld.long 0x00 8. " MIEN ,Alarm minute register enable" "Disabled,Enabled" textline " " rbitfld.long 0x00 6. " BUSY ,Indicates that time rewriting is in process" "Idle,Busy" bitfld.long 0x00 5. " SCRST ,Sub second generation/1-second generation counter reset" "No reset,Reset" bitfld.long 0x00 4. " SCST ,1-second clock output stop" "No,Yes" textline " " bitfld.long 0x00 3. " SRST ,RTC reset bit" "Completed,Reset" rbitfld.long 0x00 2. " RUN ,RTC count block operation" "No operation,Operation" bitfld.long 0x00 0. " ST ,Operation start" "Stopped,Started" line.long 0x04 "WTCR2,Control Register 2" rbitfld.long 0x04 10. " TMRUN ,Timer counter operation" "No operation,Operation" bitfld.long 0x04 9. " TMEN ,Timer counter control" "Time elapse,Time intervals" textline " " bitfld.long 0x04 8. " TMST ,Timer counter start" "Stopped,Started" bitfld.long 0x04 0. " CREAD ,Year/month/date/hour/minute/second/day of the week counter value read control [read/write]" "Completed/No effect,In progress/Copied" line.long 0x08 "WTBR,Counter Cycle Setting Register" bitfld.long 0x08 23. " BR23 ,Counter cycle setting bit [23]" "0,1" bitfld.long 0x08 22. " BR22 ,Counter cycle setting bit [22]" "0,1" bitfld.long 0x08 21. " BR21 ,Counter cycle setting bit [21]" "0,1" bitfld.long 0x08 20. " BR20 ,Counter cycle setting bit [20]" "0,1" bitfld.long 0x08 19. " BR19 ,Counter cycle setting bit [19]" "0,1" bitfld.long 0x08 18. " BR18 ,Counter cycle setting bit [18]" "0,1" textline " " bitfld.long 0x08 17. " BR17 ,Counter cycle setting bit [17]" "0,1" bitfld.long 0x08 16. " BR16 ,Counter cycle setting bit [16]" "0,1" bitfld.long 0x08 15. " BR15 ,Counter cycle setting bit [15]" "0,1" bitfld.long 0x08 14. " BR14 ,Counter cycle setting bit [14]" "0,1" bitfld.long 0x08 13. " BR13 ,Counter cycle setting bit [13]" "0,1" bitfld.long 0x08 12. " BR12 ,Counter cycle setting bit [12]" "0,1" textline " " bitfld.long 0x08 11. " BR11 ,Counter cycle setting bit [11]" "0,1" bitfld.long 0x08 10. " BR10 ,Counter cycle setting bit [10]" "0,1" bitfld.long 0x08 9. " BR9 ,Counter cycle setting bit [9]" "0,1" bitfld.long 0x08 8. " BR8 ,Counter cycle setting bit [8]" "0,1" bitfld.long 0x08 7. " BR7 ,Counter cycle setting bit [7]" "0,1" bitfld.long 0x08 6. " BR6 ,Counter cycle setting bit [6]" "0,1" textline " " bitfld.long 0x08 5. " BR5 ,Counter cycle setting bit [5]" "0,1" bitfld.long 0x08 4. " BR4 ,Counter cycle setting bit [4]" "0,1" bitfld.long 0x08 3. " BR3 ,Counter cycle setting bit [3]" "0,1" bitfld.long 0x08 2. " BR2 ,Counter cycle setting bit [2]" "0,1" bitfld.long 0x08 1. " BR1 ,Counter cycle setting bit [1]" "0,1" bitfld.long 0x08 0. " BR0 ,Counter cycle setting bit [0]" "0,1" if ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x0f))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x0f))&0x3f)==0x00)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x0f))&0x30)==0x30)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x0f))&0x30)!=0x30)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x0f))&0x30)==0x30)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)==0x00)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x04||0x06||0x09||0x11))&&(((d.b(ad:0x4003B000+0x0f))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x0f))&0x3f)!=0x00)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x04||0x06||0x09||0x11))&&(((d.b(ad:0x4003B000+0x0f))&0x3f)==0x00)) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x11))&0x1f)==(0x04||0x06||0x09||0x11))&&((d.b(ad:0x4003B000+0x0f))&0x30)==0x30) group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the date" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..." else group.byte 0x0f++0x00 line.byte 0x00 "WTDR,Date Register" bitfld.byte 0x00 4.--5. " D ,Second digit of the date" "-,?..." bitfld.byte 0x00 0.--3. ",First digit of the date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if (((d.b(ad:0x4003B000+0x0e))&0x30)==(0x00||0x10)) group.byte 0x0e++0x00 line.byte 0x00 "WTHR,Hour Register" bitfld.byte 0x00 4.--5. " H ,Second digit of the hour" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the hour" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif (((d.b(ad:0x4003B000+0x0e))&0x30)==0x20) group.byte 0x0e++0x00 line.byte 0x00 "WTHR,Hour Register" bitfld.byte 0x00 4.--5. " H ,Second digit of the hour" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the hour" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..." else group.byte 0x0e++0x00 line.byte 0x00 "WTHR,Hour Register" bitfld.byte 0x00 4.--5. " H ,Second digit of the hour" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the hour" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif group.byte 0x0d++0x00 line.byte 0x00 "WTMIR,Minute Register" bitfld.byte 0x00 4.--6. " MI ,Second digit of the minute" "0,1,2,3,4,5,-,-" bitfld.byte 0x00 0.--3. ",First digit of the minute" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." group.byte 0x0c++0x00 line.byte 0x00 "WTSR,Second Register" bitfld.byte 0x00 4.--6. " S ,Second digit of the second" "0,1,2,3,4,5,-,-" bitfld.byte 0x00 0.--3. ",First digit of the second" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." group.byte 0x12++0x00 line.byte 0x00 "WTYR,Year Register" bitfld.byte 0x00 4.--7. " Y ,First digit of the year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.byte 0x00 0.--3. ",First digit of the year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." if (((d.b(ad:0x4003B000+0x11))&0x10)==0x00) group.byte 0x11++0x00 line.byte 0x00 "WTMOR,Month Register" bitfld.byte 0x00 4. " MO ,Second digit of the month" "0,1" bitfld.byte 0x00 0.--3. ",First digit of the month" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.byte 0x11++0x00 line.byte 0x00 "WTMOR,Month Register" bitfld.byte 0x00 4. " MO ,Second digit of the month" "0,1" bitfld.byte 0x00 0.--3. ",First digit of the month" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." endif group.byte 0x10++0x00 line.byte 0x00 "WTDW,Day of the Week Register" bitfld.byte 0x00 0.--2. " DW ,Day of the week" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-" if ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)==0x00)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x01||0x3||0x5||0x7||0x8||0x10||0x12))&&(((d.b(ad:0x4003B000+0x17))&0x30)==0x30)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x17))&0x3f)==0x00)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==0x02)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00)&&(((d.b(ad:0x4003B000+0x17))&0x30)==0x30)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x04||0x06||0x09||0x19))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)!=0x00)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x04||0x06||0x09||0x19))&&(((d.b(ad:0x4003B000+0x17))&0x30)!=0x30)&&(((d.b(ad:0x4003B000+0x17))&0x3f)==0x00)) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif ((((d.b(ad:0x4003B000+0x19))&0x1f)==(0x04||0x06||0x09||0x19))&&((d.b(ad:0x4003B000+0x17))&0x30)==0x30) group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "0,1,2,3" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "0,-,-,-,-,-,-,-,-,-,-,-,-,?..." else group.byte 0x17++0x00 line.byte 0x00 "ALDR,Alarm Date Register" bitfld.byte 0x00 4.--5. " AD ,Second digit of the alarm-set date" "-,?..." bitfld.byte 0x00 0.--3. ",First digit of the alarm-set date" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif if (((d.b(ad:0x4003B000+0x16))&0x30)==(0x00||0x10)) group.byte 0x16++0x00 line.byte 0x00 "ALHR,Alarm Hour Register" bitfld.byte 0x00 4.--5. " AH ,Second digit of the alarm-set hour" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set hour" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." elif (((d.b(ad:0x4003B000+0x16))&0x30)==0x20) group.byte 0x16++0x00 line.byte 0x00 "ALHR,Alarm Hour Register" bitfld.byte 0x00 4.--5. " AH ,Second digit of the alarm-set hour" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set hour" "0,1,2,3,-,-,-,-,-,-,-,-,-,?..." else group.byte 0x16++0x00 line.byte 0x00 "ALHR,Alarm Hour Register" bitfld.byte 0x00 4.--5. " AH ,Second digit of the alarm-set hour" "0,1,2,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set hour" "-,-,-,-,-,-,-,-,-,-,-,-,-,?..." endif group.byte 0x15++0x00 line.byte 0x00 "ALMIR,Alarm Minute Register" bitfld.byte 0x00 4.--6. " AMI ,Second digit of the alarm-set minute" "0,1,2,3,4,5,-,-" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set minute" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." group.byte 0x20++0x00 line.byte 0x00 "ALYR,Alarm Year Register" bitfld.byte 0x00 4.--7. " AY ,First digit of the alarm-set year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." bitfld.byte 0x00 0.--3. ",First digit of the alarm-set year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..." if (((d.b(ad:0x4003B000+0x19))&0x10)==0x00) group.byte 0x19++0x00 line.byte 0x00 "ALMOR,Alarm Month Register" bitfld.byte 0x00 4. " AMO ,Second digit of the alarm-set month" "0,1" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set month" "-,1,2,3,4,5,6,7,8,9,-,-,-,?..." else group.byte 0x19++0x00 line.byte 0x00 "ALMOR,Alarm Month Register" bitfld.byte 0x00 4. " AMO ,Second digit of the alarm-set month" "0,1" bitfld.byte 0x00 0.--3. ",First digit of the alarm-set month" "0,1,2,-,-,-,-,-,-,-,-,-,-,?..." endif group.long 0x1c++0x03 line.long 0x00 "WTTR,Timer Setting Register" bitfld.long 0x00 17. " TM17 ,Timer setting information bit [17]" "0,1" bitfld.long 0x00 16. " TM16 ,Timer setting information bit [16]" "0,1" textline " " bitfld.long 0x00 15. " TM15 ,Timer setting information bit [15]" "0,1" bitfld.long 0x00 14. " TM14 ,Timer setting information bit [14]" "0,1" textline " " bitfld.long 0x00 13. " TM13 ,Timer setting information bit [13]" "0,1" bitfld.long 0x00 12. " TM12 ,Timer setting information bit [12]" "0,1" textline " " bitfld.long 0x00 11. " TM11 ,Timer setting information bit [11]" "0,1" bitfld.long 0x00 10. " TM10 ,Timer setting information bit [10]" "0,1" textline " " bitfld.long 0x00 9. " TM9 ,Timer setting information bit [9]" "0,1" bitfld.long 0x00 8. " TM8 ,Timer setting information bit [8]" "0,1" textline " " bitfld.long 0x00 7. " TM7 ,Timer setting information bit [7]" "0,1" bitfld.long 0x00 6. " TM6 ,Timer setting information bit [6]" "0,1" textline " " bitfld.long 0x00 5. " TM5 ,Timer setting information bit [5]" "0,1" bitfld.long 0x00 4. " TM4 ,Timer setting information bit [4]" "0,1" textline " " bitfld.long 0x00 3. " TM3 ,Timer setting information bit [3]" "0,1" bitfld.long 0x00 2. " TM2 ,Timer setting information bit [2]" "0,1" textline " " bitfld.long 0x00 1. " TM1 ,Timer setting information bit [1]" "0,1" bitfld.long 0x00 0. " TM0 ,Timer setting information bit [0]" "0,1" tree.end tree "RTC Clock Control Block" group.byte 0x20++0x00 line.byte 0x00 "WTCLKS,Clock Selection Register" bitfld.byte 0x00 0. " WTCLKS ,Input clock select" "Sub clock,Main clock" rgroup.byte 0x21++0x00 line.byte 0x00 "WTCLKM,Selection Clock Status Register" bitfld.byte 0x00 0.--1. " WTCLKM ,Clock selection status" "Not operating,Not operating,Sub clock,Main clock" sif (cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AF?3?M")||cpuis("MB9AF?3?N")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9BF32??")||cpuis("MB9BF52??")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF12??")||cpuis("MB9AF?21K")||cpuis("MB9AF?21L")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9AFAA??")||cpuis("MB9AF1A??")) group.word 0x24++0x01 line.word 0x00 "WTCAL,Frequency Correction Value Setting Register" hexmask.word 0x00 0.--9. 1. " WTCAL ,Frequency correction value setting bits" group.byte 0x26++0x00 line.byte 0x00 "WTCALEN,Frequency Correction Enable Register" bitfld.byte 0x00 0. " WTCALEN ,Frequency correction enable" "Disabled,Enabled" else group.byte 0x24++0x01 line.byte 0x00 "WTCAL,Frequency Correction Value Setting Register" hexmask.byte 0x00 0.--6. 1. " WTCAL ,Frequency correction value setting bits" line.byte 0x01 "WTCALEN,Frequency Correction Enable Register" bitfld.byte 0x01 0. " WTCALEN ,Frequency correction enable" "Disabled,Enabled" endif group.byte 0x28++0x01 line.byte 0x00 "WTDIV,Divider Ratio Setting Register" bitfld.byte 0x00 0.--3. " WTDIV ,Divider ratio" "Not divided,/2,/4,/8,/16,/32,/64,/128,/256,/512,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.byte 0x01 "WTDIVEN,Divider Output Enable Register" rbitfld.byte 0x01 1. " WTDIVRDY ,Divider status" "No operation,Operation" bitfld.byte 0x01 0. " WTDIVEN ,Divider enable" "Disabled,Enabled" sif (cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AF?3?M")||cpuis("MB9AF?3?N")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9BF32??")||cpuis("MB9BF52??")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF12??")||cpuis("MB9AF?21K")||cpuis("MB9AF?21L")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9AFAA??")||cpuis("MB9AF1A??")) group.byte 0x2c++0x00 line.byte 0x00 "WTCALPRD,Frequency Correction Cycle Setting Register" hexmask.byte 0x00 0.--5. 1. " WTCALPRD ,Frequency correction value setting bits" group.byte 0x30++0x00 line.byte 0x00 "WTCOSEL,RTCCO Output Selection Register" bitfld.byte 0x00 0. " WTCOSEL ,RTCCO output select" "CO,CO/2" endif tree.end width 0xb tree.end endif tree "Base timer" sif (cpuis("MB9BF?1?S")||cpuis("MB9BF?1?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) base ad:0x40025000 width 6. tree "Channel 0" base ad:0x40025000+0x00 if (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 1" base ad:0x40025000+0x40 if (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 2" base ad:0x40025000+0x80 if (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 3" base ad:0x40025000+0xC0 if (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 4" base ad:0x40025000+0x200 if (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 5" base ad:0x40025000+0x240 if (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 6" base ad:0x40025000+0x280 if (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 7" base ad:0x40025000+0x2C0 if (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end width 11. tree "I/O select function" tree.end width 0xb base ad:0x40025400 width 6. tree "Channel 8" base ad:0x40025400+0x00 if (((d.w(ad:0x40025400+0x00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x00+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 9" base ad:0x40025400+0x40 if (((d.w(ad:0x40025400+0x40+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x40+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x40+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x40+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 10" base ad:0x40025400+0x80 if (((d.w(ad:0x40025400+0x80+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x80+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x80+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x80+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 11" base ad:0x40025400+0xC0 if (((d.w(ad:0x40025400+0xC0+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0xC0+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0xC0+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0xC0+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 12" base ad:0x40025400+0x200 if (((d.w(ad:0x40025400+0x200+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x200+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x200+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x200+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 13" base ad:0x40025400+0x240 if (((d.w(ad:0x40025400+0x240+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x240+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x240+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x240+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 14" base ad:0x40025400+0x280 if (((d.w(ad:0x40025400+0x280+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x280+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x280+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x280+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 15" base ad:0x40025400+0x2C0 if (((d.w(ad:0x40025400+0x2C0+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x2C0+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x2C0+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025400+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025400+0x2C0+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025400+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end width 11. tree "I/O select function" base ad:0x40025400-0x400 group.word 0x100++0x01 line.word 0x00 "BTSEL0123,I/O Select Register" bitfld.word 0x00 12.--15. " SEL23 ,I/O select bits for Ch.2/Ch.3" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." bitfld.word 0x00 8.--11. " SEL01 ,I/O select bits for Ch.0/Ch.1" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." group.word 0x300++0x01 line.word 0x00 "BTSEL4567,I/O Select Register" bitfld.word 0x00 12.--15. " SEL67 ,I/O select bits for Ch.6/Ch.7" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." bitfld.word 0x00 8.--11. " SEL45 ,I/O select bits for Ch.4/Ch.5" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." group.word 0x500++0x01 line.word 0x00 "BTSEL89AB,I/O Select Register" bitfld.word 0x00 12.--15. " SELAB ,I/O select bits for Ch.10/Ch.11" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." bitfld.word 0x00 8.--11. " SEL89 ,I/O select bits for Ch.8/Ch.9" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." group.word 0x700++0x01 line.word 0x00 "BTSELCDEF,I/O Select Register" bitfld.word 0x00 12.--15. " SELEF ,I/O select bits for Ch.14/Ch.15" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." bitfld.word 0x00 8.--11. " SELCD ,I/O select bits for Ch.12/Ch.13" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." wgroup.word 0xFFC++0x01 line.word 0x00 "BTSSSR,Software-based Simultaneous Startup Register" bitfld.word 0x00 15. " SSSR_[15] ,Software-based simultaneous startup bit" "Invalid,Start Ch.15" bitfld.word 0x00 14. " [14] ,Software-based simultaneous startup bit" "Invalid,Start Ch.14" bitfld.word 0x00 13. " [13] ,Software-based simultaneous startup bit" "Invalid,Start Ch.13" bitfld.word 0x00 12. " [12] ,Software-based simultaneous startup bit" "Invalid,Start Ch.12" bitfld.word 0x00 11. " [11] ,Software-based simultaneous startup bit" "Invalid,Start Ch.11" bitfld.word 0x00 10. " [10] ,Software-based simultaneous startup bit" "Invalid,Start Ch.10" textline " " bitfld.word 0x00 9. " [9] ,Software-based simultaneous startup bit" "Invalid,Start Ch.9" bitfld.word 0x00 8. " [8] ,Software-based simultaneous startup bit" "Invalid,Start Ch.8" bitfld.word 0x00 7. " [7] ,Software-based simultaneous startup bit" "Invalid,Start Ch.7" bitfld.word 0x00 6. " [6] ,Software-based simultaneous startup bit" "Invalid,Start Ch.6" bitfld.word 0x00 5. " [5] ,Software-based simultaneous startup bit" "Invalid,Start Ch.5" bitfld.word 0x00 4. " [4] ,Software-based simultaneous startup bit" "Invalid,Start Ch.4" textline " " bitfld.word 0x00 3. " [3] ,Software-based simultaneous startup bit" "Invalid,Start Ch.3" bitfld.word 0x00 2. " [2] ,Software-based simultaneous startup bit" "Invalid,Start Ch.2" bitfld.word 0x00 1. " [1] ,Software-based simultaneous startup bit" "Invalid,Start Ch.1" bitfld.word 0x00 0. " [0] ,Software-based simultaneous startup bit" "Invalid,Start Ch.0" tree.end width 0xb else base ad:0x40025000 width 6. tree "Channel 0" base ad:0x40025000+0x00 if (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x00+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x00+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 1" base ad:0x40025000+0x40 if (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x40+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x40+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 2" base ad:0x40025000+0x80 if (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x80+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x80+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 3" base ad:0x40025000+0xC0 if (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0xC0+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0xC0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 4" base ad:0x40025000+0x200 if (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x200+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x200+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 5" base ad:0x40025000+0x240 if (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x240+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x240+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 6" base ad:0x40025000+0x280 if (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x280+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x280+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end tree "Channel 7" base ad:0x40025000+0x2C0 if (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x10) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" group.word 0x04++0x01 line.word 0x00 "PDUT,PWM Duty Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " DTIE ,Duty match interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 1. " DTIR ,Duty match interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x20) group.word 0x00++0x01 line.word 0x00 "PRLL,LOW Width Reload Register" group.word 0x04++0x01 line.word 0x00 "PRLH,HIGH Width Reload Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 11. " RTGEN ,Restart enable bit" "Disabled,Enabled" bitfld.word 0x00 10. " PMSK ,Pulse output mask bit" "Normal,Fixed to LOW" textline " " bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" textline " " bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x30) group.word 0x00++0x01 line.word 0x00 "PCSR,PWM Cycle Set Register" rgroup.word 0x08++0x01 line.word 0x00 "TMR,Timer Register" if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,Ext clock(rising),Ext clock(falling),Ext clock(both)" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" bitfld.word 0x00 8.--9. " EGS ,Trigger input edge selection bits" "Disabled,Rising,Falling,Both" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 3. " OSEL ,Output polarity specification bit" "Normal,Inverted" bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Reload,One-shot" textline " " bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" bitfld.word 0x00 0. " STRG ,Software trigger bit" "Invalid,Triggered" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" bitfld.byte 0x00 6. " TGIE ,Trigger interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " UDIE ,Underflow interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TGIR ,Trigger interrupt request bit" "Cleared,Detected" textline " " bitfld.byte 0x00 0. " UDIR ,Underflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" elif (((d.w(ad:0x40025000+0x2C0+0x0C))&0x70)==0x40) hgroup.word 0x04++0x01 hide.word 0x00 "DTBF,Data Buffer Register" in if (((d.w(ad:0x40025000+0x2C0+0x11))&0x1)==0x0) group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/1,/4,/16,/128,/256,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 12.--14. " CKS ,Count clock for the 16-bit down counter" "/512,/1024,/2048,?..." bitfld.word 0x00 8.--10. " EGS ,Measurement edge selection bits" "High,Rising,Falling,All,Low,?..." bitfld.word 0x00 7. " T32 ,32-bit timer selection bit" "16-bit,32-bit" textline " " bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." bitfld.word 0x00 2. " MDSE ,Mode selection bit" "Continuous,One-shot" bitfld.word 0x00 1. " CTEN ,Operation enable bit" "Disabled,Enabled" endif group.byte 0x10++0x01 line.byte 0x00 "STC,Status Control Register" rbitfld.byte 0x00 7. " ERR ,Error flag bit" "Normal,Error" bitfld.byte 0x00 6. " EDIE ,Measurement completion interrupt request enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVIE ,Overflow interrupt request enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " EDIR ,Measurement completion interrupt request bit" "DTBF,Detected" bitfld.byte 0x00 0. " OVIR ,Overflow interrupt request bit" "Cleared,Detected" line.byte 0x01 "TMCR2,Timer Control Registers" bitfld.byte 0x01 0. " CKS3 ,Count clock selection bit" "Low,High" else group.word 0x0C++0x01 line.word 0x00 "TMCR,Timer Control Registers" bitfld.word 0x00 4.--6. " FMD ,Timer function selection bits" "Reset,PWM,PPG,Reload,PWC,?..." endif tree.end width 11. tree "I/O select function" base ad:0x40025000 group.word 0x100++0x01 line.word 0x00 "BTSEL0123,I/O Select Register" bitfld.word 0x00 12.--15. " SEL23 ,I/O select bits for Ch.2/Ch.3" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." bitfld.word 0x00 8.--11. " SEL01 ,I/O select bits for Ch.0/Ch.1" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." group.word 0x300++0x01 line.word 0x00 "BTSEL4567,I/O Select Register" bitfld.word 0x00 12.--15. " SEL67 ,I/O select bits for Ch.6/Ch.7" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." bitfld.word 0x00 8.--11. " SEL45 ,I/O select bits for Ch.4/Ch.5" "Mode 0,Mode 1,Mode 2,Mode 3,Mode 4,Mode 5,Mode 6,Mode 7,Mode 8,?..." wgroup.word 0xFFC++0x01 line.word 0x00 "BTSSSR,Software-based Simultaneous Startup Register" bitfld.word 0x00 7. " SSSR_[7] ,Software-based simultaneous startup bit" "Invalid,Start Ch.7" bitfld.word 0x00 6. " [6] ,Software-based simultaneous startup bit" "Invalid,Start Ch.6" bitfld.word 0x00 5. " [5] ,Software-based simultaneous startup bit" "Invalid,Start Ch.5" bitfld.word 0x00 4. " [4] ,Software-based simultaneous startup bit" "Invalid,Start Ch.4" textline " " bitfld.word 0x00 3. " [3] ,Software-based simultaneous startup bit" "Invalid,Start Ch.3" bitfld.word 0x00 2. " [2] ,Software-based simultaneous startup bit" "Invalid,Start Ch.2" bitfld.word 0x00 1. " [1] ,Software-based simultaneous startup bit" "Invalid,Start Ch.1" bitfld.word 0x00 0. " [0] ,Software-based simultaneous startup bit" "Invalid,Start Ch.0" tree.end width 0xb endif tree.end sif (!cpuis("MB9AF?4*")) tree.open "MFT (Multi-function Timer)" tree "Unit 0" base ad:0x40020000 width 7. tree "Free-run Timer Unit" group.word (0x28+0x8)++0x1 "Channel 0" line.word 0x0 "TCSA0,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x28+0xC)++0x1 line.word 0x0 "TCSB0,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x28++0x1 line.word 0x0 "TCCP0,FRT Cycle Setting Register" group.word (0x28+0x4)++0x1 line.word 0x0 "TCDT0,FRT Count Value Register" group.word (0x38+0x8)++0x1 "Channel 1" line.word 0x0 "TCSA1,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x38+0xC)++0x1 line.word 0x0 "TCSB1,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x38++0x1 line.word 0x0 "TCCP1,FRT Cycle Setting Register" group.word (0x38+0x4)++0x1 line.word 0x0 "TCDT1,FRT Count Value Register" group.word (0x48+0x8)++0x1 "Channel 2" line.word 0x0 "TCSA2,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x48+0xC)++0x1 line.word 0x0 "TCSB2,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x48++0x1 line.word 0x0 "TCCP2,FRT Cycle Setting Register" group.word (0x48+0x4)++0x1 line.word 0x0 "TCDT2,FRT Count Value Register" tree.end width 8. tree "Output Compare Unit" group.byte 0x58++0x0 "Channel 0/1" line.byte 0x0 "OCFS10,OCU Channel 0/1 Connecting FRT Select Register" sif ((cpuis("MB9AF11?K"))||(cpuis("MB9AF11?L"))||(cpuis("MB9AF13?K"))||(cpuis("MB9AF13?L"))||(cpuis("MB9AF13?M"))||(cpuis("MB9AF13?N"))||(cpuis("MB9AF31?K"))||(cpuis("MB9AF31?L"))||(cpuis("MB9AFA3?L"))||(cpuis("MB9AFA3?M"))||(cpuis("MB9AFA3?N"))) bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," elif (cpuis("MB9AF105?A")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9BF*")) bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," else bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," endif group.byte 0x18++0x1 line.byte 0x0 "OCSA10,OCU Channel 0/1 Control Register A" bitfld.byte 0x00 7. " IOP1 ,OCCP(1) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP0 ,OCCP(0) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE1 ,Enable IOP1 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE0 ,Enable IOP0 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS1 ,Enable buffer register function of OCCP(1)" "Yes,No" bitfld.byte 0x00 2. " BDIS0 ,Enable buffer register function of OCCP(0)" "Yes,No" bitfld.byte 0x00 1. " CST1 ,Operation state of OCU-ch(1)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST0 ,Operation state of OCU-ch(0)" "Disabled,Enabled" line.byte 0x1 "OCSB10,OCU Channel 0/1 Control Register B" bitfld.byte 0x01 6. " BTS1 ,Transfer timing form buffer to OCCP(1)" "Zero,Peak" bitfld.byte 0x01 5. " BTS0 ,Transfer timing form buffer to OCCP(0)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD1 ,Set output level on RT(1) output pin of OCU-ch.(1)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD0 ,Set output level on RT(0) output pin of OCU-ch.(0)" "Low,High" group.word 0x0++0x1 line.word 0x0 "OCCP0,OCU Channel 0 Compare Value Store Register" group.word 0x4++0x1 line.word 0x0 "OCCP1,OCU Channel 1 Compare Value Store Register" group.byte 0x59++0x0 "Channel 2/3" line.byte 0x0 "OCFS32,OCU Channel 2/3 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSO3[3:0] ,Connect FRT channel x to OCU channel 3" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO2[3:0] ,Connect FRT channel x to OCU channel 2" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x1C++0x1 line.byte 0x0 "OCSA32,OCU Channel 2/3 Control Register A" bitfld.byte 0x00 7. " IOP3 ,OCCP(3) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP2 ,OCCP(2) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE3 ,Enable IOP3 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE2 ,Enable IOP2 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS3 ,Enable buffer register function of OCCP(3)" "Yes,No" bitfld.byte 0x00 2. " BDIS2 ,Enable buffer register function of OCCP(2)" "Yes,No" bitfld.byte 0x00 1. " CST3 ,Operation state of OCU-ch(3)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST2 ,Operation state of OCU-ch(2)" "Disabled,Enabled" line.byte 0x1 "OCSB32,OCU Channel 2/3 Control Register B" bitfld.byte 0x01 6. " BTS3 ,Transfer timing form buffer to OCCP(3)" "Zero,Peak" bitfld.byte 0x01 5. " BTS2 ,Transfer timing form buffer to OCCP(2)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD3 ,Set output level on RT(3) output pin of OCU-ch.(3)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD2 ,Set output level on RT(2) output pin of OCU-ch.(2)" "Low,High" group.word 0x8++0x1 line.word 0x0 "OCCP2,OCU Channel 2 Compare Value Store Register" group.word 0xC++0x1 line.word 0x0 "OCCP3,OCU Channel 3 Compare Value Store Register" group.byte 0x5C++0x0 "Channel 4/5" line.byte 0x0 "OCFS54,OCU Channel 4/5 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSO5[3:0] ,Connect FRT channel x to OCU channel 5" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO4[3:0] ,Connect FRT channel x to OCU channel 4" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x20++0x1 line.byte 0x0 "OCSA54,OCU Channel 4/5 Control Register A" bitfld.byte 0x00 7. " IOP5 ,OCCP(5) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP4 ,OCCP(4) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE5 ,Enable IOP5 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE4 ,Enable IOP4 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS5 ,Enable buffer register function of OCCP(5)" "Yes,No" bitfld.byte 0x00 2. " BDIS4 ,Enable buffer register function of OCCP(4)" "Yes,No" bitfld.byte 0x00 1. " CST5 ,Operation state of OCU-ch(5)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST4 ,Operation state of OCU-ch(4)" "Disabled,Enabled" line.byte 0x1 "OCSB54,OCU Channel 4/5 Control Register B" bitfld.byte 0x01 6. " BTS5 ,Transfer timing form buffer to OCCP(5)" "Zero,Peak" bitfld.byte 0x01 5. " BTS4 ,Transfer timing form buffer to OCCP(4)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD5 ,Set output level on RT(5) output pin of OCU-ch.(5)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD4 ,Set output level on RT(4) output pin of OCU-ch.(4)" "Low,High" group.word 0x10++0x1 line.word 0x0 "OCCP4,OCU Channel 4 Compare Value Store Register" group.word 0x14++0x1 line.word 0x0 "OCCP5,OCU Channel 5 Compare Value Store Register" group.byte 0x25++0x0 "Control Register C" line.byte 0x0 "OCSC,OCU Control Register C" bitfld.byte 0x00 5. " MOD5 ,Determines the operation mode of OCU ch.5" "0,1" bitfld.byte 0x00 4. " MOD4 ,Determines the operation mode of OCU ch.4" "0,1" bitfld.byte 0x00 3. " MOD3 ,Determines the operation mode of OCU ch.3" "0,1" bitfld.byte 0x00 2. " MOD2 ,Determines the operation mode of OCU ch.2" "0,1" textline " " bitfld.byte 0x00 1. " MOD1 ,Determines the operation mode of OCU ch.1" "0,1" bitfld.byte 0x00 0. " MOD0 ,Determines the operation mode of OCU ch.0" "0,1" tree.end tree "Waveform Generator Unit" if (((d.w(ad:0x40020000+0x8C))&0x38)==0x0) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x8C))&0x38)==0x8) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x8C))&0x38)==0x10) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x8C))&0x38)==0x20) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x8C))&0x38)==0x38) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x80++0x1 line.word 0x0 "WFTM10,WFG Channel 0/1 Timer Value Register" if (((d.w(ad:0x40020000+0x90))&0x38)==0x0) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x90))&0x38)==0x8) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x90))&0x38)==0x10) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x90))&0x38)==0x20) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x90))&0x38)==0x38) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x84++0x1 line.word 0x0 "WFTM32,WFG Channel 2/3 Timer Value Register" if (((d.w(ad:0x40020000+0x94))&0x38)==0x0) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x94))&0x38)==0x8) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x94))&0x38)==0x10) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x94))&0x38)==0x20) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40020000+0x94))&0x38)==0x38) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x88++0x1 line.word 0x0 "WFTM54,WFG Channel 4/5 Timer Value Register" group.word 0x98++0x1 "Interrupt Control Register" line.word 0x0 "WFIR,WFG Interrupt Control Register" bitfld.word 0x00 15. " TMIS54 ,Stop the WFG54 timer" "No effect,Stop" bitfld.word 0x00 14. " TMIE54 ,Start the WFG54 timer" "Not started,Started" bitfld.word 0x00 13. " TMIC54 ,Clear WFG54timer interrupt" "No effect,Clear" rbitfld.word 0x00 12. " TMIF54 ,Check the state of WFG54 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 11. " TMIS32 ,Stop the WFG32 timer" "No effect,Stop" bitfld.word 0x00 10. " TMIE32 ,Start the WFG32 timer" "Not started,Started" bitfld.word 0x00 9. " TMIC32 ,Clear WFG32 timer interrupt" "No effect,Clear" rbitfld.word 0x00 8. " TMIF32 ,Check the state of WFG32 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TMIS10 ,Stop the WFG10 timer" "No effect,Stop" bitfld.word 0x00 6. " TMIE10 ,Start the WFG10 timer" "Not started,Started" bitfld.word 0x00 5. " TMIC10 ,Clear WFG10 timer interrupt" "No effect,Clear" rbitfld.word 0x00 4. " TMIF10 ,Check the state of WFG10 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " DTIC ,Clear WFIR.DTIF" "No effect,Clear" rbitfld.word 0x00 0. " DTIF ,Check the state of DTIF interrupt" "No interrupt,Interrupt" tree.end width 6. tree "Noise Canceller Unit" group.word 0x9C++0x1 line.word 0x0 "NZCL,NZCL Control Register" bitfld.word 0x00 4. " SDTI ,DTIF interrupt" "No effect,Force interrupt" bitfld.word 0x00 1.--3. " NWS[2:0] ,Noise-cancelling width" "Disabled,4*PCLK,8*PCLK,16*PCLK,32*PCLK,?..." bitfld.word 0x00 0. " DTIE ,Generate DTIF interrupt by signal input from the DTTIX pin" "Ignore,Generate" tree.end width 8. tree "Input Capture Unit" group.byte 0x60++0x1 "Channel 0/1" line.byte 0x0 "ICFS10,ICU Channel 0/1 Connecting FRT Select Register" sif ((cpuis("MB9AF11?K"))||(cpuis("MB9AF11?L"))||(cpuis("MB9AF13?K"))||(cpuis("MB9AF13?L"))||(cpuis("MB9AF13?M"))||(cpuis("MB9AF13?N"))||(cpuis("MB9AF31?K"))||(cpuis("MB9AF31?L"))||(cpuis("MB9AFA3?L"))||(cpuis("MB9AFA3?M"))||(cpuis("MB9AFA3?N"))) bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," elif (cpuis("MB9AF105?A")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9BF*")) bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," else bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," endif rgroup.byte 0x78++0x0 line.byte 0x0 "ICSA10,ICU Channel 0/1 Control Register A" bitfld.byte 0x00 7. " ICP1 ,Valid edge interrupt for ICU-ch.(1) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 6. " ICP0 ,Valid edge interrupt for ICU-ch.(0) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 5. " ICE1 ,Enable ICSA.ICP1 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " ICE0 ,Enable ICSA.ICP0 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " EG1[1:0] ,Enable operations of ICU-ch.(1) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" bitfld.byte 0x00 0.--1. " EG0[1:0] ,Enable operations of ICU-ch.(0) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" rgroup.byte 0x79++0x00 line.byte 0x00 "ICSB10,ICU Channel 0/1 Control Register B" bitfld.byte 0x00 1. " IEI1 ,Latest valid edge of ICU-ch.(1)" "Falling edge,Rising edge" bitfld.byte 0x00 0. " IEI0 ,Latest valid edge of ICU-ch.(0)" "Falling edge,Rising edge" rgroup.word 0x68++0x1 line.word 0x0 "ICCP0,ICU Channel 0 Capture value store register" rgroup.word 0x6C++0x1 line.word 0x0 "ICCP1,ICU Channel 1 Capture value store register" group.byte 0x61++0x1 "Channel 2/3" line.byte 0x0 "ICFS32,ICU Channel 2/3 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 2" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 3" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x7C++0x0 line.byte 0x0 "ICSA32,ICU Channel 2/3 Control Register A" bitfld.byte 0x00 7. " ICP3 ,Valid edge interrupt for ICU-ch.(3) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 6. " ICP2 ,Valid edge interrupt for ICU-ch.(2) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 5. " ICE3 ,Enable ICSA.ICP3 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " ICE2 ,Enable ICSA.ICP2 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " EG3[1:0] ,Enable operations of ICU-ch.(3) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" bitfld.byte 0x00 0.--1. " EG2[1:0] ,Enable operations of ICU-ch.(2) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" rgroup.byte 0x7D++0x00 line.byte 0x00 "ICSB32,ICU Channel 2/3 Control Register B" bitfld.byte 0x00 1. " IEI3 ,Latest valid edge of ICU-ch.(3)" "Falling edge,Rising edge" bitfld.byte 0x00 0. " IEI2 ,Latest valid edge of ICU-ch.(2)" "Falling edge,Rising edge" rgroup.word 0x70++0x1 line.word 0x0 "ICCP2,ICU Channel 2 Capture value store register" rgroup.word 0x74++0x1 line.word 0x0 "ICCP3,ICU Channel 3 Capture value store register" tree.end width 9. tree "ADC Start Compare Unit" group.word 0xBC++0x1 line.word 0x0 "ACSA,ADCMP Control Register A" bitfld.word 0x00 12.--13. " SEL2[1:0] ,Select FRT count state for AD conversion on channel 2" "Up/Peak/Down-count match ACCP2,Up-count match ACCP2,Peak/Down-count match ACCP2,Up-count match ACCP2 or Peak/Down-count match ACCPDN2" textline " " bitfld.word 0x00 10.--11. " SEL1[1:0] ,Select FRT count state for AD conversion on channel 1" "Up/Peak/Down-count match ACCP1,Up-count match ACCP1,Peak/Down-count match ACCP1,Up-count match ACCP1 or Peak/Down-count match ACCPDN1" textline " " bitfld.word 0x00 8.--9. " SEL0[1:0] ,Select FRT count state for AD conversion on channel 0" "Up/Peak/Down-count match ACCP0,Up-count match ACCP0,Peak/Down-count match ACCP0,Up-count match ACCP0 or Peak/Down-count match ACCPDN0" textline " " bitfld.word 0x00 4.--5. " CE2[1:0] ,Enable ADCMP channel 2 respectively / selects which FRT connected to channel 2" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" bitfld.word 0x00 2.--3. " CE1[1:0] ,Enable ADCMP channel 1 respectively / selects FRT connected to channel 1" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" bitfld.word 0x00 0.--1. " CE0[1:0] ,Enable ADCMP channel 0 respectively / selects FRT connected to channel 0" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" group.byte 0xB8++0x0 line.byte 0x0 "ACSB,ADCMP Control Register B" bitfld.byte 0x00 6. " BTS2 ,Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon..." "Zero,Peak" bitfld.byte 0x00 5. " BTS1 ,Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon..." "Zero,Peak" bitfld.byte 0x00 4. " BTS0 ,Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon..." "Zero,Peak" textline " " bitfld.byte 0x00 2. " BDIS2 ,Enable ACCP2 and ACCPDN2" "Yes,No" bitfld.byte 0x00 1. " BDIS1 ,Enable ACCP1 and ACCPDN1" "Yes,No" bitfld.byte 0x00 0. " BDIS0 ,Enable ACCP02 and ACCPDN0" "Yes,No" group.word 0xA0++0x1 "Channel 0" line.word 0x0 "ACCP0,ADCMP Compare Value Store Register" group.word (0xA0+0x4)++0x1 line.word 0x0 "ACCPDN0,ADCMP Compare Value Store Register, Down-count Direction Only" group.word 0xA8++0x1 "Channel 1" line.word 0x0 "ACCP1,ADCMP Compare Value Store Register" group.word (0xA8+0x4)++0x1 line.word 0x0 "ACCPDN1,ADCMP Compare Value Store Register, Down-count Direction Only" group.word 0xB0++0x1 "Channel 2" line.word 0x0 "ACCP2,ADCMP Compare Value Store Register" group.word (0xB0+0x4)++0x1 line.word 0x0 "ACCPDN2,ADCMP Compare Value Store Register, Down-count Direction Only" tree.end width 6. tree "ADC Start Trigger Selector Unit" group.word 0xC0++0x1 line.word 0x0 "ATSA,ADC Start Trigger Select Register" bitfld.word 0x00 12.--13. " AD2P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 2" "Start signal,OR signal,?..." bitfld.word 0x00 10.--11. " AD1P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 1" "Start signal,OR signal,?..." bitfld.word 0x00 8.--9. " AD0P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 0" "Start signal,OR signal,?..." textline " " bitfld.word 0x00 4.--5. " AD2S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 2" "Start signal,OR signal,?..." bitfld.word 0x00 2.--3. " AD1S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 1" "Start signal,OR signal,?..." bitfld.word 0x00 0.--1. " AD0S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 0" "Start signal,OR signal,?..." tree.end width 12. tree.end sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))&&(!cpuis("MB9BF32?S"))&&(!cpuis("MB9BF32?T"))&&(!cpuis("MB9BF52?S"))&&(!cpuis("MB9BF52?T"))&&(!cpuis("MB9BF42?S"))&&(!cpuis("MB9BF42?T"))&&(!cpuis("MB9BF12?S"))&&(!cpuis("MB9BF12?T"))) tree "Unit 1" base ad:0x40021000 width 7. tree "Free-run Timer Unit" group.word (0x28+0x8)++0x1 "Channel 0" line.word 0x0 "TCSA0,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x28+0xC)++0x1 line.word 0x0 "TCSB0,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x28++0x1 line.word 0x0 "TCCP0,FRT Cycle Setting Register" group.word (0x28+0x4)++0x1 line.word 0x0 "TCDT0,FRT Count Value Register" group.word (0x38+0x8)++0x1 "Channel 1" line.word 0x0 "TCSA1,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x38+0xC)++0x1 line.word 0x0 "TCSB1,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x38++0x1 line.word 0x0 "TCCP1,FRT Cycle Setting Register" group.word (0x38+0x4)++0x1 line.word 0x0 "TCDT1,FRT Count Value Register" group.word (0x48+0x8)++0x1 "Channel 2" line.word 0x0 "TCSA2,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x48+0xC)++0x1 line.word 0x0 "TCSB2,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x48++0x1 line.word 0x0 "TCCP2,FRT Cycle Setting Register" group.word (0x48+0x4)++0x1 line.word 0x0 "TCDT2,FRT Count Value Register" tree.end width 8. tree "Output Compare Unit" group.byte 0x58++0x0 "Channel 0/1" line.byte 0x0 "OCFS10,OCU Channel 0/1 Connecting FRT Select Register" sif ((cpuis("MB9AF11?K"))||(cpuis("MB9AF11?L"))||(cpuis("MB9AF13?K"))||(cpuis("MB9AF13?L"))||(cpuis("MB9AF13?M"))||(cpuis("MB9AF13?N"))||(cpuis("MB9AF31?K"))||(cpuis("MB9AF31?L"))||(cpuis("MB9AFA3?L"))||(cpuis("MB9AFA3?M"))||(cpuis("MB9AFA3?N"))) bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," elif (cpuis("MB9AF105?A")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9BF*")) bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," else bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," endif group.byte 0x18++0x1 line.byte 0x0 "OCSA10,OCU Channel 0/1 Control Register A" bitfld.byte 0x00 7. " IOP1 ,OCCP(1) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP0 ,OCCP(0) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE1 ,Enable IOP1 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE0 ,Enable IOP0 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS1 ,Enable buffer register function of OCCP(1)" "Yes,No" bitfld.byte 0x00 2. " BDIS0 ,Enable buffer register function of OCCP(0)" "Yes,No" bitfld.byte 0x00 1. " CST1 ,Operation state of OCU-ch(1)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST0 ,Operation state of OCU-ch(0)" "Disabled,Enabled" line.byte 0x1 "OCSB10,OCU Channel 0/1 Control Register B" bitfld.byte 0x01 6. " BTS1 ,Transfer timing form buffer to OCCP(1)" "Zero,Peak" bitfld.byte 0x01 5. " BTS0 ,Transfer timing form buffer to OCCP(0)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD1 ,Set output level on RT(1) output pin of OCU-ch.(1)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD0 ,Set output level on RT(0) output pin of OCU-ch.(0)" "Low,High" group.word 0x0++0x1 line.word 0x0 "OCCP0,OCU Channel 0 Compare Value Store Register" group.word 0x4++0x1 line.word 0x0 "OCCP1,OCU Channel 1 Compare Value Store Register" group.byte 0x59++0x0 "Channel 2/3" line.byte 0x0 "OCFS32,OCU Channel 2/3 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSO3[3:0] ,Connect FRT channel x to OCU channel 3" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO2[3:0] ,Connect FRT channel x to OCU channel 2" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x1C++0x1 line.byte 0x0 "OCSA32,OCU Channel 2/3 Control Register A" bitfld.byte 0x00 7. " IOP3 ,OCCP(3) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP2 ,OCCP(2) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE3 ,Enable IOP3 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE2 ,Enable IOP2 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS3 ,Enable buffer register function of OCCP(3)" "Yes,No" bitfld.byte 0x00 2. " BDIS2 ,Enable buffer register function of OCCP(2)" "Yes,No" bitfld.byte 0x00 1. " CST3 ,Operation state of OCU-ch(3)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST2 ,Operation state of OCU-ch(2)" "Disabled,Enabled" line.byte 0x1 "OCSB32,OCU Channel 2/3 Control Register B" bitfld.byte 0x01 6. " BTS3 ,Transfer timing form buffer to OCCP(3)" "Zero,Peak" bitfld.byte 0x01 5. " BTS2 ,Transfer timing form buffer to OCCP(2)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD3 ,Set output level on RT(3) output pin of OCU-ch.(3)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD2 ,Set output level on RT(2) output pin of OCU-ch.(2)" "Low,High" group.word 0x8++0x1 line.word 0x0 "OCCP2,OCU Channel 2 Compare Value Store Register" group.word 0xC++0x1 line.word 0x0 "OCCP3,OCU Channel 3 Compare Value Store Register" group.byte 0x5C++0x0 "Channel 4/5" line.byte 0x0 "OCFS54,OCU Channel 4/5 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSO5[3:0] ,Connect FRT channel x to OCU channel 5" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO4[3:0] ,Connect FRT channel x to OCU channel 4" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x20++0x1 line.byte 0x0 "OCSA54,OCU Channel 4/5 Control Register A" bitfld.byte 0x00 7. " IOP5 ,OCCP(5) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP4 ,OCCP(4) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE5 ,Enable IOP5 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE4 ,Enable IOP4 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS5 ,Enable buffer register function of OCCP(5)" "Yes,No" bitfld.byte 0x00 2. " BDIS4 ,Enable buffer register function of OCCP(4)" "Yes,No" bitfld.byte 0x00 1. " CST5 ,Operation state of OCU-ch(5)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST4 ,Operation state of OCU-ch(4)" "Disabled,Enabled" line.byte 0x1 "OCSB54,OCU Channel 4/5 Control Register B" bitfld.byte 0x01 6. " BTS5 ,Transfer timing form buffer to OCCP(5)" "Zero,Peak" bitfld.byte 0x01 5. " BTS4 ,Transfer timing form buffer to OCCP(4)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD5 ,Set output level on RT(5) output pin of OCU-ch.(5)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD4 ,Set output level on RT(4) output pin of OCU-ch.(4)" "Low,High" group.word 0x10++0x1 line.word 0x0 "OCCP4,OCU Channel 4 Compare Value Store Register" group.word 0x14++0x1 line.word 0x0 "OCCP5,OCU Channel 5 Compare Value Store Register" group.byte 0x25++0x0 "Control Register C" line.byte 0x0 "OCSC,OCU Control Register C" bitfld.byte 0x00 5. " MOD5 ,Determines the operation mode of OCU ch.5" "0,1" bitfld.byte 0x00 4. " MOD4 ,Determines the operation mode of OCU ch.4" "0,1" bitfld.byte 0x00 3. " MOD3 ,Determines the operation mode of OCU ch.3" "0,1" bitfld.byte 0x00 2. " MOD2 ,Determines the operation mode of OCU ch.2" "0,1" textline " " bitfld.byte 0x00 1. " MOD1 ,Determines the operation mode of OCU ch.1" "0,1" bitfld.byte 0x00 0. " MOD0 ,Determines the operation mode of OCU ch.0" "0,1" tree.end tree "Waveform Generator Unit" if (((d.w(ad:0x40021000+0x8C))&0x38)==0x0) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x8C))&0x38)==0x8) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x8C))&0x38)==0x10) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x8C))&0x38)==0x20) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x8C))&0x38)==0x38) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x80++0x1 line.word 0x0 "WFTM10,WFG Channel 0/1 Timer Value Register" if (((d.w(ad:0x40021000+0x90))&0x38)==0x0) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x90))&0x38)==0x8) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x90))&0x38)==0x10) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x90))&0x38)==0x20) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x90))&0x38)==0x38) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x84++0x1 line.word 0x0 "WFTM32,WFG Channel 2/3 Timer Value Register" if (((d.w(ad:0x40021000+0x94))&0x38)==0x0) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x94))&0x38)==0x8) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x94))&0x38)==0x10) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x94))&0x38)==0x20) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40021000+0x94))&0x38)==0x38) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE8,GATE10,GATE12,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x88++0x1 line.word 0x0 "WFTM54,WFG Channel 4/5 Timer Value Register" group.word 0x98++0x1 "Interrupt Control Register" line.word 0x0 "WFIR,WFG Interrupt Control Register" bitfld.word 0x00 15. " TMIS54 ,Stop the WFG54 timer" "No effect,Stop" bitfld.word 0x00 14. " TMIE54 ,Start the WFG54 timer" "Not started,Started" bitfld.word 0x00 13. " TMIC54 ,Clear WFG54timer interrupt" "No effect,Clear" rbitfld.word 0x00 12. " TMIF54 ,Check the state of WFG54 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 11. " TMIS32 ,Stop the WFG32 timer" "No effect,Stop" bitfld.word 0x00 10. " TMIE32 ,Start the WFG32 timer" "Not started,Started" bitfld.word 0x00 9. " TMIC32 ,Clear WFG32 timer interrupt" "No effect,Clear" rbitfld.word 0x00 8. " TMIF32 ,Check the state of WFG32 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TMIS10 ,Stop the WFG10 timer" "No effect,Stop" bitfld.word 0x00 6. " TMIE10 ,Start the WFG10 timer" "Not started,Started" bitfld.word 0x00 5. " TMIC10 ,Clear WFG10 timer interrupt" "No effect,Clear" rbitfld.word 0x00 4. " TMIF10 ,Check the state of WFG10 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " DTIC ,Clear WFIR.DTIF" "No effect,Clear" rbitfld.word 0x00 0. " DTIF ,Check the state of DTIF interrupt" "No interrupt,Interrupt" tree.end width 6. tree "Noise Canceller Unit" group.word 0x9C++0x1 line.word 0x0 "NZCL,NZCL Control Register" bitfld.word 0x00 4. " SDTI ,DTIF interrupt" "No effect,Force interrupt" bitfld.word 0x00 1.--3. " NWS[2:0] ,Noise-cancelling width" "Disabled,4*PCLK,8*PCLK,16*PCLK,32*PCLK,?..." bitfld.word 0x00 0. " DTIE ,Generate DTIF interrupt by signal input from the DTTIX pin" "Ignore,Generate" tree.end width 8. tree "Input Capture Unit" group.byte 0x60++0x1 "Channel 0/1" line.byte 0x0 "ICFS10,ICU Channel 0/1 Connecting FRT Select Register" sif ((cpuis("MB9AF11?K"))||(cpuis("MB9AF11?L"))||(cpuis("MB9AF13?K"))||(cpuis("MB9AF13?L"))||(cpuis("MB9AF13?M"))||(cpuis("MB9AF13?N"))||(cpuis("MB9AF31?K"))||(cpuis("MB9AF31?L"))||(cpuis("MB9AFA3?L"))||(cpuis("MB9AFA3?M"))||(cpuis("MB9AFA3?N"))) bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," elif (cpuis("MB9AF105?A")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9BF*")) bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," else bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," endif rgroup.byte 0x78++0x0 line.byte 0x0 "ICSA10,ICU Channel 0/1 Control Register A" bitfld.byte 0x00 7. " ICP1 ,Valid edge interrupt for ICU-ch.(1) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 6. " ICP0 ,Valid edge interrupt for ICU-ch.(0) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 5. " ICE1 ,Enable ICSA.ICP1 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " ICE0 ,Enable ICSA.ICP0 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " EG1[1:0] ,Enable operations of ICU-ch.(1) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" bitfld.byte 0x00 0.--1. " EG0[1:0] ,Enable operations of ICU-ch.(0) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" rgroup.byte 0x79++0x00 line.byte 0x00 "ICSB10,ICU Channel 0/1 Control Register B" bitfld.byte 0x00 1. " IEI1 ,Latest valid edge of ICU-ch.(1)" "Falling edge,Rising edge" bitfld.byte 0x00 0. " IEI0 ,Latest valid edge of ICU-ch.(0)" "Falling edge,Rising edge" rgroup.word 0x68++0x1 line.word 0x0 "ICCP0,ICU Channel 0 Capture value store register" rgroup.word 0x6C++0x1 line.word 0x0 "ICCP1,ICU Channel 1 Capture value store register" group.byte 0x61++0x1 "Channel 2/3" line.byte 0x0 "ICFS32,ICU Channel 2/3 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 2" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 3" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x7C++0x0 line.byte 0x0 "ICSA32,ICU Channel 2/3 Control Register A" bitfld.byte 0x00 7. " ICP3 ,Valid edge interrupt for ICU-ch.(3) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 6. " ICP2 ,Valid edge interrupt for ICU-ch.(2) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 5. " ICE3 ,Enable ICSA.ICP3 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " ICE2 ,Enable ICSA.ICP2 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " EG3[1:0] ,Enable operations of ICU-ch.(3) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" bitfld.byte 0x00 0.--1. " EG2[1:0] ,Enable operations of ICU-ch.(2) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" rgroup.byte 0x7D++0x00 line.byte 0x00 "ICSB32,ICU Channel 2/3 Control Register B" bitfld.byte 0x00 1. " IEI3 ,Latest valid edge of ICU-ch.(3)" "Falling edge,Rising edge" bitfld.byte 0x00 0. " IEI2 ,Latest valid edge of ICU-ch.(2)" "Falling edge,Rising edge" rgroup.word 0x70++0x1 line.word 0x0 "ICCP2,ICU Channel 2 Capture value store register" rgroup.word 0x74++0x1 line.word 0x0 "ICCP3,ICU Channel 3 Capture value store register" tree.end width 9. tree "ADC Start Compare Unit" group.word 0xBC++0x1 line.word 0x0 "ACSA,ADCMP Control Register A" bitfld.word 0x00 12.--13. " SEL2[1:0] ,Select FRT count state for AD conversion on channel 2" "Up/Peak/Down-count match ACCP2,Up-count match ACCP2,Peak/Down-count match ACCP2,Up-count match ACCP2 or Peak/Down-count match ACCPDN2" textline " " bitfld.word 0x00 10.--11. " SEL1[1:0] ,Select FRT count state for AD conversion on channel 1" "Up/Peak/Down-count match ACCP1,Up-count match ACCP1,Peak/Down-count match ACCP1,Up-count match ACCP1 or Peak/Down-count match ACCPDN1" textline " " bitfld.word 0x00 8.--9. " SEL0[1:0] ,Select FRT count state for AD conversion on channel 0" "Up/Peak/Down-count match ACCP0,Up-count match ACCP0,Peak/Down-count match ACCP0,Up-count match ACCP0 or Peak/Down-count match ACCPDN0" textline " " bitfld.word 0x00 4.--5. " CE2[1:0] ,Enable ADCMP channel 2 respectively / selects which FRT connected to channel 2" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" bitfld.word 0x00 2.--3. " CE1[1:0] ,Enable ADCMP channel 1 respectively / selects FRT connected to channel 1" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" bitfld.word 0x00 0.--1. " CE0[1:0] ,Enable ADCMP channel 0 respectively / selects FRT connected to channel 0" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" group.byte 0xB8++0x0 line.byte 0x0 "ACSB,ADCMP Control Register B" bitfld.byte 0x00 6. " BTS2 ,Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon..." "Zero,Peak" bitfld.byte 0x00 5. " BTS1 ,Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon..." "Zero,Peak" bitfld.byte 0x00 4. " BTS0 ,Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon..." "Zero,Peak" textline " " bitfld.byte 0x00 2. " BDIS2 ,Enable ACCP2 and ACCPDN2" "Yes,No" bitfld.byte 0x00 1. " BDIS1 ,Enable ACCP1 and ACCPDN1" "Yes,No" bitfld.byte 0x00 0. " BDIS0 ,Enable ACCP02 and ACCPDN0" "Yes,No" group.word 0xA0++0x1 "Channel 0" line.word 0x0 "ACCP0,ADCMP Compare Value Store Register" group.word (0xA0+0x4)++0x1 line.word 0x0 "ACCPDN0,ADCMP Compare Value Store Register, Down-count Direction Only" group.word 0xA8++0x1 "Channel 1" line.word 0x0 "ACCP1,ADCMP Compare Value Store Register" group.word (0xA8+0x4)++0x1 line.word 0x0 "ACCPDN1,ADCMP Compare Value Store Register, Down-count Direction Only" group.word 0xB0++0x1 "Channel 2" line.word 0x0 "ACCP2,ADCMP Compare Value Store Register" group.word (0xB0+0x4)++0x1 line.word 0x0 "ACCPDN2,ADCMP Compare Value Store Register, Down-count Direction Only" tree.end width 6. tree "ADC Start Trigger Selector Unit" group.word 0xC0++0x1 line.word 0x0 "ATSA,ADC Start Trigger Select Register" bitfld.word 0x00 12.--13. " AD2P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 2" "Start signal,OR signal,?..." bitfld.word 0x00 10.--11. " AD1P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 1" "Start signal,OR signal,?..." bitfld.word 0x00 8.--9. " AD0P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 0" "Start signal,OR signal,?..." textline " " bitfld.word 0x00 4.--5. " AD2S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 2" "Start signal,OR signal,?..." bitfld.word 0x00 2.--3. " AD1S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 1" "Start signal,OR signal,?..." bitfld.word 0x00 0.--1. " AD0S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 0" "Start signal,OR signal,?..." tree.end width 12. tree.end endif sif (cpuis("MB9BF*")) sif (!cpuis("MB9BF32?S")&&!cpuis("MB9BF32?T")&&!cpuis("MB9BF52?S")&&!cpuis("MB9BF52?T")&&!cpuis("MB9BF42?S")&&!cpuis("MB9BF42?T")&&!cpuis("MB9BF12?S")&&!cpuis("MB9BF12?T")) tree "Unit 2" base ad:0x40022000 width 7. tree "Free-run Timer Unit" group.word (0x28+0x8)++0x1 "Channel 0" line.word 0x0 "TCSA0,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x28+0xC)++0x1 line.word 0x0 "TCSB0,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x28++0x1 line.word 0x0 "TCCP0,FRT Cycle Setting Register" group.word (0x28+0x4)++0x1 line.word 0x0 "TCDT0,FRT Count Value Register" group.word (0x38+0x8)++0x1 "Channel 1" line.word 0x0 "TCSA1,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x38+0xC)++0x1 line.word 0x0 "TCSB1,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x38++0x1 line.word 0x0 "TCCP1,FRT Cycle Setting Register" group.word (0x38+0x4)++0x1 line.word 0x0 "TCDT1,FRT Count Value Register" group.word (0x48+0x8)++0x1 "Channel 2" line.word 0x0 "TCSA2,FRT Control Register A" bitfld.word 0x00 15. " ECKE ,Count clock select" "PCLK,FRCK" bitfld.word 0x00 14. " IRQZF ,Zero value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.word 0x00 13. " IRQZE ,Enable IRQZF interrupt" "Disabled,Enabled" bitfld.word 0x00 9. " ICLR ,TCCP value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/Interrupt" textline " " bitfld.word 0x00 8. " ICRE ,Enable ICLR interrupt" "Disabled,Enabled" bitfld.word 0x00 7. " BFE ,Enable TCCP buffer" "Disabled,Enabled" bitfld.word 0x00 6. " STOP ,Start and stop control" "Start,Stop" bitfld.word 0x00 5. " MODE ,Select FRT count mode" "Up-count,Up/Down-count" textline " " bitfld.word 0x00 4. " SCLR ,FRT operation state initialization request" "Cancel,Issue" bitfld.word 0x00 0.--3. " CLK[3:0] ,Sets the count clock cycle of FRT counter" "PCLK,PCLK*2,PCLK*4,PCLK*8,PCLK*16,PCLK*32,PCLK*64,PCLK*128,PCLK*256,?..." group.word (0x48+0xC)++0x1 line.word 0x0 "TCSB2,FRT Control Register B" bitfld.word 0x00 2. " AD2E ,Output AD conversion start signal to ADC unit 2" "Don't output,Output" bitfld.word 0x00 1. " AD1E ,Output AD conversion start signal to ADC unit 1" "Don't output,Output" bitfld.word 0x00 0. " AD0E ,Output AD conversion start signal to ADC unit 0" "Don't output,Output" group.word 0x48++0x1 line.word 0x0 "TCCP2,FRT Cycle Setting Register" group.word (0x48+0x4)++0x1 line.word 0x0 "TCDT2,FRT Count Value Register" tree.end width 8. tree "Output Compare Unit" group.byte 0x58++0x0 "Channel 0/1" line.byte 0x0 "OCFS10,OCU Channel 0/1 Connecting FRT Select Register" sif ((cpuis("MB9AF11?K"))||(cpuis("MB9AF11?L"))||(cpuis("MB9AF13?K"))||(cpuis("MB9AF13?L"))||(cpuis("MB9AF13?M"))||(cpuis("MB9AF13?N"))||(cpuis("MB9AF31?K"))||(cpuis("MB9AF31?L"))||(cpuis("MB9AFA3?L"))||(cpuis("MB9AFA3?M"))||(cpuis("MB9AFA3?N"))) bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," elif (cpuis("MB9AF105?A")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9BF*")) bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," else bitfld.byte 0x00 4.--7. " FSO1[3:0] ,Connect FRT channel x to OCU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO0[3:0] ,Connect FRT channel x to OCU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," endif group.byte 0x18++0x1 line.byte 0x0 "OCSA10,OCU Channel 0/1 Control Register A" bitfld.byte 0x00 7. " IOP1 ,OCCP(1) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP0 ,OCCP(0) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE1 ,Enable IOP1 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE0 ,Enable IOP0 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS1 ,Enable buffer register function of OCCP(1)" "Yes,No" bitfld.byte 0x00 2. " BDIS0 ,Enable buffer register function of OCCP(0)" "Yes,No" bitfld.byte 0x00 1. " CST1 ,Operation state of OCU-ch(1)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST0 ,Operation state of OCU-ch(0)" "Disabled,Enabled" line.byte 0x1 "OCSB10,OCU Channel 0/1 Control Register B" bitfld.byte 0x01 6. " BTS1 ,Transfer timing form buffer to OCCP(1)" "Zero,Peak" bitfld.byte 0x01 5. " BTS0 ,Transfer timing form buffer to OCCP(0)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD1 ,Set output level on RT(1) output pin of OCU-ch.(1)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD0 ,Set output level on RT(0) output pin of OCU-ch.(0)" "Low,High" group.word 0x0++0x1 line.word 0x0 "OCCP0,OCU Channel 0 Compare Value Store Register" group.word 0x4++0x1 line.word 0x0 "OCCP1,OCU Channel 1 Compare Value Store Register" group.byte 0x59++0x0 "Channel 2/3" line.byte 0x0 "OCFS32,OCU Channel 2/3 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSO3[3:0] ,Connect FRT channel x to OCU channel 3" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO2[3:0] ,Connect FRT channel x to OCU channel 2" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x1C++0x1 line.byte 0x0 "OCSA32,OCU Channel 2/3 Control Register A" bitfld.byte 0x00 7. " IOP3 ,OCCP(3) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP2 ,OCCP(2) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE3 ,Enable IOP3 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE2 ,Enable IOP2 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS3 ,Enable buffer register function of OCCP(3)" "Yes,No" bitfld.byte 0x00 2. " BDIS2 ,Enable buffer register function of OCCP(2)" "Yes,No" bitfld.byte 0x00 1. " CST3 ,Operation state of OCU-ch(3)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST2 ,Operation state of OCU-ch(2)" "Disabled,Enabled" line.byte 0x1 "OCSB32,OCU Channel 2/3 Control Register B" bitfld.byte 0x01 6. " BTS3 ,Transfer timing form buffer to OCCP(3)" "Zero,Peak" bitfld.byte 0x01 5. " BTS2 ,Transfer timing form buffer to OCCP(2)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD3 ,Set output level on RT(3) output pin of OCU-ch.(3)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD2 ,Set output level on RT(2) output pin of OCU-ch.(2)" "Low,High" group.word 0x8++0x1 line.word 0x0 "OCCP2,OCU Channel 2 Compare Value Store Register" group.word 0xC++0x1 line.word 0x0 "OCCP3,OCU Channel 3 Compare Value Store Register" group.byte 0x5C++0x0 "Channel 4/5" line.byte 0x0 "OCFS54,OCU Channel 4/5 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSO5[3:0] ,Connect FRT channel x to OCU channel 5" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSO4[3:0] ,Connect FRT channel x to OCU channel 4" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x20++0x1 line.byte 0x0 "OCSA54,OCU Channel 4/5 Control Register A" bitfld.byte 0x00 7. " IOP5 ,OCCP(5) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 6. " IOP4 ,OCCP(4) value detection on FRT interrupt (write/read)" "Clear/No interrupt,No effect/interrupt" bitfld.byte 0x00 5. " IOE5 ,Enable IOP5 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " IOE4 ,Enable IOP4 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " BDIS5 ,Enable buffer register function of OCCP(5)" "Yes,No" bitfld.byte 0x00 2. " BDIS4 ,Enable buffer register function of OCCP(4)" "Yes,No" bitfld.byte 0x00 1. " CST5 ,Operation state of OCU-ch(5)" "Disabled,Enabled" bitfld.byte 0x00 0. " CST4 ,Operation state of OCU-ch(4)" "Disabled,Enabled" line.byte 0x1 "OCSB54,OCU Channel 4/5 Control Register B" bitfld.byte 0x01 6. " BTS5 ,Transfer timing form buffer to OCCP(5)" "Zero,Peak" bitfld.byte 0x01 5. " BTS4 ,Transfer timing form buffer to OCCP(4)" "Zero,Peak" bitfld.byte 0x01 4. " CMOD ,OCU operation mode" "0,1" bitfld.byte 0x01 1. " OTD5 ,Set output level on RT(5) output pin of OCU-ch.(5)" "Low,High" textline " " bitfld.byte 0x01 0. " OTD4 ,Set output level on RT(4) output pin of OCU-ch.(4)" "Low,High" group.word 0x10++0x1 line.word 0x0 "OCCP4,OCU Channel 4 Compare Value Store Register" group.word 0x14++0x1 line.word 0x0 "OCCP5,OCU Channel 5 Compare Value Store Register" group.byte 0x25++0x0 "Control Register C" line.byte 0x0 "OCSC,OCU Control Register C" bitfld.byte 0x00 5. " MOD5 ,Determines the operation mode of OCU ch.5" "0,1" bitfld.byte 0x00 4. " MOD4 ,Determines the operation mode of OCU ch.4" "0,1" bitfld.byte 0x00 3. " MOD3 ,Determines the operation mode of OCU ch.3" "0,1" bitfld.byte 0x00 2. " MOD2 ,Determines the operation mode of OCU ch.2" "0,1" textline " " bitfld.byte 0x00 1. " MOD1 ,Determines the operation mode of OCU ch.1" "0,1" bitfld.byte 0x00 0. " MOD0 ,Determines the operation mode of OCU ch.0" "0,1" tree.end tree "Waveform Generator Unit" if (((d.w(ad:0x40022000+0x8C))&0x38)==0x0) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x8C))&0x38)==0x8) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x8C))&0x38)==0x10) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x8C))&0x38)==0x20) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x8C))&0x38)==0x38) group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x8C++0x1 "Channel 0/1" line.word 0x0 "WFSA10,WFG Channel 0/1 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x80++0x1 line.word 0x0 "WFTM10,WFG Channel 0/1 Timer Value Register" if (((d.w(ad:0x40022000+0x90))&0x38)==0x0) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x90))&0x38)==0x8) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x90))&0x38)==0x10) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x90))&0x38)==0x20) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x90))&0x38)==0x38) group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x90++0x1 "Channel 2/3" line.word 0x0 "WFSA32,WFG Channel 2/3 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x84++0x1 line.word 0x0 "WFTM32,WFG Channel 2/3 Timer Value Register" if (((d.w(ad:0x40022000+0x94))&0x38)==0x0) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,CH_PPG,Not reflected,CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x94))&0x38)==0x8) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Not reflected,Low/CH_PPG,Not reflected,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x94))&0x38)==0x10) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,Flag0,Flag1,High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x94))&0x38)==0x20) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" textline " " bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." elif (((d.w(ad:0x40022000+0x94))&0x38)==0x38) group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE16,GATE18,GATE20,?..." textline " " bitfld.word 0x00 6.--7. " GTEN[1:0] ,Select the output condition of the CH_GATE for each channel of WFG" "Low,RT(0),RT(1),High/Low" textline " " bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." else group.word 0x94++0x1 "Channel 4/5" line.word 0x0 "WFSA54,WFG Channel 4/5 Control Register A" bitfld.word 0x00 12. " DMOD ,Polarity of non-overlap signal" "High active,Low active" bitfld.word 0x00 10.--11. " PGEN[1:0] ,How to reflect the CH_PPG signal that is input to each channel of WFG on WFG output" "Low/High,Low/CH_PPG,Low/High,Low/CH_PPG" textline " " bitfld.word 0x00 8.--9. " PSEL[1:0] ,Select the PPG timer unit to be used at each channel of WFG" "GATE0,GATE2,GATE4,?..." bitfld.word 0x00 3.--5. " TMD[2:0] ,Selects WFG operation mode" "Through,RT-PPG,Timer- PPG,,RT dead timer,,,PPG dead timer" bitfld.word 0x00 0.--2. " DCK[2:0] ,Set the count clock cycle of the WFG timer" "PLCK,PLCK/2,PLCK/4,PLCK/8,PLCK/16,PLCK/32,PLCK/64,?..." endif group.word 0x88++0x1 line.word 0x0 "WFTM54,WFG Channel 4/5 Timer Value Register" group.word 0x98++0x1 "Interrupt Control Register" line.word 0x0 "WFIR,WFG Interrupt Control Register" bitfld.word 0x00 15. " TMIS54 ,Stop the WFG54 timer" "No effect,Stop" bitfld.word 0x00 14. " TMIE54 ,Start the WFG54 timer" "Not started,Started" bitfld.word 0x00 13. " TMIC54 ,Clear WFG54timer interrupt" "No effect,Clear" rbitfld.word 0x00 12. " TMIF54 ,Check the state of WFG54 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 11. " TMIS32 ,Stop the WFG32 timer" "No effect,Stop" bitfld.word 0x00 10. " TMIE32 ,Start the WFG32 timer" "Not started,Started" bitfld.word 0x00 9. " TMIC32 ,Clear WFG32 timer interrupt" "No effect,Clear" rbitfld.word 0x00 8. " TMIF32 ,Check the state of WFG32 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 7. " TMIS10 ,Stop the WFG10 timer" "No effect,Stop" bitfld.word 0x00 6. " TMIE10 ,Start the WFG10 timer" "Not started,Started" bitfld.word 0x00 5. " TMIC10 ,Clear WFG10 timer interrupt" "No effect,Clear" rbitfld.word 0x00 4. " TMIF10 ,Check the state of WFG10 timer interrupt" "No interrupt,Interrupt" textline " " bitfld.word 0x00 1. " DTIC ,Clear WFIR.DTIF" "No effect,Clear" rbitfld.word 0x00 0. " DTIF ,Check the state of DTIF interrupt" "No interrupt,Interrupt" tree.end width 6. tree "Noise Canceller Unit" group.word 0x9C++0x1 line.word 0x0 "NZCL,NZCL Control Register" bitfld.word 0x00 4. " SDTI ,DTIF interrupt" "No effect,Force interrupt" bitfld.word 0x00 1.--3. " NWS[2:0] ,Noise-cancelling width" "Disabled,4*PCLK,8*PCLK,16*PCLK,32*PCLK,?..." bitfld.word 0x00 0. " DTIE ,Generate DTIF interrupt by signal input from the DTTIX pin" "Ignore,Generate" tree.end width 8. tree "Input Capture Unit" group.byte 0x60++0x1 "Channel 0/1" line.byte 0x0 "ICFS10,ICU Channel 0/1 Connecting FRT Select Register" sif ((cpuis("MB9AF11?K"))||(cpuis("MB9AF11?L"))||(cpuis("MB9AF13?K"))||(cpuis("MB9AF13?L"))||(cpuis("MB9AF13?M"))||(cpuis("MB9AF13?N"))||(cpuis("MB9AF31?K"))||(cpuis("MB9AF31?L"))||(cpuis("MB9AFA3?L"))||(cpuis("MB9AFA3?M"))||(cpuis("MB9AFA3?N"))) bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,,,,,,,,,,,,," elif (cpuis("MB9AF105?A")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9BF*")) bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,External FRT,,,,,,,,,,," else bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 1" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 0" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," endif rgroup.byte 0x78++0x0 line.byte 0x0 "ICSA10,ICU Channel 0/1 Control Register A" bitfld.byte 0x00 7. " ICP1 ,Valid edge interrupt for ICU-ch.(1) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 6. " ICP0 ,Valid edge interrupt for ICU-ch.(0) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 5. " ICE1 ,Enable ICSA.ICP1 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " ICE0 ,Enable ICSA.ICP0 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " EG1[1:0] ,Enable operations of ICU-ch.(1) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" bitfld.byte 0x00 0.--1. " EG0[1:0] ,Enable operations of ICU-ch.(0) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" rgroup.byte 0x79++0x00 line.byte 0x00 "ICSB10,ICU Channel 0/1 Control Register B" bitfld.byte 0x00 1. " IEI1 ,Latest valid edge of ICU-ch.(1)" "Falling edge,Rising edge" bitfld.byte 0x00 0. " IEI0 ,Latest valid edge of ICU-ch.(0)" "Falling edge,Rising edge" rgroup.word 0x68++0x1 line.word 0x0 "ICCP0,ICU Channel 0 Capture value store register" rgroup.word 0x6C++0x1 line.word 0x0 "ICCP1,ICU Channel 1 Capture value store register" group.byte 0x61++0x1 "Channel 2/3" line.byte 0x0 "ICFS32,ICU Channel 2/3 Connecting FRT Select Register" bitfld.byte 0x00 4.--7. " FSI1[3:0] ,Connect FRT channel x to ICU channel 2" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," bitfld.byte 0x00 0.--3. " FSI0[3:0] ,Connect FRT channel x to ICU channel 3" "FRT ch.0,FRT ch.1,FRT ch.2,External FRT,,,,,,,,,,,," group.byte 0x7C++0x0 line.byte 0x0 "ICSA32,ICU Channel 2/3 Control Register A" bitfld.byte 0x00 7. " ICP3 ,Valid edge interrupt for ICU-ch.(3) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 6. " ICP2 ,Valid edge interrupt for ICU-ch.(2) (write/read)" "Clear/No interrupt,No effect/Interrupt" bitfld.byte 0x00 5. " ICE3 ,Enable ICSA.ICP3 interrupt" "Disabled,Enabled" bitfld.byte 0x00 4. " ICE2 ,Enable ICSA.ICP2 interrupt" "Disabled,Enabled" textline " " bitfld.byte 0x00 2.--3. " EG3[1:0] ,Enable operations of ICU-ch.(3) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" bitfld.byte 0x00 0.--1. " EG2[1:0] ,Enable operations of ICU-ch.(2) and selects a valid edge(s)" "Disabled/Ignore input,Enabled/Rising edge,Enabled/Falling edge,Enabled/Both edges" rgroup.byte 0x7D++0x00 line.byte 0x00 "ICSB32,ICU Channel 2/3 Control Register B" bitfld.byte 0x00 1. " IEI3 ,Latest valid edge of ICU-ch.(3)" "Falling edge,Rising edge" bitfld.byte 0x00 0. " IEI2 ,Latest valid edge of ICU-ch.(2)" "Falling edge,Rising edge" rgroup.word 0x70++0x1 line.word 0x0 "ICCP2,ICU Channel 2 Capture value store register" rgroup.word 0x74++0x1 line.word 0x0 "ICCP3,ICU Channel 3 Capture value store register" tree.end width 9. tree "ADC Start Compare Unit" group.word 0xBC++0x1 line.word 0x0 "ACSA,ADCMP Control Register A" bitfld.word 0x00 12.--13. " SEL2[1:0] ,Select FRT count state for AD conversion on channel 2" "Up/Peak/Down-count match ACCP2,Up-count match ACCP2,Peak/Down-count match ACCP2,Up-count match ACCP2 or Peak/Down-count match ACCPDN2" textline " " bitfld.word 0x00 10.--11. " SEL1[1:0] ,Select FRT count state for AD conversion on channel 1" "Up/Peak/Down-count match ACCP1,Up-count match ACCP1,Peak/Down-count match ACCP1,Up-count match ACCP1 or Peak/Down-count match ACCPDN1" textline " " bitfld.word 0x00 8.--9. " SEL0[1:0] ,Select FRT count state for AD conversion on channel 0" "Up/Peak/Down-count match ACCP0,Up-count match ACCP0,Peak/Down-count match ACCP0,Up-count match ACCP0 or Peak/Down-count match ACCPDN0" textline " " bitfld.word 0x00 4.--5. " CE2[1:0] ,Enable ADCMP channel 2 respectively / selects which FRT connected to channel 2" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" bitfld.word 0x00 2.--3. " CE1[1:0] ,Enable ADCMP channel 1 respectively / selects FRT connected to channel 1" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" bitfld.word 0x00 0.--1. " CE0[1:0] ,Enable ADCMP channel 0 respectively / selects FRT connected to channel 0" "Disabled,Enabled/FRT(0),Enabled/FRT(1),Enabled/FRT(2)" group.byte 0xB8++0x0 line.byte 0x0 "ACSB,ADCMP Control Register B" bitfld.byte 0x00 6. " BTS2 ,Performs buffer transfer of the ACCP2 and ACCPDN2 registers upon..." "Zero,Peak" bitfld.byte 0x00 5. " BTS1 ,Performs buffer transfer of the ACCP1 and ACCPDN1 registers upon..." "Zero,Peak" bitfld.byte 0x00 4. " BTS0 ,Performs buffer transfer of the ACCP0 and ACCPDN0 registers upon..." "Zero,Peak" textline " " bitfld.byte 0x00 2. " BDIS2 ,Enable ACCP2 and ACCPDN2" "Yes,No" bitfld.byte 0x00 1. " BDIS1 ,Enable ACCP1 and ACCPDN1" "Yes,No" bitfld.byte 0x00 0. " BDIS0 ,Enable ACCP02 and ACCPDN0" "Yes,No" group.word 0xA0++0x1 "Channel 0" line.word 0x0 "ACCP0,ADCMP Compare Value Store Register" group.word (0xA0+0x4)++0x1 line.word 0x0 "ACCPDN0,ADCMP Compare Value Store Register, Down-count Direction Only" group.word 0xA8++0x1 "Channel 1" line.word 0x0 "ACCP1,ADCMP Compare Value Store Register" group.word (0xA8+0x4)++0x1 line.word 0x0 "ACCPDN1,ADCMP Compare Value Store Register, Down-count Direction Only" group.word 0xB0++0x1 "Channel 2" line.word 0x0 "ACCP2,ADCMP Compare Value Store Register" group.word (0xB0+0x4)++0x1 line.word 0x0 "ACCPDN2,ADCMP Compare Value Store Register, Down-count Direction Only" tree.end width 6. tree "ADC Start Trigger Selector Unit" group.word 0xC0++0x1 line.word 0x0 "ATSA,ADC Start Trigger Select Register" bitfld.word 0x00 12.--13. " AD2P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 2" "Start signal,OR signal,?..." bitfld.word 0x00 10.--11. " AD1P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 1" "Start signal,OR signal,?..." bitfld.word 0x00 8.--9. " AD0P[1:0] ,Selects the start signal to be used to start priority conversion of ADC channel 0" "Start signal,OR signal,?..." textline " " bitfld.word 0x00 4.--5. " AD2S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 2" "Start signal,OR signal,?..." bitfld.word 0x00 2.--3. " AD1S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 1" "Start signal,OR signal,?..." bitfld.word 0x00 0.--1. " AD0S[1:0] ,Selects the start signal to be used to start the scan conversion of ADC channel 0" "Start signal,OR signal,?..." tree.end width 12. tree.end endif endif tree.end tree "PPG (Programmable Pulse Generator)" base ad:0x40024000 width 10. group.word 0x00++0x01 line.word 0x00 "TTCR0,PPG Start Trigger Control Register 0" bitfld.word 0x00 15. " TRG6O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 14. " TRG4O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 13. " TRG2O ,Control the PPG start trigger signal" "Disabled,No effect" textline " " bitfld.word 0x00 12. " TRG0O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 10.--11. " CS0 ,Set an operation clock of UP counter" "PCLK/2,PCLK/8,PCLK/32,PCLK/64" rbitfld.word 0x00 9. " MONI0 ,Indicates the PPG 8-bit UP counter operation state" "Stopped,Started" textline " " bitfld.word 0x00 8. " STR0 ,Enables the 8-bit UP counter operation" "No effect,Enabled" group.word 0x08++0x01 line.word 0x00 "COMP0,PPG Compare Register 0" hexmask.word.byte 0x00 8.--15. 1. " COMP0 ,Sets a PPG Compare Register value" group.word 0x0C++0x01 line.word 0x00 "COMP2,PPG Compare Register 2" hexmask.word.byte 0x00 0.--7. 1. " COMP2 ,Sets a PPG Compare Register value" group.word 0x10++0x01 line.word 0x00 "COMP4,PPG Compare Register 4" hexmask.word.byte 0x00 8.--15. 1. " COMP4 ,Sets a PPG Compare Register value" group.word 0x14++0x01 line.word 0x00 "COMP6,PPG Compare Register 6" hexmask.word.byte 0x00 0.--7. 1. " COMP6 ,Sets a PPG Compare Register value" sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) group.word 0x20++0x01 line.word 0x00 "TTCR1,PPG Start Trigger Control Register 1" bitfld.word 0x00 15. " TRG7O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 14. " TRG5O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 13. " TRG3O ,Control the PPG start trigger signal" "Disabled,No effect" textline " " bitfld.word 0x00 12. " TRG1O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 10.--11. " CS1 ,Set an operation clock of UP counter" "PCLK/2,PCLK/8,PCLK/32,PCLK/64" rbitfld.word 0x00 9. " MONI1 ,Indicates the PPG 8-bit UP counter operation state" "Stopped,Started" textline " " bitfld.word 0x00 8. " STR1 ,Enables the 8-bit UP counter operation" "No effect,Enabled" group.word 0x28++0x01 line.word 0x00 "COMP1,PPG Compare Register 1" hexmask.word.byte 0x00 8.--15. 1. " COMP1 ,Sets a PPG Compare Register value" group.word 0x2C++0x01 line.word 0x00 "COMP3,PPG Compare Register 3" hexmask.word.byte 0x00 0.--7. 1. " COMP3 ,Sets a PPG Compare Register value" group.word 0x30++0x01 line.word 0x00 "COMP5,PPG Compare Register 5" hexmask.word.byte 0x00 8.--15. 1. " COMP5 ,Sets a PPG Compare Register value" group.word 0x34++0x01 line.word 0x00 "COMP7,PPG Compare Register 7" hexmask.word.byte 0x00 0.--7. 1. " COMP7 ,Sets a PPG Compare Register value" endif sif ((cpuis("MB9BF*"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) group.word 0x40++0x01 line.word 0x00 "TTCR2,PPG Start Trigger Control Register 2" bitfld.word 0x00 15. " TRG22O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 14. " TRG20O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 13. " TRG18O ,Control the PPG start trigger signal" "Disabled,No effect" textline " " bitfld.word 0x00 12. " TRG16O ,Control the PPG start trigger signal" "Disabled,No effect" bitfld.word 0x00 10.--11. " CS2 ,Set an operation clock of UP counter" "PCLK/2,PCLK/8,PCLK/32,PCLK/64" rbitfld.word 0x00 9. " MONI2 ,Indicates the PPG 8-bit UP counter operation state" "Stopped,Started" textline " " bitfld.word 0x00 8. " STR2 ,Enables the 8-bit UP counter operation" "No effect,Enabled" group.word 0x48++0x01 line.word 0x00 "COMP8,PPG Compare Register 8" hexmask.word.byte 0x00 8.--15. 1. " COMP8 ,Sets a PPG Compare Register value" group.word 0x4C++0x01 line.word 0x00 "COMP10,PPG Compare Register 10" hexmask.word.byte 0x00 0.--7. 1. " COMP10 ,Sets a PPG Compare Register value" group.word 0x50++0x01 line.word 0x00 "COMP12,PPG Compare Register 12" hexmask.word.byte 0x00 8.--15. 1. " COMP12 ,Sets a PPG Compare Register value" group.word 0x54++0x01 line.word 0x00 "COMP14,PPG Compare Register 14" hexmask.word.byte 0x00 0.--7. 1. " COMP14 ,Sets a PPG Compare Register value" endif group.word 0x100++0x01 line.word 0x00 "TRG,PPG Start Register" sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF11?M"))&&(!cpuis("MB9AF11?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) bitfld.word 0x00 15. " PEN15 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 14. " PEN14 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 13. " PEN13 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " PEN12 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 11. " PEN11 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 10. " PEN10 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " PEN09 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 8. " PEN08 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 7. " PEN07 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " PEN06 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 5. " PEN05 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 4. " PEN04 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PEN03 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 2. " PEN02 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 1. " PEN01 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " PEN00 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" else bitfld.word 0x00 7. " PEN07 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 6. " PEN06 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 5. " PEN05 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " PEN04 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 3. " PEN03 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 2. " PEN02 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " PEN01 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 0. " PEN00 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" endif group.word 0x104++0x01 line.word 0x00 "REVC,Output Reverse Register" sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) bitfld.word 0x00 15. " REV15 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 14. " REV14 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 13. " REV13 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 12. " REV12 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 11. " REV11 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 10. " REV10 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 9. " REV09 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 8. " REV08 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 7. " REV07 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 6. " REV06 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 5. " REV05 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 4. " REV04 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 3. " REV03 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 2. " REV02 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 1. " REV01 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 0. " REV00 ,Sets a polarity of PPG output value" "Normal,Inverted" else bitfld.word 0x00 7. " REV07 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 6. " REV06 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 5. " REV05 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 4. " REV04 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 3. " REV03 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 2. " REV02 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 1. " REV01 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 0. " REV00 ,Sets a polarity of PPG output value" "Normal,Inverted" endif sif ((cpuis("MB9B*"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) group.word 0x140++0x01 line.word 0x00 "TRG1,PPG Start Register 1" bitfld.word 0x00 7. " PEN23 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 6. " PEN22 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 5. " PEN21 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " PEN20 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 3. " PEN19 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 2. " PEN18 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " PEN17 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" bitfld.word 0x00 0. " PEN16 ,Starts PPG operation and sets its operation mode" "Disabled,Enabled" group.word 0x144++0x01 line.word 0x00 "REVC1,Output Reverse Register 1" bitfld.word 0x00 7. " REV23 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 6. " REV22 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 5. " REV21 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 4. " REV20 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 3. " REV19 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 2. " REV18 ,Sets a polarity of PPG output value" "Normal,Inverted" textline " " bitfld.word 0x00 1. " REV17 ,Sets a polarity of PPG output value" "Normal,Inverted" bitfld.word 0x00 0. " REV16 ,Sets a polarity of PPG output value" "Normal,Inverted" endif group.byte 0x200++0x01 line.byte 0x00 "PPGC1,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x00 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x00 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC0,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.byte 0x204++0x01 line.byte 0x00 "PPGC3,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x00 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x00 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC2,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.word 0x208++0x01 line.word 0x00 "PRL0,PPG Reload Register" group.word 0x20C++0x01 line.word 0x00 "PRL1,PPG Reload Register" group.word 0x210++0x01 line.word 0x00 "PRL2,PPG Reload Register" group.word 0x214++0x01 line.word 0x00 "PRL3,PPG Reload Register" group.byte 0x218++0x00 line.byte 0x00 "GATEC0,PPG Gate Function Control Registers" bitfld.byte 0x00 5. " STRG2 ,Selects an operation trigger signal for PPG2" "TRG,GATE" bitfld.byte 0x00 4. " EDGE2 ,Sets an effective level of GATE2 signal from the multifunction timer" "High,Low" bitfld.byte 0x00 1. " STRG0 ,Selects an operation trigger signal for PPG0" "TRG,GATE" textline " " bitfld.byte 0x00 0. " EDGE0 ,Sets an effective level of GATE0 signal from the multifunction timer" "High,Low" group.byte 0x240++0x01 line.byte 0x00 "PPGC5,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x00 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x00 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC4,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.byte 0x244++0x01 line.byte 0x00 "PPGC7,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x00 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x00 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC6,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.word 0x248++0x01 line.word 0x00 "PRL4,PPG Reload Register" group.word 0x24C++0x01 line.word 0x00 "PRL5,PPG Reload Register" group.word 0x250++0x01 line.word 0x00 "PRL6,PPG Reload Register" group.word 0x254++0x01 line.word 0x00 "PRL7,PPG Reload Register" group.byte 0x258++0x00 line.byte 0x00 "GATEC4,PPG Gate Function Control Registers" bitfld.byte 0x00 5. " STRG6 ,Selects an operation trigger signal for PPG6" "TRG,GATE" bitfld.byte 0x00 4. " EDGE6 ,Sets an effective level of GATE6 signal from the multifunction timer" "High,Low" bitfld.byte 0x00 1. " STRG4 ,Selects an operation trigger signal for PPG4" "TRG,GATE" textline " " bitfld.byte 0x00 0. " EDGE4 ,Sets an effective level of GATE4 signal from the multifunction timer" "High,Low" sif ((!cpuis("MB9AF11?K"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF13?K"))&&(!cpuis("MB9AF13?L"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AF31?K"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AFA3?L"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) group.byte 0x280++0x01 line.byte 0x00 "PPGC9,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC8,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.byte 0x284++0x01 line.byte 0x00 "PPGC11,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC10,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.word 0x288++0x01 line.word 0x00 "PRL8,PPG Reload Register" group.word 0x28C++0x01 line.word 0x00 "PRL9,PPG Reload Register" group.word 0x290++0x01 line.word 0x00 "PRL10,PPG Reload Register" group.word 0x294++0x01 line.word 0x00 "PRL11,PPG Reload Register" group.byte 0x298++0x00 line.byte 0x00 "GATEC8,PPG Gate Function Control Registers" bitfld.byte 0x00 5. " STRG10 ,Selects an operation trigger signal for PPG10" "TRG,GATE" bitfld.byte 0x00 4. " EDGE10 ,Sets an effective level of GATE10 signal from the multifunction timer" "High,Low" bitfld.byte 0x00 1. " STRG8 ,Selects an operation trigger signal for PPG8" "TRG,GATE" textline " " bitfld.byte 0x00 0. " EDGE8 ,Sets an effective level of GATE8 signal from the multifunction timer" "High,Low" group.byte 0x2C0++0x01 line.byte 0x00 "PPGC13,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC12,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.byte 0x2C4++0x01 line.byte 0x00 "PPGC15,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC14,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.word 0x2C8++0x01 line.word 0x00 "PRL12,PPG Reload Register" group.word 0x2CC++0x01 line.word 0x00 "PRL13,PPG Reload Register" group.word 0x2D0++0x01 line.word 0x00 "PRL14,PPG Reload Register" group.word 0x2D4++0x01 line.word 0x00 "PRL15,PPG Reload Register" group.byte 0x2D8++0x00 line.byte 0x00 "GATEC12,PPG Gate Function Control Registers" bitfld.byte 0x00 5. " STRG14 ,Selects an operation trigger signal for PPG14" "TRG,GATE" bitfld.byte 0x00 4. " EDGE14 ,Sets an effective level of GATE14 signal from the multifunction timer" "High,Low" bitfld.byte 0x00 1. " STRG12 ,Selects an operation trigger signal for PPG12" "TRG,GATE" textline " " bitfld.byte 0x00 0. " EDGE12 ,Sets an effective level of GATE12 signal from the multifunction timer" "High,Low" endif sif ((cpuis("MB9BF*"))&&(!cpuis("MB9BF129T"))&&(!cpuis("MB9BF129S"))&&(!cpuis("MB9BF128T"))&&(!cpuis("MB9BF128S"))) group.byte 0x300++0x01 line.byte 0x00 "PPGC17,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC16,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.byte 0x304++0x01 line.byte 0x00 "PPGC19,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC18,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.word 0x308++0x01 line.word 0x00 "PRL16,PPG Reload Register" group.word 0x30C++0x01 line.word 0x00 "PRL17,PPG Reload Register" group.word 0x310++0x01 line.word 0x00 "PRL18,PPG Reload Register" group.word 0x314++0x01 line.word 0x00 "PRL19,PPG Reload Register" group.byte 0x318++0x00 line.byte 0x00 "GATEC16,PPG Gate Function Control Registers" bitfld.byte 0x00 5. " STRG14 ,Selects an operation trigger signal for PPG14" "TRG,GATE" bitfld.byte 0x00 4. " EDGE14 ,Sets an effective level of GATE14 signal from the multifunction timer" "High,Low" bitfld.byte 0x00 1. " STRG12 ,Selects an operation trigger signal for PPG12" "TRG,GATE" textline " " bitfld.byte 0x00 0. " EDGE12 ,Sets an effective level of GATE12 signal from the multifunction timer" "High,Low" group.byte 0x340++0x01 line.byte 0x00 "PPGC21,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC20,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.byte 0x344++0x01 line.byte 0x00 "PPGC23,PPG Operation Mode Control Register" bitfld.byte 0x00 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x00 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x00 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x00 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" sif (!cpuis("MB9AF105?A")&&!cpuis("MB9AF11*")&&!cpuis("MB9AF132K")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF13?L")&&!cpuis("MB9AF14*")&&!cpuis("MB9AF31*")&&!cpuis("MB9AF34*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AFA4*")&&!cpuis("MB9AFB4*")&&!cpuis("MB9BF?1*")) bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif line.byte 0x01 "PPGC22,PPG Operation Mode Control Register" bitfld.byte 0x01 7. " PIE ,Enables a PPG interrupt" "Disabled,Enabled" bitfld.byte 0x01 6. " PUF ,Controls the underflow bits of PPG Counter" "No detected,Detected" bitfld.byte 0x01 5. " INTM ,Sets an interrupt mode" "PPLH or PPLL,PPLH" textline " " bitfld.byte 0x01 3.--4. " PCS ,Sets an operation clock of PPG's DOWN Counter" "PCLK,PCLK/4,PCLK/16,PCLK/64" bitfld.byte 0x01 1.--2. " MD ,PPG output value can be set to be reversed" "8bit,8+8bit,16bit,16+16bit" sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGR/Mft timer,TGC" else bitfld.byte 0x01 0. " TTRG ,Selects the PPG start trigger" "TGC,TGR/Mft timer" endif group.word 0x348++0x01 line.word 0x00 "PRL20,PPG Reload Register" group.word 0x34C++0x01 line.word 0x00 "PRL21,PPG Reload Register" group.word 0x350++0x01 line.word 0x00 "PRL22,PPG Reload Register" group.word 0x354++0x01 line.word 0x00 "PRL23,PPG Reload Register" group.byte 0x358++0x00 line.byte 0x00 "GATEC20,PPG Gate Function Control Registers" bitfld.byte 0x00 5. " STRG14 ,Selects an operation trigger signal for PPG14" "TRG,GATE" bitfld.byte 0x00 4. " EDGE14 ,Sets an effective level of GATE14 signal from the multifunction timer" "High,Low" bitfld.byte 0x00 1. " STRG12 ,Selects an operation trigger signal for PPG12" "TRG,GATE" textline " " bitfld.byte 0x00 0. " EDGE12 ,Sets an effective level of GATE12 signal from the multifunction timer" "High,Low" endif sif (cpuis("MB9AFA3*")) group.byte 0x380++0x00 line.byte 0x00 "IGBTMD,IGBT Mode Control Register" bitfld.byte 0x00 7. " IGATIH ,Stop prohibition mode selection in output active bit" "Normal,Prohibition" bitfld.byte 0x00 4.--6. " IGNFW ,Noise filter width selection bit" "Disabled,4 PCLK,8 PCLK,16 PCLK,32 PCLK,?..." textline " " bitfld.byte 0x00 3. " IGOSEL[1] ,IGBT1 output level selection bit" "Normal,Inverted" bitfld.byte 0x00 2. " IGOSEL[0] ,IGBT0 output level selection bit" "Normal,Inverted" textline " " bitfld.byte 0x00 1. " IGTRGLV ,Trigger input level selection bit" "Normal,Inverted" bitfld.byte 0x00 0. " IGBTMD ,IGBT mode selection bit" "Normal,IGBT" endif width 0xb tree.end endif sif (!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF14?L")&&!cpuis("MB9AF14?M")&&!cpuis("MB9AF14?N")&&!cpuis("MB9AF34?L")&&!cpuis("MB9AF34?M")&&!cpuis("MB9AF34?N")&&!cpuis("MB9AF?4?L")&&!cpuis("MB9AF?4?M")&&!cpuis("MB9AF?4?N")&&!cpuis("MB9AFA3?L")&&!cpuis("MB9AFA3?M")&&!cpuis("MB9AFA3?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")&&!cpuis("MB9AFAA?N")&&!cpuis("MB9AFA4?L")&&!cpuis("MB9AFA4?M")&&!cpuis("MB9AFA4?N")&&!cpuis("MB9AF13?K")&&!cpuis("MB9AFB4?L")&&!cpuis("MB9AFB4?M")&&!cpuis("MB9AFB4?N")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")&&!cpuis("MB9AF121K")&&!cpuis("MB9AF121L")) tree "QPRC (Quad Position and Revolution Counter)" tree "Channel 0" base ad:0x40026000 width 8. group.word 0x00++0x01 line.word 0x00 "QPCR,QPRC Position Count Register" group.word 0x04++0x01 line.word 0x00 "QRCR,QPRC Revolution Count Register" group.word 0x08++0x01 line.word 0x00 "QPCCR,QPRC Position Counter Compare Register" group.word 0x0C++0x01 line.word 0x00 "QPRCR,QPRC Position and Revolution Counter Compare Register" group.word 0x10++0x01 line.word 0x00 "QMPR,QPRC Maximum Position Register" group.word 0x14++0x01 line.word 0x00 "QICR,QPRC Interrupt Control Register" bitfld.word 0x00 13. " QPCNRCMF ,PC match and RC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 12. " QPCNRCMIE ,PC match and RC match interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 11. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" textline " " rbitfld.word 0x00 10. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" bitfld.word 0x00 9. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted" bitfld.word 0x00 8. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected" textline " " bitfld.word 0x00 4. " OUZIE ,Overflow underflow or zero index interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" if (((d.w(ad:0x40026000+0x18))&0x23)==0x20) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" bitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" elif ((((d.w(ad:0x40026000+0x18))&0x20)==0x20)&&(((d.w(ad:0x40026000+0x18))&0x3)!=0x00)) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" rbitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" elif (((d.w(ad:0x40026000+0x18))&0x23)==0x00) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising or Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" bitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" else group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising or Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" rbitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" endif group.word 0x1C++0x01 line.word 0x00 "QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" sif ((!cpuis("MB9AF105?A"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF11?M"))&&(!cpuis("MB9AF11?N"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9BF?1?S"))&&(!cpuis("MB9BF?1?T"))&&(!cpuis("MB9BF10*"))&&(!cpuis("MB9BF30*"))&&(!cpuis("MB9BF40*"))&&(!cpuis("MB9BF50*"))) rgroup.long 0x3C++0x03 line.long 0x00 "QPRCRR,Quad Counter Position Rotation Count Register" hexmask.long.word 0x00 16.--31. 1. " QPCRR ,Quad counter position count display bit" hexmask.long.word 0x00 0.--15. 1. " QRCRR ,Quad counter rotation count display bit" endif width 0xb tree.end sif (!cpuis("MB9BF52?K")&&!cpuis("MB9BF12?K")&&!cpuis("MB9BF32?K")&&!cpuis("MB9BF121J")&&!cpuis("MB9BF52?S")&&!cpuis("MB9BF42?S")&&!cpuis("MB9BF12?S")&&!cpuis("MB9BF32?S")&&!cpuis("MB9AF31?K")&&!cpuis("MB9AF11?K")) tree "Channel 1" base ad:0x40026040 width 8. group.word 0x00++0x01 line.word 0x00 "QPCR,QPRC Position Count Register" group.word 0x04++0x01 line.word 0x00 "QRCR,QPRC Revolution Count Register" group.word 0x08++0x01 line.word 0x00 "QPCCR,QPRC Position Counter Compare Register" group.word 0x0C++0x01 line.word 0x00 "QPRCR,QPRC Position and Revolution Counter Compare Register" group.word 0x10++0x01 line.word 0x00 "QMPR,QPRC Maximum Position Register" group.word 0x14++0x01 line.word 0x00 "QICR,QPRC Interrupt Control Register" bitfld.word 0x00 13. " QPCNRCMF ,PC match and RC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 12. " QPCNRCMIE ,PC match and RC match interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 11. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" textline " " rbitfld.word 0x00 10. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" bitfld.word 0x00 9. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted" bitfld.word 0x00 8. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected" textline " " bitfld.word 0x00 4. " OUZIE ,Overflow underflow or zero index interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" if (((d.w(ad:0x40026040+0x18))&0x23)==0x20) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" bitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" elif ((((d.w(ad:0x40026040+0x18))&0x20)==0x20)&&(((d.w(ad:0x40026040+0x18))&0x3)!=0x00)) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" rbitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" elif (((d.w(ad:0x40026040+0x18))&0x23)==0x00) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising or Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" bitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" else group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising or Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" rbitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" endif group.word 0x1C++0x01 line.word 0x00 "QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" sif ((!cpuis("MB9AF105?A"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF11?M"))&&(!cpuis("MB9AF11?N"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9BF?1?S"))&&(!cpuis("MB9BF?1?T"))&&(!cpuis("MB9BF10*"))&&(!cpuis("MB9BF30*"))&&(!cpuis("MB9BF40*"))&&(!cpuis("MB9BF50*"))) rgroup.long 0x3C++0x03 line.long 0x00 "QPRCRR,Quad Counter Position Rotation Count Register" hexmask.long.word 0x00 16.--31. 1. " QPCRR ,Quad counter position count display bit" hexmask.long.word 0x00 0.--15. 1. " QRCRR ,Quad counter rotation count display bit" endif width 0xb tree.end endif sif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")) tree "Channel 2" base ad:0x40026080 width 8. group.word 0x00++0x01 line.word 0x00 "QPCR,QPRC Position Count Register" group.word 0x04++0x01 line.word 0x00 "QRCR,QPRC Revolution Count Register" group.word 0x08++0x01 line.word 0x00 "QPCCR,QPRC Position Counter Compare Register" group.word 0x0C++0x01 line.word 0x00 "QPRCR,QPRC Position and Revolution Counter Compare Register" group.word 0x10++0x01 line.word 0x00 "QMPR,QPRC Maximum Position Register" group.word 0x14++0x01 line.word 0x00 "QICR,QPRC Interrupt Control Register" bitfld.word 0x00 13. " QPCNRCMF ,PC match and RC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 12. " QPCNRCMIE ,PC match and RC match interrupt enable bit" "Disabled,Enabled" rbitfld.word 0x00 11. " DIROU ,Last position counter flow direction bit" "Incremented,Decremented" textline " " rbitfld.word 0x00 10. " DIRPC ,Last position counter direction bit" "Incremented,Decremented" bitfld.word 0x00 9. " CDCF ,Count inversion interrupt request flag bit" "Not inverted,Inverted" bitfld.word 0x00 8. " CDCIE ,Count inversion interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " ZIIF ,Zero index interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 6. " OFDF ,Overflow interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 5. " UFDF ,Underflow interrupt request flag bit" "Not detected,Detected" textline " " bitfld.word 0x00 4. " OUZIE ,Overflow underflow or zero index interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 3. " QPRCMF ,PC and RC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 2. " QPRCMIE ,PC and RC match interrupt enable bit" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " QPCMF ,PC match interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " QPCMIE ,PC match interrupt enable bit" "Disabled,Enabled" if (((d.w(ad:0x40026080+0x18))&0x23)==0x20) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" bitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" elif ((((d.w(ad:0x40026080+0x18))&0x20)==0x20)&&(((d.w(ad:0x40026080+0x18))&0x3)!=0x00)) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Level L,Level H,Disabled" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" rbitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" elif (((d.w(ad:0x40026080+0x18))&0x23)==0x00) group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising or Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" bitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" else group.word 0x18++0x01 line.word 0x00 "QCR,QPRC Control Register" bitfld.word 0x00 14.--15. " CGE ,Detection edge selection bits" "Disabled,Falling,Rising,Rising or Falling" bitfld.word 0x00 12.--13. " BES ,BIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" bitfld.word 0x00 10.--11. " AES ,AIN detection edge selection bits" "Disabled,Falling,Rising,Rising/Falling" textline " " bitfld.word 0x00 8.--9. " PCRM ,Position counter reset mask bits" "No reset,Twice,Four,Eight" rbitfld.word 0x00 7. " SWAP ,Swap bit" "Not swapped,Swapped AIN/BIN" bitfld.word 0x00 6. " RSEL ,Register function selection bit" "Position,Revolution" textline " " bitfld.word 0x00 5. " CGSC ,Count clear or gate selection bit" "Counter clear,Gate" bitfld.word 0x00 4. " PSTP ,Position counter stop bit" "Disabled,Enabled" bitfld.word 0x00 2.--3. " RCM ,Revolution counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" textline " " bitfld.word 0x00 0.--1. " PCM ,Position counter mode bits" "RC_Mode0,RC_Mode1,RC_Mode2,RC_Mode3" endif group.word 0x1C++0x01 line.word 0x00 "QECR,QPRC Extension Control Register" bitfld.word 0x00 2. " ORNGIE ,Outrange interrupt enable bit" "Disabled,Enabled" bitfld.word 0x00 1. " ORNGF ,Outrange interrupt request flag bit" "Not detected,Detected" bitfld.word 0x00 0. " ORNGMD ,Outrange mode selection bit" "Positive number,8K value" sif ((!cpuis("MB9AF105?A"))&&(!cpuis("MB9AF11?L"))&&(!cpuis("MB9AF11?M"))&&(!cpuis("MB9AF11?N"))&&(!cpuis("MB9AF31?L"))&&(!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9BF?1?S"))&&(!cpuis("MB9BF?1?T"))&&(!cpuis("MB9BF10*"))&&(!cpuis("MB9BF30*"))&&(!cpuis("MB9BF40*"))&&(!cpuis("MB9BF50*"))) rgroup.long 0x3C++0x03 line.long 0x00 "QPRCRR,Quad Counter Position Rotation Count Register" hexmask.long.word 0x00 16.--31. 1. " QPCRR ,Quad counter position count display bit" hexmask.long.word 0x00 0.--15. 1. " QRCRR ,Quad counter rotation count display bit" endif width 0xb tree.end endif tree.end endif sif (cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF14?L")||cpuis("MB9AF14?M")||cpuis("MB9AF14?N")||cpuis("MB9AF34?L")||cpuis("MB9AF34?M")||cpuis("MB9AF34?N")||cpuis("MB9AF14?M")||cpuis("MB9AF?4?L")||cpuis("MB9AF?4?M")||cpuis("MB9AF?4?N")||cpuis("MB9AFA3??")||cpuis("MB9AF154M")||cpuis("MB9AF154N")||cpuis("MB9AF154R")||cpuis("MB9AF155M")||cpuis("MB9AF155N")||cpuis("MB9AF155R")||cpuis("MB9AF156M")||cpuis("MB9AF156N")||cpuis("MB9AF156R")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2L")||cpuis("MB9AFAA2M")||cpuis("MB9AFAA2N")||cpuis("MB9AF1A1L")||cpuis("MB9AF1A1M")||cpuis("MB9AF1A1N")||cpuis("MB9AF1A2L")||cpuis("MB9AF1A2M")||cpuis("MB9AF1A2N")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF428S")||cpuis("MB9BF428T")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")||cpuis("MB9BF129S")||cpuis("MB9BF129T")||cpuis("MB9BF128S")||cpuis("MB9BF128T")||cpuis("MB9BF329S")||cpuis("MB9BF329T")||cpuis("MB9BF328S")||cpuis("MB9BF328T")) tree "HDMI-CEC (HDMI-CEC/Remote Control Reception)" tree "Channel 1" base ad:0x40034000 width 8. tree "CEC Reception/Remote Control Reception Registers" if (((d.b(ad:0x40034000+0x41))&0x1)==0x1) group.byte 0x41++0x00 line.byte 0x00 "RCCR,Reception Control Register" rbitfld.byte 0x00 7. " THSEL ,Threshold selection bit" "Low,High" rbitfld.byte 0x00 3. " ADRCE ,Address comparison enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1.--2. " MOD[0:1] ,Operation mode setting bits" "SIRCS,,NEC/AEHA,HDMI-CEC" bitfld.byte 0x00 0. " EN ,Operation enable bit" "Disabled,Enabled" else group.byte 0x41++0x00 line.byte 0x00 "RCCR,Reception Control Register" bitfld.byte 0x00 7. " THSEL ,Threshold selection bit" "Low,High" bitfld.byte 0x00 3. " ADRCE ,Address comparison enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1.--2. " MOD[0:1] ,Operation mode setting bits" "SIRCS,,NEC/AEHA,HDMI-CEC" bitfld.byte 0x00 0. " EN ,Operation enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40034000+0x41))&0x6)==0x6)&&(((d.b(ad:0x40034000+0x41))&0x1)==0x1) group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ACKIE ,ACK interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" textline " " bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" bitfld.byte 0x00 2. " ACK ,ACK detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " EOM ,EOM detection bit" "Not detected,Detected" bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" elif (((d.b(ad:0x40034000+0x41))&0x6)==0x6)&&(((d.b(ad:0x40034000+0x41))&0x1)==0x0) group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ACKIE ,ACK interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" textline " " bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" bitfld.byte 0x00 2. " ACK ,ACK detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " EOM ,EOM detection bit" "Not detected,Detected" bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" elif (((d.b(ad:0x40034000+0x41))&0x6)!=0x6)&&(((d.b(ad:0x40034000+0x41))&0x1)==0x1) group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" else group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" endif if (((d.b(ad:0x40034000+0x41))&0x1)==0x1) rgroup.byte 0x4C++0x01 line.byte 0x1 "RCADR1,Device Address Setting Register 1" hexmask.byte 0x1 0.--4. 1. " RCADR1 ,Device address setting bits" line.byte 0x0 "RCADR2,Device Address Setting Register 2" hexmask.byte 0x0 0.--4. 1. " RCADR2 ,Device address setting bits" rgroup.byte 0x44++0x01 line.byte 0x00 "RCDAHW,H Width Setting Register A" line.byte 0x01 "RCSHW,Start Bit H Width Setting Register" rgroup.byte 0x49++0x00 line.byte 0x00 "RCDBHW,H Width Setting Register B" else group.byte 0x4C++0x01 line.byte 0x1 "RCADR1,Device Address Setting Register 1" hexmask.byte 0x1 0.--4. 1. " RCADR1 ,Device address setting bits" line.byte 0x0 "RCADR2,Device Address Setting Register 2" hexmask.byte 0x0 0.--4. 1. " RCADR2 ,Device address setting bits" group.byte 0x44++0x01 line.byte 0x00 "RCDAHW,H Width Setting Register A" line.byte 0x01 "RCSHW,Start Bit H Width Setting Register" group.byte 0x49++0x00 line.byte 0x00 "RCDBHW,H Width Setting Register B" endif rgroup.byte 0x50++0x01 line.byte 0x01 "RCDTHH,Data Save H High Register" line.byte 0x00 "RCDTHL,Data Save H Low Register" rgroup.byte 0x54++0x01 line.byte 0x00 "RCDTLL,Data Save L Low Register" line.byte 0x01 "RCDTLH,Data Save L High Register" if (((d.b(ad:0x40034000+0x41))&0x1)==0x1) rgroup.word 0x58++0x01 line.word 0x00 "RCCKD,Clock Division Setting Register" bitfld.word 0x00 12. " CKSEL ,Operating clock selection bit" "Divided PCLK,Sub-clock" hexmask.word 0x00 0.--11. 1. " CKDIV ,Operating clock division setting bits" if (((d.b(ad:0x40034000+0x41))&0x06)==0x04) rgroup.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " RC ,Repeat code detection flag bit" "Not detected,Detected" rgroup.byte 0x5c++0x00 line.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" else rgroup.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" hgroup.byte 0x5c++0x00 hide.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" endif if (((d.b(ad:0x40034000+0x41))&0x06)==0x06) rgroup.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 7. " LELIE ,Maximum data bit width violation interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " LESIE ,Minimum data bit width violation interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " LELE ,Maximum data bit width violation detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LESE ,Minimum data bit width violation detection enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " LEL ,Maximum data bit width violation detection flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LES ,Minimum data bit width violation detection flag bit" "Not detected,Detected" rgroup.byte 0x64++0x01 line.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" line.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" else rgroup.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" hgroup.byte 0x64++0x01 hide.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" hide.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" endif else group.word 0x58++0x01 line.word 0x00 "RCCKD,Clock Division Setting Register" bitfld.word 0x00 12. " CKSEL ,Operating clock selection bit" "Divided PCLK,Sub-clock" hexmask.word 0x00 0.--11. 1. " CKDIV ,Operating clock division setting bits" if (((d.b(ad:0x40034000+0x41))&0x06)==0x04) group.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " RC ,Repeat code detection flag bit" "Not detected,Detected" group.byte 0x5c++0x00 line.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" else group.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" hgroup.byte 0x5c++0x00 hide.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" endif if (((d.b(ad:0x40034000+0x41))&0x06)==0x06) group.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 7. " LELIE ,Maximum data bit width violation interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " LESIE ,Minimum data bit width violation interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " LELE ,Maximum data bit width violation detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LESE ,Minimum data bit width violation detection enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " LEL ,Maximum data bit width violation detection flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LES ,Minimum data bit width violation detection flag bit" "Not detected,Detected" group.byte 0x64++0x01 line.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" line.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" else group.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" hgroup.byte 0x64++0x01 hide.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" hide.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" endif endif tree.end tree "CEC Transmission Registers" group.byte 0x00++0x00 line.byte 0x00 "TXCTRL,Transmission Control Register" bitfld.byte 0x00 5. " IBREN ,Bus error detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " ITSTEN ,Transmission status interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " EOM , EOM setting bit" "EOM0,EOM1" bitfld.byte 0x00 2. " START , START setting bit" "Invalid,Valid" textline " " bitfld.byte 0x00 0. " TXEN ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x04++0x00 line.byte 0x00 "TXDATA,Transmission Data Register" group.byte 0x08++0x00 line.byte 0x00 "TXSTS,Transmission Status Register" bitfld.byte 0x00 5. " IBR ,Bus error detection interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 4. " ITST ,Transmission status interrupt request bit" "Cleared,Detected" textline " " rbitfld.byte 0x00 0. " ACKSV ,ACK cycle value bit" "0,1" group.byte 0x0C++0x00 line.byte 0x00 "SFREE,Signal Free Time Setting Register" bitfld.byte 0x00 0.--3. " SFREE ,Signal free time setting bits" "1bit cycle,2bit cycle,3bit cycle,4bit cycle,5bit cycle,6bit cycle,7bit cycle,8bit cycle,9bit cycle,10bit cycle,11bit cycle,12bit cycle,13bit cycle,14bit cycle,15bit cycle,16bit cycle" tree.end width 0xb tree.end tree "Channel 2" base ad:0x40034100 width 8. tree "CEC Reception/Remote Control Reception Registers" if (((d.b(ad:0x40034100+0x41))&0x1)==0x1) group.byte 0x41++0x00 line.byte 0x00 "RCCR,Reception Control Register" rbitfld.byte 0x00 7. " THSEL ,Threshold selection bit" "Low,High" rbitfld.byte 0x00 3. " ADRCE ,Address comparison enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 1.--2. " MOD[0:1] ,Operation mode setting bits" "SIRCS,,NEC/AEHA,HDMI-CEC" bitfld.byte 0x00 0. " EN ,Operation enable bit" "Disabled,Enabled" else group.byte 0x41++0x00 line.byte 0x00 "RCCR,Reception Control Register" bitfld.byte 0x00 7. " THSEL ,Threshold selection bit" "Low,High" bitfld.byte 0x00 3. " ADRCE ,Address comparison enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1.--2. " MOD[0:1] ,Operation mode setting bits" "SIRCS,,NEC/AEHA,HDMI-CEC" bitfld.byte 0x00 0. " EN ,Operation enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40034100+0x41))&0x6)==0x6)&&(((d.b(ad:0x40034100+0x41))&0x1)==0x1) group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ACKIE ,ACK interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" rbitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" textline " " bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" bitfld.byte 0x00 2. " ACK ,ACK detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " EOM ,EOM detection bit" "Not detected,Detected" bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" elif (((d.b(ad:0x40034100+0x41))&0x6)==0x6)&&(((d.b(ad:0x40034100+0x41))&0x1)==0x0) group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ACKIE ,ACK interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" textline " " bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" bitfld.byte 0x00 2. " ACK ,ACK detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " EOM ,EOM detection bit" "Not detected,Detected" bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" elif (((d.b(ad:0x40034100+0x41))&0x6)!=0x6)&&(((d.b(ad:0x40034100+0x41))&0x1)==0x1) group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" else group.byte 0x40++0x00 line.byte 0x00 "RCST,Reception Interrupt Control Register" bitfld.byte 0x00 7. " STIE ,Start bit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 5. " OVFIE ,Counter overflow interrupt enable bit" "Disabled,Enabled" textline " " rbitfld.byte 0x00 4. " OVFSEL ,Counter overflow detection condition setting bit" "128 clocks,256 clocks" bitfld.byte 0x00 3. " ST ,Start bit detection bit" "Not detected,Detected" textline " " bitfld.byte 0x00 0. " OVF ,Counter overflow detection bit" "Not detected,Detected" endif if (((d.b(ad:0x40034100+0x41))&0x1)==0x1) rgroup.byte 0x4C++0x01 line.byte 0x1 "RCADR1,Device Address Setting Register 1" hexmask.byte 0x1 0.--4. 1. " RCADR1 ,Device address setting bits" line.byte 0x0 "RCADR2,Device Address Setting Register 2" hexmask.byte 0x0 0.--4. 1. " RCADR2 ,Device address setting bits" rgroup.byte 0x44++0x01 line.byte 0x00 "RCDAHW,H Width Setting Register A" line.byte 0x01 "RCSHW,Start Bit H Width Setting Register" rgroup.byte 0x49++0x00 line.byte 0x00 "RCDBHW,H Width Setting Register B" else group.byte 0x4C++0x01 line.byte 0x1 "RCADR1,Device Address Setting Register 1" hexmask.byte 0x1 0.--4. 1. " RCADR1 ,Device address setting bits" line.byte 0x0 "RCADR2,Device Address Setting Register 2" hexmask.byte 0x0 0.--4. 1. " RCADR2 ,Device address setting bits" group.byte 0x44++0x01 line.byte 0x00 "RCDAHW,H Width Setting Register A" line.byte 0x01 "RCSHW,Start Bit H Width Setting Register" group.byte 0x49++0x00 line.byte 0x00 "RCDBHW,H Width Setting Register B" endif rgroup.byte 0x50++0x01 line.byte 0x01 "RCDTHH,Data Save H High Register" line.byte 0x00 "RCDTHL,Data Save H Low Register" rgroup.byte 0x54++0x01 line.byte 0x00 "RCDTLL,Data Save L Low Register" line.byte 0x01 "RCDTLH,Data Save L High Register" if (((d.b(ad:0x40034100+0x41))&0x1)==0x1) rgroup.word 0x58++0x01 line.word 0x00 "RCCKD,Clock Division Setting Register" bitfld.word 0x00 12. " CKSEL ,Operating clock selection bit" "Divided PCLK,Sub-clock" hexmask.word 0x00 0.--11. 1. " CKDIV ,Operating clock division setting bits" if (((d.b(ad:0x40034100+0x41))&0x06)==0x04) rgroup.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " RC ,Repeat code detection flag bit" "Not detected,Detected" rgroup.byte 0x5c++0x00 line.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" else rgroup.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" hgroup.byte 0x5c++0x00 hide.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" endif if (((d.b(ad:0x40034100+0x41))&0x06)==0x06) rgroup.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 7. " LELIE ,Maximum data bit width violation interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " LESIE ,Minimum data bit width violation interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " LELE ,Maximum data bit width violation detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LESE ,Minimum data bit width violation detection enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " LEL ,Maximum data bit width violation detection flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LES ,Minimum data bit width violation detection flag bit" "Not detected,Detected" rgroup.byte 0x64++0x01 line.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" line.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" else rgroup.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" hgroup.byte 0x64++0x01 hide.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" hide.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" endif else group.word 0x58++0x01 line.word 0x00 "RCCKD,Clock Division Setting Register" bitfld.word 0x00 12. " CKSEL ,Operating clock selection bit" "Divided PCLK,Sub-clock" hexmask.word 0x00 0.--11. 1. " CKDIV ,Operating clock division setting bits" if (((d.b(ad:0x40034100+0x41))&0x06)==0x04) group.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " RC ,Repeat code detection flag bit" "Not detected,Detected" group.byte 0x5c++0x00 line.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" else group.byte 0x5d++0x00 line.byte 0x00 "RCRC,Repeat Code Interrupt Control Register" bitfld.byte 0x00 4. " RCIE ,Repeat Code Interrupt enable bit" "Disabled,Enabled" hgroup.byte 0x5c++0x00 hide.byte 0x00 "RCRHW,Repeat Code H Width Setting Register" endif if (((d.b(ad:0x40034100+0x41))&0x06)==0x06) group.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 7. " LELIE ,Maximum data bit width violation interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " LESIE ,Minimum data bit width violation interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " LELE ,Maximum data bit width violation detection enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " LESE ,Minimum data bit width violation detection enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " LEL ,Maximum data bit width violation detection flag bit" "Not detected,Detected" bitfld.byte 0x00 0. " LES ,Minimum data bit width violation detection flag bit" "Not detected,Detected" group.byte 0x64++0x01 line.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" line.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" else group.byte 0x61++0x00 line.byte 0x00 "RCLE,Data Bit Width Violation Control Register" bitfld.byte 0x00 3. " EPE ,Error pulse output enable bit" "Disabled,Enabled" hgroup.byte 0x64++0x01 hide.byte 0x00 "RCLESW,Minimum Data Bit Width Setting Register" hide.byte 0x01 "RCLELW,Maximum Data Bit Width Setting Register" endif endif tree.end tree "CEC Transmission Registers" group.byte 0x00++0x00 line.byte 0x00 "TXCTRL,Transmission Control Register" bitfld.byte 0x00 5. " IBREN ,Bus error detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " ITSTEN ,Transmission status interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " EOM , EOM setting bit" "EOM0,EOM1" bitfld.byte 0x00 2. " START , START setting bit" "Invalid,Valid" textline " " bitfld.byte 0x00 0. " TXEN ,Transmission operation enable bit" "Disabled,Enabled" group.byte 0x04++0x00 line.byte 0x00 "TXDATA,Transmission Data Register" group.byte 0x08++0x00 line.byte 0x00 "TXSTS,Transmission Status Register" bitfld.byte 0x00 5. " IBR ,Bus error detection interrupt request bit" "Cleared,Detected" bitfld.byte 0x00 4. " ITST ,Transmission status interrupt request bit" "Cleared,Detected" textline " " rbitfld.byte 0x00 0. " ACKSV ,ACK cycle value bit" "0,1" group.byte 0x0C++0x00 line.byte 0x00 "SFREE,Signal Free Time Setting Register" bitfld.byte 0x00 0.--3. " SFREE ,Signal free time setting bits" "1bit cycle,2bit cycle,3bit cycle,4bit cycle,5bit cycle,6bit cycle,7bit cycle,8bit cycle,9bit cycle,10bit cycle,11bit cycle,12bit cycle,13bit cycle,14bit cycle,15bit cycle,16bit cycle" tree.end width 0xb tree.end tree.end endif tree "12-bit ADC (12-bit A/D Converter)" tree "Unit 0" base ad:0x40027000 width 7. group.byte 0x00++0x01 line.byte 0x00 "ADSR,A/D Status Register" bitfld.byte 0x00 7. " ADSTP ,A/D conversion forced stop bit" "No effect,Stopped" bitfld.byte 0x00 6. " FDAS ,FIFO data placement selection bit" "MSB side,LSB side" rbitfld.byte 0x00 2. " PCNS ,Priority conversion pending flag" "Not pending,Pending" textline " " rbitfld.byte 0x00 1. " PCS ,Priority conversion status flag" "Stopped,In progress" rbitfld.byte 0x00 0. " SCS ,Scan conversion status flag" "Stopped,In progress" line.byte 0x01 "ADCR,A/D Control Register" bitfld.byte 0x01 7. " SCIF ,Scan conversion interrupt request bit" "Not stored,Stored" bitfld.byte 0x01 6. " PCIF ,Priority conversion interrupt request bit" "Not stored,Stored" bitfld.byte 0x01 5. " CMPIF ,Conversion result comparison interrupt request bit" "Not satisfied,Satisfied" textline " " bitfld.byte 0x01 3. " SCIE ,Scan conversion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x01 2. " PCIE ,Priority conversion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x01 1. " CMPIE ,Conversion result comparison interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " OVRIE ,FIFO overrun interrupt enable bit" "Disabled,Enabled" group.byte 0x08++0x01 line.byte 0x00 "SFNS,Scan Conversion FIFO Stage Count Setup Register" bitfld.byte 0x00 0.--3. " SFS[3:0] ,Scan conversion FIFO stage count setting bit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" line.byte 0x01 "SCCR,Scan Conversion Control Register" rbitfld.byte 0x01 7. " SEMP ,Scan conversion FIFO empty bit" "Data remains,Empty" rbitfld.byte 0x01 6. " SFUL ,Scan conversion FIFO full bit" "Not full,Full" bitfld.byte 0x01 5. " SOVR ,Scan conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.byte 0x01 4. " SFCLR ,Scan conversion FIFO clear bit" "No effect,Cleared" bitfld.byte 0x01 2. " RPT ,Scan conversion repeat bit" "Single,Repeat" bitfld.byte 0x01 1. " SHEN ,Scan conversion timer start enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " SSTR ,Scan conversion start bit" "No effect,Started" hgroup.long 0x0C++0x03 hide.long 0x00 "SCFD,Scan Conversion FIFO Data Register" in sif (cpuis("MB9AF131L")||cpuis("MB9AF132L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF131K")||cpuis("MB9AF132K")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF121J")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF421K")||cpuis("MB9AF421L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF42?T")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9AF154N")||cpuis("MB9AF155N")||cpuis("MB9AF156N")||cpuis("MB9AF154R")||cpuis("MB9AF155R")||cpuis("MB9AF156R")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF154M")||cpuis("MB9AF155M")||cpuis("MB9AF156M")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1L")||cpuis("MB9AF1A2L")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA2L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1M")||cpuis("MB9AF1A2M")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA2M")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1N")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN31 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN30 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN29 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN28 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN27 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" else group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN31 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN30 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN29 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN28 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN27 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" endif group.byte 0x18++0x01 line.byte 0x00 "PFNS,Priority Conversion FIFO Stage Count Setup Register" rbitfld.byte 0x00 4.--5. " TEST[1:0] ,Test bits" "0,1,2,3" bitfld.byte 0x00 0.--1. " PFS[1:0] ,Priority conversion FIFO stage count setting bits" "First,Second,Third,Fourth" line.byte 0x01 "PCCR,Priority Conversion Control Register" rbitfld.byte 0x01 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty" rbitfld.byte 0x01 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full" bitfld.byte 0x01 5. " POVR ,Priority conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.byte 0x01 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared" bitfld.byte 0x01 3. " ESCE ,External trigger analog input selection bit" "P1A [2:0],External" bitfld.byte 0x01 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled" bitfld.byte 0x01 0. " PSTR ,Priority conversion start bit" "No effect,Started" hgroup.long 0x1C++0x03 hide.long 0x00 "PCFD,Priority Conversion FIFO Data Register" in group.byte 0x20++0x00 line.byte 0x00 "PCIS,Priority Conversion Input Selection Register" sif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,?..." elif (cpuis("MB9AF14?N")||cpuis("MB9AF34?N")||cpuis("MB9AFA4?N")||cpuis("MB9AFB4?N")||cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("MB9BF?2?L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..." elif (cpuis("MB9AF14?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA4?M")||cpuis("MB9AFB4?M")||cpuis("MB9AF15?M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." elif (cpuis("MB9AF105NA")||cpuis("MB9AF105RA")||cpuis("MB9AF11?N")||cpuis("MB9AF132?")||cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF1A?N")||cpuis("MB9AFAA?N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("MB9BF?2?K")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." elif (cpuis("MB9AF11?M")||cpuis("MB9AF131N")||cpuis("MB9AF131M")||cpuis("MB9AF14?L")||cpuis("MB9AF31?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA3?M")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF1A?M")||cpuis("MB9AFAA?M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,?..." elif (cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF13?L")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF131L")||cpuis("MB9AF132L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..." elif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 0.--2. " P1A[2:0] ,Priority level 1 analog input selection" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--2. " P1A[2:0] ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7" endif group.byte 0x24++0x00 line.byte 0x00 "CMPCR,A/D Comparison Control Register" bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled" bitfld.byte 0x00 6. " CMD1 ,Comparison mode 1" "=CMPD" bitfld.byte 0x00 5. " CMD0 ,Comparison mode 0" "CCH [4:0],All" textline " " sif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,?..." elif (cpuis("MB9AF14?N")||cpuis("MB9AF34?N")||cpuis("MB9AFA4?N")||cpuis("MB9AFB4?N")||cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("MB9BF?2?L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..." elif (cpuis("MB9AF14?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA4?M")||cpuis("MB9AFB4?M")||cpuis("MB9AF15?M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." elif (cpuis("MB9AF105NA")||cpuis("MB9AF105RA")||cpuis("MB9AF11?N")||cpuis("MB9AF132?")||cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF1A?N")||cpuis("MB9AFAA?N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("MB9BF?2?K")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." elif (cpuis("MB9AF11?M")||cpuis("MB9AF131N")||cpuis("MB9AF131M")||cpuis("MB9AF14?L")||cpuis("MB9AF31?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA3?M")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF1A?M")||cpuis("MB9AFAA?M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,?..." elif (cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF13?L")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF131L")||cpuis("MB9AF132L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..." elif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x26++0x01 line.word 0x00 "CMPD,A/D Comparison Value Setup Register" bitfld.word 0x00 15. " CMAD11 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 14. " CMAD10 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 13. " CMAD9 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 12. " CMAD8 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 11. " CMAD7 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 10. " CMAD6 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 9. " CMAD5 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 8. " CMAD4 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 7. " CMAD3 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 6. " CMAD2 ,A/D conversion result value setting bits" "Low,High" sif (cpuis("MB9AF131L")||cpuis("MB9AF132L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF131K")||cpuis("MB9AF132K")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF121J")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF421K")||cpuis("MB9AF421L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF42?T")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9AF154N")||cpuis("MB9AF155N")||cpuis("MB9AF156N")||cpuis("MB9AF154R")||cpuis("MB9AF155R")||cpuis("MB9AF156R")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF154M")||cpuis("MB9AF155M")||cpuis("MB9AF156M")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1L")||cpuis("MB9AF1A2L")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA2L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1M")||cpuis("MB9AF1A2M")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA2M")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1N")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 15. " TS31 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS30 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS29 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS28 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS27 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" else group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 15. " TS31 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS30 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS29 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS28 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS27 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" endif group.byte 0x30++0x01 line.byte 0x00 "ADST1,Sampling Time Setup Register" bitfld.byte 0x00 5.--7. " STX1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256" bitfld.byte 0x00 4. " ST14 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 3. " ST13 ,Sampling time setting bits" "Low,High" textline " " bitfld.byte 0x00 2. " ST12 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 1. " ST11 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 0. " ST10 ,Sampling time setting bits" "Low,High" line.byte 0x01 "ADST0,Sampling Time Setup Register" bitfld.byte 0x01 5.--7. " STX0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256" bitfld.byte 0x01 4. " ST04 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 3. " ST03 ,Sampling time setting bits" "Low,High" textline " " bitfld.byte 0x01 2. " ST02 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 1. " ST01 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 0. " ST00 ,Sampling time setting bits" "Low,High" group.byte 0x34++0x00 line.byte 0x00 "ADCT,Comparison Time Setup Register" sif (cpuis("MB9AF10?N*")||cpuis("MB9AF10?R*")||cpuis("MB9BF10*")||cpuis("MB9BF30*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")) bitfld.byte 0x00 0.--2. " CT ,Comparison time setting bits" "/2,/3,/4,/5,/6,/7,/8,/9" else hexmask.byte 0x00 0.--7. 1. " CT ,Comparison time setting bits" endif sif (!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF132K")&&!cpuis("MB9AFA3??")&&!cpuis("MB9AFAA?N")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")) group.byte 0x38++0x01 line.byte 0x00 "PRTSL,Priority Conversion Timer Trigger Selection Register" bitfld.byte 0x00 0.--3. " PRTSL[3:0] ,Scan conversion timer trigger selection bit" "No selected,Multifunction,0,1,2,3,4,5,6,7,?..." line.byte 0x01 "SCTSL,Scan Conversion Timer Trigger Selection Register" bitfld.byte 0x01 0.--3. " SCTSL[3:0] ,Scan conversion timer trigger selection bit" "No selected,Multifunction,0,1,2,3,4,5,6,7,?..." endif sif (cpuis("MB9AF13?L")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF132K")||cpuis("MB9AFA3??")||cpuis("MB9AFAA?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")) group.word 0x3C++0x01 line.word 0x00 "ADCEN,A/D Operation Enable Setup Register" hexmask.word.byte 0x00 8.--15. 1. " ENBLTIME ,Enable state transition cycle selection bits" rbitfld.word 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.word 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" elif (!cpuis("MB9AF105?A")) group.byte 0x3C++0x00 line.byte 0x00 "ADCEN,A/D Operation Enable Setup Register" bitfld.byte 0x00 4.--5. " CYCLSL ,Basic cycle selection" "36 cycles,20 cycles,9 cycles,44 cycles" rbitfld.byte 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.byte 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" else group.byte 0x3C++0x00 line.byte 0x00 "ADCEN,A/D Operation Enable Setup Register" rbitfld.byte 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.byte 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" endif width 0xb tree.end sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF14*")||cpuis("MB9AF3*")||cpuis("MB9AF?4*")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF50?N*")||cpuis("MB9BF50?R*")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF30?N*")||cpuis("MB9BF30?R*")||cpuis("MB9BF40?N*")||cpuis("MB9BF40?R*")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9BF42?S")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")) tree "Unit 1" base ad:0x40027100 width 7. group.byte 0x00++0x01 line.byte 0x00 "ADSR,A/D Status Register" bitfld.byte 0x00 7. " ADSTP ,A/D conversion forced stop bit" "No effect,Stopped" bitfld.byte 0x00 6. " FDAS ,FIFO data placement selection bit" "MSB side,LSB side" rbitfld.byte 0x00 2. " PCNS ,Priority conversion pending flag" "Not pending,Pending" textline " " rbitfld.byte 0x00 1. " PCS ,Priority conversion status flag" "Stopped,In progress" rbitfld.byte 0x00 0. " SCS ,Scan conversion status flag" "Stopped,In progress" line.byte 0x01 "ADCR,A/D Control Register" bitfld.byte 0x01 7. " SCIF ,Scan conversion interrupt request bit" "Not stored,Stored" bitfld.byte 0x01 6. " PCIF ,Priority conversion interrupt request bit" "Not stored,Stored" bitfld.byte 0x01 5. " CMPIF ,Conversion result comparison interrupt request bit" "Not satisfied,Satisfied" textline " " bitfld.byte 0x01 3. " SCIE ,Scan conversion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x01 2. " PCIE ,Priority conversion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x01 1. " CMPIE ,Conversion result comparison interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " OVRIE ,FIFO overrun interrupt enable bit" "Disabled,Enabled" group.byte 0x08++0x01 line.byte 0x00 "SFNS,Scan Conversion FIFO Stage Count Setup Register" bitfld.byte 0x00 0.--3. " SFS[3:0] ,Scan conversion FIFO stage count setting bit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" line.byte 0x01 "SCCR,Scan Conversion Control Register" rbitfld.byte 0x01 7. " SEMP ,Scan conversion FIFO empty bit" "Data remains,Empty" rbitfld.byte 0x01 6. " SFUL ,Scan conversion FIFO full bit" "Not full,Full" bitfld.byte 0x01 5. " SOVR ,Scan conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.byte 0x01 4. " SFCLR ,Scan conversion FIFO clear bit" "No effect,Cleared" bitfld.byte 0x01 2. " RPT ,Scan conversion repeat bit" "Single,Repeat" bitfld.byte 0x01 1. " SHEN ,Scan conversion timer start enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " SSTR ,Scan conversion start bit" "No effect,Started" hgroup.long 0x0C++0x03 hide.long 0x00 "SCFD,Scan Conversion FIFO Data Register" in sif (cpuis("MB9AF131L")||cpuis("MB9AF132L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF131K")||cpuis("MB9AF132K")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF121J")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF421K")||cpuis("MB9AF421L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF42?T")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9AF154N")||cpuis("MB9AF155N")||cpuis("MB9AF156N")||cpuis("MB9AF154R")||cpuis("MB9AF155R")||cpuis("MB9AF156R")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF154M")||cpuis("MB9AF155M")||cpuis("MB9AF156M")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1L")||cpuis("MB9AF1A2L")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA2L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1M")||cpuis("MB9AF1A2M")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA2M")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1N")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN31 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN30 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN29 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN28 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN27 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" else group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN31 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN30 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN29 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN28 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN27 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" endif group.byte 0x18++0x01 line.byte 0x00 "PFNS,Priority Conversion FIFO Stage Count Setup Register" rbitfld.byte 0x00 4.--5. " TEST[1:0] ,Test bits" "0,1,2,3" bitfld.byte 0x00 0.--1. " PFS[1:0] ,Priority conversion FIFO stage count setting bits" "First,Second,Third,Fourth" line.byte 0x01 "PCCR,Priority Conversion Control Register" rbitfld.byte 0x01 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty" rbitfld.byte 0x01 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full" bitfld.byte 0x01 5. " POVR ,Priority conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.byte 0x01 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared" bitfld.byte 0x01 3. " ESCE ,External trigger analog input selection bit" "P1A [2:0],External" bitfld.byte 0x01 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled" bitfld.byte 0x01 0. " PSTR ,Priority conversion start bit" "No effect,Started" hgroup.long 0x1C++0x03 hide.long 0x00 "PCFD,Priority Conversion FIFO Data Register" in group.byte 0x20++0x00 line.byte 0x00 "PCIS,Priority Conversion Input Selection Register" sif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,?..." elif (cpuis("MB9AF14?N")||cpuis("MB9AF34?N")||cpuis("MB9AFA4?N")||cpuis("MB9AFB4?N")||cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("MB9BF?2?L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..." elif (cpuis("MB9AF14?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA4?M")||cpuis("MB9AFB4?M")||cpuis("MB9AF15?M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." elif (cpuis("MB9AF105NA")||cpuis("MB9AF105RA")||cpuis("MB9AF11?N")||cpuis("MB9AF132?")||cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF1A?N")||cpuis("MB9AFAA?N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("MB9BF?2?K")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." elif (cpuis("MB9AF11?M")||cpuis("MB9AF131N")||cpuis("MB9AF131M")||cpuis("MB9AF14?L")||cpuis("MB9AF31?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA3?M")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF1A?M")||cpuis("MB9AFAA?M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,?..." elif (cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF13?L")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF131L")||cpuis("MB9AF132L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..." elif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 0.--2. " P1A[2:0] ,Priority level 1 analog input selection" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--2. " P1A[2:0] ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7" endif group.byte 0x24++0x00 line.byte 0x00 "CMPCR,A/D Comparison Control Register" bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled" bitfld.byte 0x00 6. " CMD1 ,Comparison mode 1" "=CMPD" bitfld.byte 0x00 5. " CMD0 ,Comparison mode 0" "CCH [4:0],All" textline " " sif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,?..." elif (cpuis("MB9AF14?N")||cpuis("MB9AF34?N")||cpuis("MB9AFA4?N")||cpuis("MB9AFB4?N")||cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("MB9BF?2?L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..." elif (cpuis("MB9AF14?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA4?M")||cpuis("MB9AFB4?M")||cpuis("MB9AF15?M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." elif (cpuis("MB9AF105NA")||cpuis("MB9AF105RA")||cpuis("MB9AF11?N")||cpuis("MB9AF132?")||cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF1A?N")||cpuis("MB9AFAA?N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("MB9BF?2?K")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." elif (cpuis("MB9AF11?M")||cpuis("MB9AF131N")||cpuis("MB9AF131M")||cpuis("MB9AF14?L")||cpuis("MB9AF31?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA3?M")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF1A?M")||cpuis("MB9AFAA?M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,?..." elif (cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF13?L")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF131L")||cpuis("MB9AF132L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..." elif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x26++0x01 line.word 0x00 "CMPD,A/D Comparison Value Setup Register" bitfld.word 0x00 15. " CMAD11 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 14. " CMAD10 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 13. " CMAD9 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 12. " CMAD8 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 11. " CMAD7 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 10. " CMAD6 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 9. " CMAD5 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 8. " CMAD4 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 7. " CMAD3 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 6. " CMAD2 ,A/D conversion result value setting bits" "Low,High" sif (cpuis("MB9AF131L")||cpuis("MB9AF132L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF131K")||cpuis("MB9AF132K")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF121J")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF421K")||cpuis("MB9AF421L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF42?T")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9AF154N")||cpuis("MB9AF155N")||cpuis("MB9AF156N")||cpuis("MB9AF154R")||cpuis("MB9AF155R")||cpuis("MB9AF156R")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF154M")||cpuis("MB9AF155M")||cpuis("MB9AF156M")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1L")||cpuis("MB9AF1A2L")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA2L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1M")||cpuis("MB9AF1A2M")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA2M")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1N")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 15. " TS31 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS30 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS29 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS28 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS27 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" else group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 15. " TS31 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS30 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS29 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS28 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS27 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" endif group.byte 0x30++0x01 line.byte 0x00 "ADST1,Sampling Time Setup Register" bitfld.byte 0x00 5.--7. " STX1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256" bitfld.byte 0x00 4. " ST14 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 3. " ST13 ,Sampling time setting bits" "Low,High" textline " " bitfld.byte 0x00 2. " ST12 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 1. " ST11 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 0. " ST10 ,Sampling time setting bits" "Low,High" line.byte 0x01 "ADST0,Sampling Time Setup Register" bitfld.byte 0x01 5.--7. " STX0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256" bitfld.byte 0x01 4. " ST04 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 3. " ST03 ,Sampling time setting bits" "Low,High" textline " " bitfld.byte 0x01 2. " ST02 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 1. " ST01 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 0. " ST00 ,Sampling time setting bits" "Low,High" group.byte 0x34++0x00 line.byte 0x00 "ADCT,Comparison Time Setup Register" sif (cpuis("MB9AF10?N*")||cpuis("MB9AF10?R*")||cpuis("MB9BF10*")||cpuis("MB9BF30*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")) bitfld.byte 0x00 0.--2. " CT ,Comparison time setting bits" "/2,/3,/4,/5,/6,/7,/8,/9" else hexmask.byte 0x00 0.--7. 1. " CT ,Comparison time setting bits" endif sif (!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF132K")&&!cpuis("MB9AFA3??")&&!cpuis("MB9AFAA?N")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")) group.byte 0x38++0x01 line.byte 0x00 "PRTSL,Priority Conversion Timer Trigger Selection Register" bitfld.byte 0x00 0.--3. " PRTSL[3:0] ,Scan conversion timer trigger selection bit" "No selected,Multifunction,0,1,2,3,4,5,6,7,?..." line.byte 0x01 "SCTSL,Scan Conversion Timer Trigger Selection Register" bitfld.byte 0x01 0.--3. " SCTSL[3:0] ,Scan conversion timer trigger selection bit" "No selected,Multifunction,0,1,2,3,4,5,6,7,?..." endif sif (cpuis("MB9AF13?L")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF132K")||cpuis("MB9AFA3??")||cpuis("MB9AFAA?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")) group.word 0x3C++0x01 line.word 0x00 "ADCEN,A/D Operation Enable Setup Register" hexmask.word.byte 0x00 8.--15. 1. " ENBLTIME ,Enable state transition cycle selection bits" rbitfld.word 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.word 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" elif (!cpuis("MB9AF105?A")) group.byte 0x3C++0x00 line.byte 0x00 "ADCEN,A/D Operation Enable Setup Register" bitfld.byte 0x00 4.--5. " CYCLSL ,Basic cycle selection" "36 cycles,20 cycles,9 cycles,44 cycles" rbitfld.byte 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.byte 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" else group.byte 0x3C++0x00 line.byte 0x00 "ADCEN,A/D Operation Enable Setup Register" rbitfld.byte 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.byte 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" endif width 0xb tree.end endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF31*")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")||cpuis("MB9BF50?N*")||cpuis("MB9BF50?R*")||cpuis("MB9BF51?S")||cpuis("MB9BF51?T")||cpuis("MB9BF51?N")||cpuis("MB9BF51?R")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")||cpuis("MB9BF11?S")||cpuis("MB9BF11?T")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF30?N*")||cpuis("MB9BF30?R*")||cpuis("MB9BF40?N*")||cpuis("MB9BF40?R*")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF41?N")||cpuis("MB9BF41?R")||cpuis("MB9BF41?S")||cpuis("MB9BF41?T")||cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) tree "Unit 2" base ad:0x40027200 width 7. group.byte 0x00++0x01 line.byte 0x00 "ADSR,A/D Status Register" bitfld.byte 0x00 7. " ADSTP ,A/D conversion forced stop bit" "No effect,Stopped" bitfld.byte 0x00 6. " FDAS ,FIFO data placement selection bit" "MSB side,LSB side" rbitfld.byte 0x00 2. " PCNS ,Priority conversion pending flag" "Not pending,Pending" textline " " rbitfld.byte 0x00 1. " PCS ,Priority conversion status flag" "Stopped,In progress" rbitfld.byte 0x00 0. " SCS ,Scan conversion status flag" "Stopped,In progress" line.byte 0x01 "ADCR,A/D Control Register" bitfld.byte 0x01 7. " SCIF ,Scan conversion interrupt request bit" "Not stored,Stored" bitfld.byte 0x01 6. " PCIF ,Priority conversion interrupt request bit" "Not stored,Stored" bitfld.byte 0x01 5. " CMPIF ,Conversion result comparison interrupt request bit" "Not satisfied,Satisfied" textline " " bitfld.byte 0x01 3. " SCIE ,Scan conversion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x01 2. " PCIE ,Priority conversion interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x01 1. " CMPIE ,Conversion result comparison interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " OVRIE ,FIFO overrun interrupt enable bit" "Disabled,Enabled" group.byte 0x08++0x01 line.byte 0x00 "SFNS,Scan Conversion FIFO Stage Count Setup Register" bitfld.byte 0x00 0.--3. " SFS[3:0] ,Scan conversion FIFO stage count setting bit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" line.byte 0x01 "SCCR,Scan Conversion Control Register" rbitfld.byte 0x01 7. " SEMP ,Scan conversion FIFO empty bit" "Data remains,Empty" rbitfld.byte 0x01 6. " SFUL ,Scan conversion FIFO full bit" "Not full,Full" bitfld.byte 0x01 5. " SOVR ,Scan conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.byte 0x01 4. " SFCLR ,Scan conversion FIFO clear bit" "No effect,Cleared" bitfld.byte 0x01 2. " RPT ,Scan conversion repeat bit" "Single,Repeat" bitfld.byte 0x01 1. " SHEN ,Scan conversion timer start enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " SSTR ,Scan conversion start bit" "No effect,Started" hgroup.long 0x0C++0x03 hide.long 0x00 "SCFD,Scan Conversion FIFO Data Register" in sif (cpuis("MB9AF131L")||cpuis("MB9AF132L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF131K")||cpuis("MB9AF132K")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF121J")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF421K")||cpuis("MB9AF421L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF42?T")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9AF154N")||cpuis("MB9AF155N")||cpuis("MB9AF156N")||cpuis("MB9AF154R")||cpuis("MB9AF155R")||cpuis("MB9AF156R")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF154M")||cpuis("MB9AF155M")||cpuis("MB9AF156M")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1L")||cpuis("MB9AF1A2L")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA2L")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1M")||cpuis("MB9AF1A2M")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA2M")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1N")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN31 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN30 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN29 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN28 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN27 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" else group.word 0x10++0x01 line.word 0x00 "SCIS32,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN31 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN30 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN29 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN28 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN27 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN26 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN25 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN24 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN23 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN22 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN21 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN20 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN19 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN18 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN17 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN16 ,Analog input selection bits" "Disabled,Enabled" group.word 0x14++0x01 line.word 0x00 "SCIS10,Scan Conversion Input Selection Register" bitfld.word 0x00 15. " AN15 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " AN14 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " AN13 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " AN12 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " AN11 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " AN10 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " AN9 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " AN8 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " AN7 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " AN6 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " AN5 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " AN4 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AN3 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " AN2 ,Analog input selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " AN1 ,Analog input selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " AN0 ,Analog input selection bits" "Disabled,Enabled" endif group.byte 0x18++0x01 line.byte 0x00 "PFNS,Priority Conversion FIFO Stage Count Setup Register" rbitfld.byte 0x00 4.--5. " TEST[1:0] ,Test bits" "0,1,2,3" bitfld.byte 0x00 0.--1. " PFS[1:0] ,Priority conversion FIFO stage count setting bits" "First,Second,Third,Fourth" line.byte 0x01 "PCCR,Priority Conversion Control Register" rbitfld.byte 0x01 7. " PEMP ,Priority conversion FIFO empty bit" "Not empty,Empty" rbitfld.byte 0x01 6. " PFUL ,Priority conversion FIFO full bit" "Not full,Full" bitfld.byte 0x01 5. " POVR ,Priority conversion overrun flag" "Not occurred,Occurred" textline " " bitfld.byte 0x01 4. " PFCLR ,Priority conversion FIFO clear bit" "No effect,Cleared" bitfld.byte 0x01 3. " ESCE ,External trigger analog input selection bit" "P1A [2:0],External" bitfld.byte 0x01 2. " PEEN ,Priority conversion external start enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " PHEN ,Priority conversion timer start enable bit" "Disabled,Enabled" bitfld.byte 0x01 0. " PSTR ,Priority conversion start bit" "No effect,Started" hgroup.long 0x1C++0x03 hide.long 0x00 "PCFD,Priority Conversion FIFO Data Register" in group.byte 0x20++0x00 line.byte 0x00 "PCIS,Priority Conversion Input Selection Register" sif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,?..." elif (cpuis("MB9AF14?N")||cpuis("MB9AF34?N")||cpuis("MB9AFA4?N")||cpuis("MB9AFB4?N")||cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("MB9BF?2?L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..." elif (cpuis("MB9AF14?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA4?M")||cpuis("MB9AFB4?M")||cpuis("MB9AF15?M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." elif (cpuis("MB9AF105NA")||cpuis("MB9AF105RA")||cpuis("MB9AF11?N")||cpuis("MB9AF132?")||cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF1A?N")||cpuis("MB9AFAA?N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("MB9BF?2?K")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." elif (cpuis("MB9AF11?M")||cpuis("MB9AF131N")||cpuis("MB9AF131M")||cpuis("MB9AF14?L")||cpuis("MB9AF31?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA3?M")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF1A?M")||cpuis("MB9AFAA?M")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,?..." elif (cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF13?L")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF131L")||cpuis("MB9AF132L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,?..." elif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 3.--7. " P2A[4:0] ,Priority level 2 analog input selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif sif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 0.--2. " P1A[2:0] ,Priority level 1 analog input selection" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--2. " P1A[2:0] ,Priority level 1 analog input selection" "0,1,2,3,4,5,6,7" endif group.byte 0x24++0x00 line.byte 0x00 "CMPCR,A/D Comparison Control Register" bitfld.byte 0x00 7. " CMPEN ,Conversion result comparison function operation" "Disabled,Enabled" bitfld.byte 0x00 6. " CMD1 ,Comparison mode 1" "=CMPD" bitfld.byte 0x00 5. " CMD0 ,Comparison mode 0" "CCH [4:0],All" textline " " sif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,?..." elif (cpuis("MB9AF14?N")||cpuis("MB9AF34?N")||cpuis("MB9AFA4?N")||cpuis("MB9AFB4?N")||cpuis("MB9BF*S")||cpuis("MB9BF*T")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,?..." elif (cpuis("MB9BF?2?L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,?..." elif (cpuis("MB9AF14?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA4?M")||cpuis("MB9AFB4?M")||cpuis("MB9AF15?M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." elif (cpuis("MB9AF105NA")||cpuis("MB9AF105RA")||cpuis("MB9AF11?N")||cpuis("MB9AF132?")||cpuis("MB9AF31?N")||cpuis("MB9AFA3?N")||cpuis("MB9BF?1?N")||cpuis("MB9BF?1?R")||cpuis("MB9AF1A?N")||cpuis("MB9AFAA?N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." elif (cpuis("MB9BF?2?K")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,?..." elif (cpuis("MB9AF11?M")||cpuis("MB9AF131N")||cpuis("MB9AF131M")||cpuis("MB9AF14?L")||cpuis("MB9AF31?M")||cpuis("MB9AF34?M")||cpuis("MB9AFA3?M")||cpuis("MB9AFA4?L")||cpuis("MB9AFB4?L")||cpuis("MB9AF1A?M")||cpuis("MB9AFAA?M")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,?..." elif (cpuis("MB9AF11?L")||cpuis("MB9AF31?L")||cpuis("MB9AFA3?L")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,?..." elif (cpuis("MB9AF111K")||cpuis("MB9AF112K")||cpuis("MB9AF13?L")||cpuis("MB9AF311K")||cpuis("MB9AF312K")||cpuis("MB9AF131L")||cpuis("MB9AF132L")||cpuis("MB9BF121J")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,?..." elif (cpuis("MB9AF132K")||cpuis("MB9AF131K")) bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--4. " CCH[4:0] ,Comparison target analog input channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif group.word 0x26++0x01 line.word 0x00 "CMPD,A/D Comparison Value Setup Register" bitfld.word 0x00 15. " CMAD11 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 14. " CMAD10 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 13. " CMAD9 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 12. " CMAD8 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 11. " CMAD7 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 10. " CMAD6 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 9. " CMAD5 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 8. " CMAD4 ,A/D conversion result value setting bits" "Low,High" bitfld.word 0x00 7. " CMAD3 ,A/D conversion result value setting bits" "Low,High" textline " " bitfld.word 0x00 6. " CMAD2 ,A/D conversion result value setting bits" "Low,High" sif (cpuis("MB9AF131L")||cpuis("MB9AF132L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF131K")||cpuis("MB9AF132K")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF121J")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF421K")||cpuis("MB9AF421L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF?21M")||cpuis("MB9BF?22M")||cpuis("MB9BF?24M")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BF12?S")||cpuis("MB9BF12?T")||cpuis("MB9BF42?T")||cpuis("MB9BF42?T")||cpuis("MB9BF32?S")||cpuis("MB9BF32?T")||cpuis("MB9BF52?S")||cpuis("MB9BF52?T")||cpuis("MB9AF154N")||cpuis("MB9AF155N")||cpuis("MB9AF156N")||cpuis("MB9AF154R")||cpuis("MB9AF155R")||cpuis("MB9AF156R")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF154M")||cpuis("MB9AF155M")||cpuis("MB9AF156M")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1L")||cpuis("MB9AF1A2L")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA2L")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1M")||cpuis("MB9AF1A2M")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA2M")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9AF1A1N")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2N")||cpuis("MB9BF10?N*")||cpuis("MB9BF10?R*")) group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" elif (cpuis("MB9BFD1?S")||cpuis("MB9BFD1?T")) group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 15. " TS31 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS30 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS29 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS28 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS27 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" else group.word 0x28++0x01 line.word 0x00 "ADSS23,Sampling Time Selection Register" bitfld.word 0x00 15. " TS31 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS30 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS29 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS28 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS27 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS26 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS25 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS24 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS23 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS22 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS21 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS20 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS19 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS18 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS17 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS16 ,Sampling time selection bits" "Disabled,Enabled" group.word 0x2C++0x01 line.word 0x00 "ADSS01,Sampling Time Selection Register" bitfld.word 0x00 15. " TS15 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 14. " TS14 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 13. " TS13 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " TS12 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 11. " TS11 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 10. " TS10 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 9. " TS9 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 8. " TS8 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 7. " TS7 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 6. " TS6 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 5. " TS5 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 4. " TS4 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " TS3 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 2. " TS2 ,Sampling time selection bits" "Disabled,Enabled" bitfld.word 0x00 1. " TS1 ,Sampling time selection bits" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " TS0 ,Sampling time selection bits" "Disabled,Enabled" endif group.byte 0x30++0x01 line.byte 0x00 "ADST1,Sampling Time Setup Register" bitfld.byte 0x00 5.--7. " STX1 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256" bitfld.byte 0x00 4. " ST14 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 3. " ST13 ,Sampling time setting bits" "Low,High" textline " " bitfld.byte 0x00 2. " ST12 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 1. " ST11 ,Sampling time setting bits" "Low,High" bitfld.byte 0x00 0. " ST10 ,Sampling time setting bits" "Low,High" line.byte 0x01 "ADST0,Sampling Time Setup Register" bitfld.byte 0x01 5.--7. " STX0 ,Sampling time N times setting bits" "x1,x4,x8,x16,x32,x64,x128,x256" bitfld.byte 0x01 4. " ST04 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 3. " ST03 ,Sampling time setting bits" "Low,High" textline " " bitfld.byte 0x01 2. " ST02 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 1. " ST01 ,Sampling time setting bits" "Low,High" bitfld.byte 0x01 0. " ST00 ,Sampling time setting bits" "Low,High" group.byte 0x34++0x00 line.byte 0x00 "ADCT,Comparison Time Setup Register" sif (cpuis("MB9AF10?N*")||cpuis("MB9AF10?R*")||cpuis("MB9BF10*")||cpuis("MB9BF30*")||cpuis("MB9BF40*")||cpuis("MB9BF50*")) bitfld.byte 0x00 0.--2. " CT ,Comparison time setting bits" "/2,/3,/4,/5,/6,/7,/8,/9" else hexmask.byte 0x00 0.--7. 1. " CT ,Comparison time setting bits" endif sif (!cpuis("MB9AF13?L")&&!cpuis("MB9AF13?M")&&!cpuis("MB9AF13?N")&&!cpuis("MB9AF132K")&&!cpuis("MB9AFA3??")&&!cpuis("MB9AFAA?N")&&!cpuis("MB9AF1A?M")&&!cpuis("MB9AF1A?N")&&!cpuis("MB9AF1A?L")&&!cpuis("MB9AFAA?L")&&!cpuis("MB9AFAA?M")) group.byte 0x38++0x01 line.byte 0x00 "PRTSL,Priority Conversion Timer Trigger Selection Register" bitfld.byte 0x00 0.--3. " PRTSL[3:0] ,Scan conversion timer trigger selection bit" "No selected,Multifunction,0,1,2,3,4,5,6,7,?..." line.byte 0x01 "SCTSL,Scan Conversion Timer Trigger Selection Register" bitfld.byte 0x01 0.--3. " SCTSL[3:0] ,Scan conversion timer trigger selection bit" "No selected,Multifunction,0,1,2,3,4,5,6,7,?..." endif sif (cpuis("MB9AF13?L")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF132K")||cpuis("MB9AFA3??")||cpuis("MB9AFAA?N")||cpuis("MB9AF1A?M")||cpuis("MB9AF1A?N")||cpuis("MB9AF1A?L")||cpuis("MB9AFAA?L")||cpuis("MB9AFAA?M")) group.word 0x3C++0x01 line.word 0x00 "ADCEN,A/D Operation Enable Setup Register" hexmask.word.byte 0x00 8.--15. 1. " ENBLTIME ,Enable state transition cycle selection bits" rbitfld.word 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.word 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" elif (!cpuis("MB9AF105?A")) group.byte 0x3C++0x00 line.byte 0x00 "ADCEN,A/D Operation Enable Setup Register" bitfld.byte 0x00 4.--5. " CYCLSL ,Basic cycle selection" "36 cycles,20 cycles,9 cycles,44 cycles" rbitfld.byte 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.byte 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" else group.byte 0x3C++0x00 line.byte 0x00 "ADCEN,A/D Operation Enable Setup Register" rbitfld.byte 0x00 1. " READY ,A/D operation enable state bit" "Disabled,Enabled" bitfld.byte 0x00 0. " ENBL ,A/D operation enable bit" "Disabled,Enabled" endif width 0xb tree.end endif tree.end sif (cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AFA3??")||cpuis("MB9AF1A1L")||cpuis("MB9AF1A1M")||cpuis("MB9AF1A1N")||cpuis("MB9AF1A2L")||cpuis("MB9AF1A2M")||cpuis("MB9AF1A2N")||cpuis("MB9AFAA1L")||cpuis("MB9AFAA1M")||cpuis("MB9AFAA1N")||cpuis("MB9AFAA2L")||cpuis("MB9AFAA2M")||cpuis("MB9AFAA2N")||cpuis("MB9BF124K")||cpuis("MB9BF124L")||cpuis("MB9BF124M")||cpuis("MB9BF122K")||cpuis("MB9BF122L")||cpuis("MB9BF122M")||cpuis("MB9BF121K")||cpuis("MB9BF121L")||cpuis("MB9BF121M")||cpuis("MB9BF324K")||cpuis("MB9BF324L")||cpuis("MB9BF324M")||cpuis("MB9BF322K")||cpuis("MB9BF322L")||cpuis("MB9BF322M")||cpuis("MB9BF321K")||cpuis("MB9BF321L")||cpuis("MB9BF321M")||cpuis("MB9BF524K")||cpuis("MB9BF524L")||cpuis("MB9BF524M")||cpuis("MB9BF522K")||cpuis("MB9BF522L")||cpuis("MB9BF522M")||cpuis("MB9BF521K")||cpuis("MB9BF521L")||cpuis("MB9BF521M")||cpuis("MB9AF421K")||cpuis("MB9AF421L")||cpuis("MB9AF121K")||cpuis("MB9AF121L")||cpuis("MB9BF429S")||cpuis("MB9BF429T")||cpuis("MB9BF428S")||cpuis("MB9BF428T")||cpuis("MB9BF329S")||cpuis("MB9BF329T")||cpuis("MB9BF328S")||cpuis("MB9BF328T")||cpuis("MB9BF129S")||cpuis("MB9BF129T")||cpuis("MB9BF128S")||cpuis("MB9BF128T")||cpuis("MB9BF529S")||cpuis("MB9BF529T")||cpuis("MB9BF528S")||cpuis("MB9BF528T")) tree "10-bit DAC (10-bit D/A Converter)" base ad:0x40028000 sif (cpuis("MB9AF121K")||cpuis("MB9AF121L")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) width 7. tree "Channel 0" group.word 0x0++0x01 line.word 0x00 "DADR0,D/A Data Register 0" hexmask.word 0x00 0.--9. 1. " DA ,D/A Data Register" group.byte 0x2++0x00 line.byte 0x00 "DACR0,D/A Control Register 0" bitfld.byte 0x00 0. " DAE ,D/A converter operation enable" "Disabled,Enabled" tree.end width 0xb else width 7. tree "Channel 0" group.word 0x0++0x01 line.word 0x00 "DADR0,D/A Data Register 0" hexmask.word 0x00 0.--9. 1. " DA ,D/A Data Register" group.byte 0x2++0x00 line.byte 0x00 "DACR0,D/A Control Register 0" bitfld.byte 0x00 0. " DAE ,D/A converter operation enable" "Disabled,Enabled" tree.end tree "Channel 1" group.word 0x4++0x01 line.word 0x00 "DADR1,D/A Data Register 1" hexmask.word 0x00 0.--9. 1. " DA ,D/A Data Register" group.byte 0x6++0x00 line.byte 0x00 "DACR1,D/A Control Register 1" bitfld.byte 0x00 0. " DAE ,D/A converter operation enable" "Disabled,Enabled" tree.end width 0xb endif tree.end endif sif (cpuis("MB9AFA*")||cpuis("MB9AFB*")||cpuis("MB9AFAA*")) tree "LCDC (LCD Controller)" base ad:0x40032000 width 13. group.byte 0x00++0x01 line.byte 0x00 "LCDCC1,LCDC Control Register 1" bitfld.byte 0x00 6. " LCDEN ,Timer mode operation enable" "Disabled,Enabled" bitfld.byte 0x00 5. " VSEL ,LCD drive power control" "External,Internal" sif (cpuis("MB9AFA3*")||cpuis("MB9AFAA*")) bitfld.byte 0x00 2.--4. " MS ,LCD controller display mode selection" "Disabled,4 COM 1/2 duty,4 COM 1/3 duty,4 COM 1/4 duty,8 COM 1/8 duty,8 COM 1/8 duty,8 COM 1/8 duty,8 COM 1/8 duty" else bitfld.byte 0x00 2.--4. " MS ,LCD controller display mode selection" "Disabled,,,,8 COM 1/8 duty,8 COM 1/8 duty,8 COM 1/8 duty,8 COM 1/8 duty" endif line.byte 0x01 "LCDCC2,LCDC Control Register 2" bitfld.byte 0x01 5. " RSEL ,Divider resistor value selection" "100k ohms,10k ohms" bitfld.byte 0x01 4. " BLS8 ,8 COM mode bias selection" "1/3,1/4" bitfld.byte 0x01 3. " INV ,Reverse display control" "Not reversed,Reversed" textline " " bitfld.byte 0x01 2. " BK ,Blank display control" "Data,Blank" bitfld.byte 0x01 1. " LCDIEN ,Interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " LCDIF ,Interrupt request detection" "No interrupt,Interrupt" if (((d.b(ad:0x40032000))&0x20)==0x20) group.byte 0x02++0x00 line.byte 0x00 "LCDCC3,LCDC Control Register 3" bitfld.byte 0x00 7. " PICTL ,I/O port input not cut off" "No,Yes" bitfld.byte 0x00 6. " BLSEL ,Blink interval selection" "Sub-clock/2^14,Sub-clock/2^15" bitfld.byte 0x00 5. " VE4 ,VV4 selection bit" ",LCD" bitfld.byte 0x00 4. " VE3 ,VV3 selection bit" "GPIO,LCD" textline " " bitfld.byte 0x00 3. " VE2 ,VV2 selection bit" "GPIO,LCD" bitfld.byte 0x00 2. " VE1 ,VV1 selection bit" "GPIO,LCD" bitfld.byte 0x00 1. " VE0 ,VV0 selection bit" "GPIO,LCD" else group.byte 0x02++0x00 line.byte 0x00 "LCDCC3,LCDC Control Register 3" bitfld.byte 0x00 7. " PICTL ,I/O port input cut off" "No,Yes" bitfld.byte 0x00 6. " BLSEL ,Blink interval selection" "Sub-clock/2^14,Sub-clock/2^15" bitfld.byte 0x00 5. " VE4 ,VV4 selection bit" "GPIO,LCD" bitfld.byte 0x00 4. " VE3 ,VV3 selection bit" "GPIO,LCD" textline " " bitfld.byte 0x00 3. " VE2 ,VV2 selection bit" "GPIO,LCD" bitfld.byte 0x00 2. " VE1 ,VV1 selection bit" "GPIO,LCD" bitfld.byte 0x00 1. " VE0 ,VV0 selection bit" "GPIO,LCD" endif group.long 0x04++0x0B line.long 0x00 "LCDC_PSR,LCDC Clock Prescaler Register" bitfld.long 0x00 22. " CLKSEL ,Source clock selection" "Sub-clock,PCLK" hexmask.long.tbyte 0x00 0.--21. 1. " CLKDIV ,LCDC clock division ratio" line.long 0x04 "LCDC_COMEN,LCDC COM Output Enable Register" bitfld.long 0x04 7. " COM7 ,Dual purpose COM/SEG port control" "GPIO,COM7/SEG07" bitfld.long 0x04 6. " COM6 ,Dual purpose COM/SEG port control" "GPIO,COM6/SEG06" textline " " bitfld.long 0x04 5. " COM5 ,Dual purpose COM/SEG port control" "GPIO,COM5/SEG05" bitfld.long 0x04 4. " COM4 ,Dual purpose COM/SEG port control" "GPIO,COM4/SEG04" textline " " bitfld.long 0x04 3. " COM3 ,Dual purpose COM port control" "GPIO,COM3" bitfld.long 0x04 2. " COM2 ,Dual purpose COM port control" "GPIO,COM2" textline " " bitfld.long 0x04 1. " COM1 ,Dual purpose COM port control" "GPIO,COM1" bitfld.long 0x04 0. " COM0 ,Dual purpose COM port control" "GPIO,COM0" line.long 0x08 "LCDC_SEGEN1,LCDC SEG Output Enable Register 1" sif (cpuis("MB9AFA4?M")||cpuis("MB9AFA4?N")||cpuis("MB9AFA3??")||cpuis("MB9AFB4?M")||cpuis("MB9AFB4?N")||cpuis("MB9AFAA*")) sif (!cpuis("MB9AFA3?L")&&!cpuis("MB9AFAA?L")) bitfld.long 0x08 31. " SEG31 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG31/On" bitfld.long 0x08 30. " SEG30 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG30/On" textline " " bitfld.long 0x08 29. " SEG29 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG29/On" bitfld.long 0x08 28. " SEG28 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG28/On" textline " " bitfld.long 0x08 27. " SEG27 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG27/On" bitfld.long 0x08 26. " SEG26 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG26/On" textline " " bitfld.long 0x08 25. " SEG25 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG25/On" bitfld.long 0x08 24. " SEG24 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG24/On" textline " " endif bitfld.long 0x08 23. " SEG23 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG23/On" bitfld.long 0x08 22. " SEG22 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG22/On" textline " " bitfld.long 0x08 21. " SEG21 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG21/On" bitfld.long 0x08 20. " SEG20 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG20/On" textline " " endif bitfld.long 0x08 19. " SEG19 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG19/On" bitfld.long 0x08 18. " SEG18 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG18/On" textline " " bitfld.long 0x08 17. " SEG17 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG17/On" bitfld.long 0x08 16. " SEG16 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG16/On" textline " " bitfld.long 0x08 15. " SEG15 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG15/On" bitfld.long 0x08 14. " SEG14 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG14/On" textline " " bitfld.long 0x08 13. " SEG13 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG13/On" bitfld.long 0x08 12. " SEG12 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG12/On" textline " " bitfld.long 0x08 11. " SEG11 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG11/On" bitfld.long 0x08 10. " SEG10 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG10/On" textline " " bitfld.long 0x08 9. " SEG09 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG09/On" bitfld.long 0x08 8. " SEG08 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG08/On" textline " " bitfld.long 0x08 7. " SEG07 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG07/On" bitfld.long 0x08 6. " SEG06 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG06/On" textline " " bitfld.long 0x08 5. " SEG05 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG05/On" bitfld.long 0x08 4. " SEG04 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG04/On" textline " " bitfld.long 0x08 3. " SEG03 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG03/On" bitfld.long 0x08 2. " SEG02 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG02/On" textline " " bitfld.long 0x08 1. " SEG01 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG01/On" bitfld.long 0x08 0. " SEG00 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG00/On" sif (!cpuis("MB9AFA3?L")&&!cpuis("MB9AFA4?L")&&!cpuis("MB9AFB4?L")&&!cpuis("MB9AFAA?L")) group.long 0x10++0x03 line.long 0x00 "LCDC_SEGEN2,LCDC SEG Output Enable Register 2" sif (cpuis("MB9AF?4?N")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) sif (!cpuis("MB9AFA3?M")&&!cpuis("MB9AFAA?M")) sif (!cpuis("MB9AFA4??")&&!cpuis("MB9AFB4?N")) bitfld.long 0x00 11. " SEG43 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG43/On" bitfld.long 0x00 10. " SEG42 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG42/On" textline " " bitfld.long 0x00 9. " SEG41 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG41/On" bitfld.long 0x00 8. " SEG40 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG40/On" textline " " endif bitfld.long 0x00 7. " SEG39 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG39/On" bitfld.long 0x00 6. " SEG38 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG38/On" textline " " bitfld.long 0x00 5. " SEG37 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG37/On" endif sif (cpuis("MB9AFA3?M")||cpuis("MB9AFAA?M")) bitfld.long 0x00 4. " SEG36 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG36/On" else bitfld.long 0x00 4. " SEG36 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG36/On" endif textline " " bitfld.long 0x00 3. " SEG35 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG35/On" bitfld.long 0x00 2. " SEG34 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG34/On" textline " " bitfld.long 0x00 1. " SEG33 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG33/On" endif sif (cpuis("MB9AF?4??")||cpuis("MB9AFA3?M")||cpuis("MB9AFA3?N")||cpuis("MB9AFAA?M")||cpuis("MB9AFAA?N")) sif (cpuis("MB9AF?4?M")) bitfld.long 0x00 0. " SEG32 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG32/On" else bitfld.long 0x00 0. " SEG32 ,Dual purpose SEG port control [output/analog switches]" "GPIO/Off,SEG32/On" endif endif else hgroup.long 0x10++0x3 hide.long 0x00 "LCDC_SEGEN2,LCDC SEG Output Enable Register 2" endif if (((d.b(ad:0x40032000))&0x10)==0x10) group.word 0x14++0x01 line.word 0x00 "LCDC_BLINK,LCDC Blink Setting Register" bitfld.word 0x00 15. " BLD15 ,Blink operation control bit 15" "Disabled,SEG01-COM7" bitfld.word 0x00 14. " BLD14 ,Blink operation control bit 14" "Disabled,SEG01-COM6" textline " " bitfld.word 0x00 13. " BLD13 ,Blink operation control bit 13" "Disabled,SEG01-COM5" bitfld.word 0x00 12. " BLD12 ,Blink operation control bit 12" "Disabled,SEG01-COM4" textline " " bitfld.word 0x00 11. " BLD11 ,Blink operation control bit 11" "Disabled,SEG01-COM3" bitfld.word 0x00 10. " BLD10 ,Blink operation control bit 10" "Disabled,SEG01-COM2" textline " " bitfld.word 0x00 9. " BLD9 ,Blink operation control bit 9" "Disabled,SEG01-COM1" bitfld.word 0x00 8. " BLD8 ,Blink operation control bit 8" "Disabled,SEG01-COM0" textline " " bitfld.word 0x00 7. " BLD7 ,Blink operation control bit 7" "Disabled,SEG00-COM7" bitfld.word 0x00 6. " BLD6 ,Blink operation control bit 6" "Disabled,SEG00-COM6" textline " " bitfld.word 0x00 5. " BLD5 ,Blink operation control bit 5" "Disabled,SEG00-COM5" bitfld.word 0x00 4. " BLD4 ,Blink operation control bit 4" "Disabled,SEG00-COM4" textline " " bitfld.word 0x00 3. " BLD3 ,Blink operation control bit 3" "Disabled,SEG00-COM3" bitfld.word 0x00 2. " BLD2 ,Blink operation control bit 2" "Disabled,SEG00-COM2" textline " " bitfld.word 0x00 1. " BLD1 ,Blink operation control bit 1" "Disabled,SEG00-COM1" bitfld.word 0x00 0. " BLD0 ,Blink operation control bit 0" "Disabled,SEG00-COM0" else group.word 0x14++0x01 line.word 0x00 "LCDC_BLINK,LCDC Blink Setting Register" bitfld.word 0x00 15. " BLD15 ,Blink operation control bit 15" "Disabled,SEG03-COM3" bitfld.word 0x00 14. " BLD14 ,Blink operation control bit 14" "Disabled,SEG03-COM2" textline " " bitfld.word 0x00 13. " BLD13 ,Blink operation control bit 13" "Disabled,SEG03-COM1" bitfld.word 0x00 12. " BLD12 ,Blink operation control bit 12" "Disabled,SEG03-COM0" textline " " bitfld.word 0x00 11. " BLD11 ,Blink operation control bit 11" "Disabled,SEG02-COM3" bitfld.word 0x00 10. " BLD10 ,Blink operation control bit 10" "Disabled,SEG02-COM2" textline " " bitfld.word 0x00 9. " BLD9 ,Blink operation control bit 9" "Disabled,SEG02-COM1" bitfld.word 0x00 8. " BLD8 ,Blink operation control bit 8" "Disabled,SEG02-COM0" textline " " bitfld.word 0x00 7. " BLD7 ,Blink operation control bit 7" "Disabled,SEG01-COM3" bitfld.word 0x00 6. " BLD6 ,Blink operation control bit 6" "Disabled,SEG01-COM2" textline " " bitfld.word 0x00 5. " BLD5 ,Blink operation control bit 5" "Disabled,SEG01-COM1" bitfld.word 0x00 4. " BLD4 ,Blink operation control bit 4" "Disabled,SEG01-COM0" textline " " bitfld.word 0x00 3. " BLD3 ,Blink operation control bit 3" "Disabled,SEG00-COM3" bitfld.word 0x00 2. " BLD2 ,Blink operation control bit 2" "Disabled,SEG00-COM2" textline " " bitfld.word 0x00 1. " BLD1 ,Blink operation control bit 1" "Disabled,SEG00-COM1" bitfld.word 0x00 0. " BLD0 ,Blink operation control bit 0" "Disabled,SEG00-COM0" endif tree "LCD RAM" group.byte 0x1C++0x00 line.byte 0x00 "LCDRAM00,Display Data Memory Register 00" group.byte 0x1D++0x00 line.byte 0x00 "LCDRAM01,Display Data Memory Register 01" group.byte 0x1E++0x00 line.byte 0x00 "LCDRAM02,Display Data Memory Register 02" group.byte 0x1F++0x00 line.byte 0x00 "LCDRAM03,Display Data Memory Register 03" group.byte 0x20++0x00 line.byte 0x00 "LCDRAM04,Display Data Memory Register 04" group.byte 0x21++0x00 line.byte 0x00 "LCDRAM05,Display Data Memory Register 05" group.byte 0x22++0x00 line.byte 0x00 "LCDRAM06,Display Data Memory Register 06" group.byte 0x23++0x00 line.byte 0x00 "LCDRAM07,Display Data Memory Register 07" group.byte 0x24++0x00 line.byte 0x00 "LCDRAM08,Display Data Memory Register 08" group.byte 0x25++0x00 line.byte 0x00 "LCDRAM09,Display Data Memory Register 09" group.byte 0x26++0x00 line.byte 0x00 "LCDRAM10,Display Data Memory Register 010" group.byte 0x27++0x00 line.byte 0x00 "LCDRAM11,Display Data Memory Register 011" group.byte 0x28++0x00 line.byte 0x00 "LCDRAM12,Display Data Memory Register 012" group.byte 0x29++0x00 line.byte 0x00 "LCDRAM13,Display Data Memory Register 013" group.byte 0x2A++0x00 line.byte 0x00 "LCDRAM14,Display Data Memory Register 014" group.byte 0x2B++0x00 line.byte 0x00 "LCDRAM15,Display Data Memory Register 015" group.byte 0x2C++0x00 line.byte 0x00 "LCDRAM16,Display Data Memory Register 016" group.byte 0x2D++0x00 line.byte 0x00 "LCDRAM17,Display Data Memory Register 017" group.byte 0x2E++0x00 line.byte 0x00 "LCDRAM18,Display Data Memory Register 018" group.byte 0x2F++0x00 line.byte 0x00 "LCDRAM19,Display Data Memory Register 019" group.byte 0x30++0x00 line.byte 0x00 "LCDRAM20,Display Data Memory Register 020" group.byte 0x31++0x00 line.byte 0x00 "LCDRAM21,Display Data Memory Register 021" group.byte 0x32++0x00 line.byte 0x00 "LCDRAM22,Display Data Memory Register 022" group.byte 0x33++0x00 line.byte 0x00 "LCDRAM23,Display Data Memory Register 023" group.byte 0x34++0x00 line.byte 0x00 "LCDRAM24,Display Data Memory Register 024" group.byte 0x35++0x00 line.byte 0x00 "LCDRAM25,Display Data Memory Register 025" group.byte 0x36++0x00 line.byte 0x00 "LCDRAM26,Display Data Memory Register 026" group.byte 0x37++0x00 line.byte 0x00 "LCDRAM27,Display Data Memory Register 027" group.byte 0x38++0x00 line.byte 0x00 "LCDRAM28,Display Data Memory Register 028" group.byte 0x39++0x00 line.byte 0x00 "LCDRAM29,Display Data Memory Register 029" group.byte 0x3A++0x00 line.byte 0x00 "LCDRAM30,Display Data Memory Register 030" group.byte 0x3B++0x00 line.byte 0x00 "LCDRAM31,Display Data Memory Register 031" group.byte 0x3C++0x00 line.byte 0x00 "LCDRAM32,Display Data Memory Register 032" group.byte 0x3D++0x00 line.byte 0x00 "LCDRAM33,Display Data Memory Register 033" group.byte 0x3E++0x00 line.byte 0x00 "LCDRAM34,Display Data Memory Register 034" group.byte 0x3F++0x00 line.byte 0x00 "LCDRAM35,Display Data Memory Register 035" group.byte 0x40++0x00 line.byte 0x00 "LCDRAM36,Display Data Memory Register 036" group.byte 0x41++0x00 line.byte 0x00 "LCDRAM37,Display Data Memory Register 037" group.byte 0x42++0x00 line.byte 0x00 "LCDRAM38,Display Data Memory Register 038" group.byte 0x43++0x00 line.byte 0x00 "LCDRAM39,Display Data Memory Register 039" tree.end width 0xb tree.end endif tree.open "MFSI (Multi-functional Serial Interface)" sif cpuis("MB9AF105?A")||cpuis("MB9AF11?L")||cpuis("MB9AF11?M")||cpuis("MB9AF11?N")||cpuis("MB9AF13?L")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF31?L")||cpuis("MB9AF31?M")||cpuis("MB9AF31?N")||cpuis("MB9AFA3*")||cpuis("MB9BF11?N")||cpuis("MB9BF11?R")||cpuis("MB9BF31?N")||cpuis("MB9BF31?R")||cpuis("MB9BF51*") tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 4" base ad:0x40038400 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038400+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038400+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038400+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 6" base ad:0x40038600 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038600+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038600+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038600+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 7" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038700+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038700+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038700+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end elif cpu()==("MB9AF111K")||cpu()==("MB9AF112K")||cpu()==("MB9AF311K")||cpu()==("MB9AF312K") tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end elif cpu()==("MB9AF32?K")||cpu()==("MB9AF52?K") tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end elif cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M") tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 4" base ad:0x40038400 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038400+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038400+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038400+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end tree "Channel 6" base ad:0x40038600 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038600+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038600+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038600+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 7" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038700+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038700+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038700+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end elif (cpu()=="MB9AF132K") tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end elif cpu()=="MB9BF121J" tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end elif (cpuis("MB9BF529*")||cpuis("MB9BF528*")||cpuis("MB9BF429*")||cpuis("MB9BF428*")||cpuis("MB9BF329*")||cpuis("MB9BF328*")||cpuis("MB9BF129*")||cpuis("MB9BF128*")) tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 4" base ad:0x40038400 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038400+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038400+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038400+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end tree "Channel 6" base ad:0x40038600 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038600+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038600+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038600+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 7" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038700+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038700+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038700+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 8" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038800+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038800+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038800))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038800+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038800+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038800+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038800+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038800+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038800+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038800+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 9" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038900+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038900+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038900))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038900+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038900+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038900+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038900+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038900+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038900+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038900+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 10" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038A00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038A00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038A00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038A00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038A00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038A00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038A00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038A00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038A00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 11" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038B00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038B00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038B00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038B00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038B00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038B00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038B00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038B00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038B00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 12" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038C00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038C00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038C00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038C00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038C00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038C00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038C00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038C00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038C00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 13" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038D00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038D00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038D00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038D00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038D00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038D00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038D00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038D00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038D00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 14" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038E00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038E00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038E00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038E00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038E00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038E00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038E00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038E00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038E00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 15" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038F00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038F00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038F00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038F00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038F00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038F00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038F00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038F00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038F00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end elif (cpuis("MB9AF121*")||cpuis("MB9AF421*")) tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end elif (cpuis("MB9AF15*")) tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 4" base ad:0x40038400 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038400+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038400+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038400+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 6" base ad:0x40038600 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038600+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038600+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038600+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 7" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038700+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038700+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038700+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 8" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038800+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038800+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038800))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038800+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038800+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038800+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038800+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038800+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038800+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038800+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 9" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038900+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038900+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038900))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038900+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038900+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038900+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038900+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038900+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038900+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038900+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end sif (cpuis("MB9AF15?R")||cpuis("MB9AF15?N")) tree "Channel 10" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038A00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038A00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038A00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038A00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038A00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038A00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038A00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038A00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038A00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 11" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038B00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038B00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038B00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038B00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038B00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038B00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038B00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038B00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038B00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 12" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038C00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038C00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038C00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038C00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038C00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038C00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038C00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038C00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038C00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 13" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038D00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038D00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038D00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038D00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038D00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038D00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038D00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038D00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038D00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end endif sif (cpuis("MB9AF15?R")) tree "Channel 14" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038E00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038E00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038E00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038E00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038E00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038E00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038E00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038E00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038E00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 15" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038F00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038F00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038F00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038F00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038F00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038F00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038F00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038F00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038F00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end endif elif (cpu()=="MB9BF129T")||(cpu()=="MB9BF129S")||(cpu()=="MB9BF128T")||(cpu()=="MB9BF128S") tree "Channel 0" base 0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 1" base 0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 2" base 0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 3" base 0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 4" base 0x40038400 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038400+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038400+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038400+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 5" base 0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. tree.end tree "Channel 6" base 0x40038600 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038600+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038600+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038600+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 7" base 0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038700+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038700+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038700+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 8" base 0x40038800 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038800+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038800+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038800))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038800+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038800+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038800+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038800+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038800+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038800+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038800+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038800))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038800+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038800+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038800+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038800+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038800+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038800+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 9" base 0x40038900 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038900+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038900+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038900))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038900+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038900+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038900+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038900+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038900+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038900+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038900+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038900))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038900+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038900+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038900+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038900+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038900+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038900+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 10" base 0x40038A00 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038A00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038A00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038A00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038A00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038A00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038A00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038A00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038A00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038A00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038A00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038A00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038A00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038A00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038A00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038A00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038A00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 11" base 0x40038B00 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038B00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038B00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038B00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038B00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038B00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038B00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038B00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038B00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038B00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038B00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038B00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038B00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038B00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038B00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038B00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038B00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 12" base 0x40038C00 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038C00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038C00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038C00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038C00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038C00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038C00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038C00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038C00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038C00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038C00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038C00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038C00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038C00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038C00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038C00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038C00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 13" base 0x40038D00 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038D00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038D00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038D00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038D00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038D00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038D00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038D00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038D00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038D00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038D00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038D00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038D00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038D00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038D00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038D00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038D00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 14" base 0x40038E00 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038E00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038E00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038E00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038E00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038E00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038E00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038E00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038E00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038E00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038E00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038E00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038E00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038E00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038E00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038E00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038E00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 15" base 0x40038F00 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038F00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038F00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038F00))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038F00+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038F00+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038F00+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038F00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038F00+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038F00+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038F00))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038F00+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038F00+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038F00+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038F00+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038F00+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038F00+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end else tree "Channel 0" base ad:0x40038000 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038000))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038000+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038000+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038000+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038000+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038000+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038000+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038000))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038000+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038000+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038000+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038000+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038000+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038000+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 1" base ad:0x40038100 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038100))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038100+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038100+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038100+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038100+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038100+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038100+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038100))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038100+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038100+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038100+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038100+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038100+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038100+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 2" base ad:0x40038200 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038200))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038200+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038200+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038200+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038200+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038200+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038200+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038200))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038200+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038200+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038200+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038200+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038200+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038200+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 3" base ad:0x40038300 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif endif else if (((d.b(ad:0x40038300))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038300+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038300+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038300+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038300+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038300+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038300+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038300))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038300+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) sif (cpu()=="MB9AF132K"||cpu()=="MB9AF131K") group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" ",,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038300+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038300+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038300+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038300+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038300+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. tree.end tree "Channel 4" base ad:0x40038400 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038400))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038400+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038400+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038400+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038400+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038400+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038400+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038400))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038400+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038400+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038400+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038400+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038400+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038400+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 5" base ad:0x40038500 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." endif else if (((d.b(ad:0x40038500))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038500+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038500+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if ((((d.b(ad:0x40038500+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038500+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038500+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif else if (((d.b(ad:0x40038500+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038500))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038500+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else sif ((cpu()=="MB9AF111K")||(cpu()=="MB9AF112K")||(cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,,LIN,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif endif if (((d.b(ad:0x40038500+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038500+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038500+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038500+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038500+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 6" base ad:0x40038600 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038600))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038600+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038600+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038600+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038600+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038600+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038600+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038600))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038600+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038600+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038600+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038600+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038600+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038600+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end tree "Channel 7" base ad:0x40038700 width 8. sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." endif else if (((d.b(ad:0x40038700))&0xE0)==0x00) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x20) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=1)" "3,4" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit (ESBL=0)" "1,2" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " PE ,Parity error flag bit" "No error,Error" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700))&0xE0)==0x0) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 4. " PEN ,Parity enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " P ,Parity select bit" "Even,Odd" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " FLWEN ,Flow control enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-3,2-4" bitfld.byte 0x00 5. " INV ,Inverted serial data format bit" "Normal,Inverted" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,,,7-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x40) width 9. group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " SPI ,SPI corresponding bit" "Normal,SPI" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" sif ((cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SCINV ,Serial clock invert bit" "Not inverted,Inverted" bitfld.byte 0x00 2. " BDS ,Transfer direction select bit" "LSB,MSB" textline " " bitfld.byte 0x00 1. " SCKE ,Master mode serial clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" textline " " bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if (((d.b(ad:0x40038700+0x5))&0x1)==0x1) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 7. " SOP ,Serial output pin set bit" "No effect,High state" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 3.--4. " WT[1:0] ,Data transmit/receive wait select bits" "0,1,2,3" bitfld.byte 0x00 0.--2. " L[2:0] ,Data length select bit" "8-bit,5-bit,6-bit,7-bit,9-bit,?..." endif hgroup.word 0x8++0x1 hide.word 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x60) width 9. if (((d.b(ad:0x40038700+0x1))&0x40)==0x0) group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 5. " LBR ,LIN Break Field setting bit" "No effect,LIN Break" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" else group.byte 0x1++0x0 line.byte 0x0 "SCR,Serial Control Register" bitfld.byte 0x00 7. " UPCL ,Programmable Clear bit" "No effect,Clear" bitfld.byte 0x00 6. " MS ,Master/Slave function select bit" "Master,Slave" bitfld.byte 0x00 4. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " RXE ,Receive operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " TXE ,Transmit operation enable bit" "Disabled,Enabled" endif sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")) if ((((d.b(ad:0x40038700+0x4))&0x40)==0x40)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" elif ((((d.b(ad:0x40038700+0x4))&0x40)==0x00)&&(((d.b(ad:0x40038700+0x1))&0x01)==0x00)) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif else if (((d.b(ad:0x40038700+0x4))&0x40)==0x40) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "3,4" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "INT,SIN" bitfld.byte 0x00 3. " SBL ,Stop bit length select bit" "1,2" bitfld.byte 0x00 0. " SOE ,Serial data output enable bit" "Disabled,Enabled" endif endif group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " LBD ,LIN Break field detection flag bit (during writing/during reading)" "Clear/Not detected,No effect/Detected" bitfld.byte 0x00 4. " FRE ,Framing error flag bit" "No error,Error" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No error,Error" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x0)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2.--3. " LBL[1:0] ,LIN Break field length select bits" "13-bit,14-bit,15-bit,16-bit" bitfld.byte 0x00 0.--1. " DEL[1:0] ,LIN Break delimiter length select bits" "1-bit,2-bit,3-bit,4-bit" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 6. " ESBL ,Extension stop bit length select bit" "1-2,3-4" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" else group.byte 0x4++0x0 line.byte 0x0 "ESCR,Extended Communication Control Register" bitfld.byte 0x00 4. " LBIE ,LIN Break field detect interrupt enable bit" "Disabled,Enabled" endif wgroup.byte 0x8++0x0 line.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" bitfld.word 0x00 15. " EXT ,External clock select bit" "Internal,External" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. elif (((d.b(ad:0x40038700))&0xE0)==0x80) width 9. if ((((d.b(ad:0x40038700+0x1))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x1))&0x40)==0x40)) group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,?..." bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" else group.byte 0x1++0x0 line.byte 0x0 "IBCR,I2C Bus Control Register" bitfld.byte 0x00 7. " MSS ,Master/Slave select bit" "Slave,Master" bitfld.byte 0x00 6. " ACT/SCC ,Operation flag/iteration start condition generation bit" "No effect/Idle,Start/Busy" bitfld.byte 0x00 5. " ACKE ,Data byte acknowledge enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " WSEL ,Wait selection bit" "9 bits,8 bits" textline " " bitfld.byte 0x00 3. " CNDE ,Condition detection interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " INTE ,Interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 1. " BER ,Bus error flag bit" "No error,Error" bitfld.byte 0x00 0. " INT ,Interrupt flag bit (during writing/during reading)" "Clear/No request,No effect/Request" endif sif ((cpuis("MB9AF15*"))||(cpuis("MB9AF13*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AF34*"))||(cpuis("MB9AF14*"))||(cpuis("MB9AFA*"))||(cpuis("MB9AFB*"))) group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." bitfld.byte 0x00 4. " WUCR ,Wake-up control bit" "Disabled,Enabled" bitfld.byte 0x00 3. " RIE ,Receive interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 2. " TIE ,Transmit interrupt enable bit" "Disabled,Enabled" endif if (((d.b(ad:0x40038700+0x1))&0x80)==0x80) group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Arbitration lost" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" else group.byte 0x4++0x0 line.byte 0x0 "IBSR,I2C Bus Status Register" bitfld.byte 0x00 7. " FBT ,First byte bit" "Not first,First" bitfld.byte 0x00 6. " RACK ,Acknowledge flag bit" "Low,High" bitfld.byte 0x00 5. " RSA , address detection bit" "Not detected,Detected" bitfld.byte 0x00 4. " TRX ,Data direction bit" "Receive,Transmit" textline " " bitfld.byte 0x00 3. " AL ,Arbitration lost bit" "Not lost,Lost" bitfld.byte 0x00 2. " RSC ,Iteration start condition check bit" "Not detected,Detected" bitfld.byte 0x00 1. " SPC ,Stop condition check bit" "Not detected,Detected" bitfld.byte 0x00 0. " BB ,Bus state bit" "Idle,Busy" endif if ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x0)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" textline " " bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x0)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x20)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 5. " DMA ,DMA mode enable bit" "Disabled,Enabled" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" elif ((((d.b(ad:0x40038700+0x1))&0x1)==0x1)&&(((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x5))&0x20)==0x0)) group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" textline " " bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" else group.byte 0x5++0x0 line.byte 0x0 "SSR,Serial Status Register" bitfld.byte 0x00 7. " REC ,Receive error flag clear bit" "No effect,Clear" bitfld.byte 0x00 6. " TSET ,Transmit empty flag set bit" "No effect,Set" bitfld.byte 0x00 4. " TBIE ,Transmit bus idle interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " ORE ,Overrun error flag bit" "No overrun,Overrun" bitfld.byte 0x00 2. " RDRF ,Receive data full flag bit" "Empty,Data" bitfld.byte 0x00 1. " TDRE ,Transmit data empty flag bit" "Data,Empty" bitfld.byte 0x00 0. " TBI ,Transmit bus idle flag" "Transmitting,Not transmitting" endif hgroup.byte 0x8++0x0 hide.byte 0x0 "RDR/TDR,Receive Data Register/Transmit Data Register" in sif (cpuis("MB9AF105?A")||cpuis("MB9AF11*")||cpuis("MB9AF132K")||cpuis("MB9AF13?M")||cpuis("MB9AF13?N")||cpuis("MB9AF13?L")||cpuis("MB9AF14*")||cpuis("MB9AF31*")||cpuis("MB9AF34*")||cpuis("MB9AFA3*")||cpuis("MB9AFA4*")||cpuis("MB9AFB4*")||cpuis("MB9BF?1*")||(cpu()=="MB9B129T")||(cpu()=="MB9B129S")||(cpu()=="MB9B128T")||(cpu()=="MB9B128S")) if ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x80)&&(((d.b(ad:0x40038700+0x1))&0xC0)!=0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 5. " SDAS ,SDA status bit" "Low,High" bitfld.byte 0x00 4. " SCLS ,SCL status bit" "Masked,Not masked" bitfld.byte 0x00 3. " SDAC ,SDA output control bit" "Low,High" textline " " bitfld.byte 0x00 2. " SCLC ,SCL output control bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" elif ((((d.b(ad:0x40038700+0x11))&0x80)==0x00)&&(((d.b(ad:0x40038700+0x1))&0xC0)==0x00)) group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" else group.byte 0x13++0x0 line.byte 0x00 "EIBCR,Extension I2C Bus Control Register" bitfld.byte 0x00 3. " SDAC ,SDA status bit" "Low,High" bitfld.byte 0x00 2. " SCLC ,SCL status bit" "Low,High" bitfld.byte 0x00 1. " SOCE ,Serial output enabled bit" "Disabled,Enabled" bitfld.byte 0x00 0. " BEC ,Bus error control bit" "Aborted,Continued" endif endif group.byte 0x11++0x0 line.byte 0x0 "ISMK,7-bit Slave Address Mask Register" bitfld.byte 0x00 7. " EN ,I2C interface operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 6. " SM6 ,Slave address mask bit 6" "Masked,Not masked" bitfld.byte 0x00 5. " SM5 ,Slave address mask bit 5" "Masked,Not masked" bitfld.byte 0x00 4. " SM4 ,Slave address mask bit 4" "Masked,Not masked" textline " " bitfld.byte 0x00 3. " SM3 ,Slave address mask bit 3" "Masked,Not masked" bitfld.byte 0x00 2. " SM2 ,Slave address mask bit 2" "Masked,Not masked" bitfld.byte 0x00 1. " SM1 ,Slave address mask bit 1" "Masked,Not masked" bitfld.byte 0x00 0. " SM0 ,Slave address mask bit 0" "Masked,Not masked" group.byte 0x10++0x0 line.byte 0x0 "ISBA,7-bit Slave Address Register" bitfld.byte 0x00 7. " SAEN ,Slave address enable bit" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 1. " SA[6:0] ,7-bit slave address" group.word 0xC++0x1 line.word 0x0 "BGR,Baud Rate Generator Registers" hexmask.word.byte 0x00 8.--14. 1. " BGR1 ,Baud Rate Generator Register 1" hexmask.word.byte 0x00 0.--7. 1. " BGR0 ,Baud Rate Generator Register 0" width 12. else group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register" bitfld.byte 0x00 5.--7. " MD[2:0] ,Operation mode set bit" "UART0,UART1,CSIO,LIN,I2C,?..." endif endif width 12. width 8. tree "FIFO Registers" group.byte 0x15++0x0 line.byte 0x0 "FCR1,FIFO Control Register 1" ; bitfld.byte 0x00 7. " FTST1 ,FIFO test bit" "Disabled,Enabled" ; bitfld.byte 0x00 6. " FTST0 ,FIFO test bit" "Disabled,Enabled" bitfld.byte 0x00 4. " FLSTE ,Re-transmit data lost detect enable bit" "Disabled,Enabled" bitfld.byte 0x00 3. " FRIIE ,Receive FIFO idle detection enable bit" "Disabled,Enable" bitfld.byte 0x00 2. " FDRQ ,Transmit FIFO data request bit" "Not requested,Requested" bitfld.byte 0x00 1. " FTIE ,Transmit FIFO interrupt enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " FSEL ,FIFO select bit (FIFO1/FIFO2)" "Transmit/Receive,Receive/Transmit" group.byte 0x14++0x0 line.byte 0x0 "FCR0,FIFO Control Register 0" bitfld.byte 0x00 6. " FLST ,FIFO re-transmit data lost flag bit" "Not lost,Lost" bitfld.byte 0x00 5. " FLD ,FIFO pointer reload bit" "Not reloaded,Reloaded" bitfld.byte 0x00 4. " FSET ,FIFO pointer save bit" "No effect,Saved" bitfld.byte 0x00 3. " FCL2 ,FIFO2 reset bit" "No effect,Reset" textline " " bitfld.byte 0x00 2. " FCL1 ,FIFO1 reset bit" "No effect,Reset" bitfld.byte 0x00 1. " FE2 ,FIFO2 operation enable bit" "Disabled,Enabled" bitfld.byte 0x00 0. " FE1 ,FIFO1 operation enable bit" "Disabled,Enabled" group.byte 0x18++0x1 line.byte 0x1 "FBYTE2,FIFO Byte Register 2" line.byte 0x0 "FBYTE1,FIFO Byte Register 1" tree.end width 12. tree.end endif tree.end tree "I2C (I2C Auxiliary Noise Filter)" base ad:0x40038800 width 8. sif cpuis("MB9AF131K")||cpuis("MB9AF132K")||cpuis("MB9AF121L")||cpuis("MB9AF421L") group.word 0x00++0x01 line.word 0x00 "I2CDNF,I2C Auxiliary Noise Filter Setting Register" bitfld.word 0x00 10.--11. " I2CDNF5 ,Auxiliary noise filter additional step select bits for ch5 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 6.--7. " I2CDNF3 ,Auxiliary noise filter additional step select bits for ch3 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 2.--3. " I2CDNF1 ,Auxiliary noise filter additional step select bits for ch1 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 0.--1. " I2CDNF0 ,Auxiliary noise filter additional step select bits for ch0 " "Not added,1 step,2 steps,3 steps" elif cpuis("MB9BF321L")||cpuis("MB9BF322L")||cpuis("MB9BF324L")||cpuis("MB9BF321M")||cpuis("MB9BF322M")||cpuis("MB9BF324M")||cpuis("MB9BF521L")||cpuis("MB9BF522L")||cpuis("MB9BF524L")||cpuis("MB9BF521M")||cpuis("MB9BF522M")||cpuis("MB9BF524M")||cpuis("MB9BF121L")||cpuis("MB9BF122L")||cpuis("MB9BF124L")||cpuis("MB9BF121M")||cpuis("MB9BF122M")||cpuis("MB9BF124M") group.word 0x00++0x01 line.word 0x00 "I2CDNF,I2C Auxiliary Noise Filter Setting Register" bitfld.word 0x00 14.--15. " I2CDNF7 ,Auxiliary noise filter additional step select bits for ch7 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 12.--13. " I2CDNF6 ,Auxiliary noise filter additional step select bits for ch6 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 10.--11. " I2CDNF5 ,Auxiliary noise filter additional step select bits for ch5 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 8.--9. " I2CDNF4 ,Auxiliary noise filter additional step select bits for ch4 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 6.--7. " I2CDNF3 ,Auxiliary noise filter additional step select bits for ch3 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 4.--5. " I2CDNF2 ,Auxiliary noise filter additional step select bits for ch2 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 0.--1. " I2CDNF0 ,Auxiliary noise filter additional step select bits for ch0 " "Not added,1 step,2 steps,3 steps" elif cpuis("MB9BF321K")||cpuis("MB9BF322K")||cpuis("MB9BF324K")||cpuis("MB9BF521K")||cpuis("MB9BF522K")||cpuis("MB9BF524K")||cpuis("MB9BF121K")||cpuis("MB9BF122K")||cpuis("MB9BF124K") group.word 0x00++0x01 line.word 0x00 "I2CDNF,I2C Auxiliary Noise Filter Setting Register" bitfld.word 0x00 6.--7. " I2CDNF3 ,Auxiliary noise filter additional step select bits for ch3 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 0.--1. " I2CDNF0 ,Auxiliary noise filter additional step select bits for ch0 " "Not added,1 step,2 steps,3 steps" elif cpuis("MB9AF121K")||cpuis("MB9AF421K") group.word 0x00++0x01 line.word 0x00 "I2CDNF,I2C Auxiliary Noise Filter Setting Register" bitfld.word 0x00 6.--7. " I2CDNF3 ,Auxiliary noise filter additional step select bits for ch3 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 2.--3. " I2CDNF1 ,Auxiliary noise filter additional step select bits for ch1 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 0.--1. " I2CDNF0 ,Auxiliary noise filter additional step select bits for ch0 " "Not added,1 step,2 steps,3 steps" elif cpuis("MB9BF121J") group.word 0x00++0x01 line.word 0x00 "I2CDNF,I2C Auxiliary Noise Filter Setting Register" bitfld.word 0x00 10.--11. " I2CDNF5 ,Auxiliary noise filter additional step select bits for ch5 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 4.--5. " I2CDNF2 ,Auxiliary noise filter additional step select bits for ch2 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 2.--3. " I2CDNF1 ,Auxiliary noise filter additional step select bits for ch1 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 0.--1. " I2CDNF0 ,Auxiliary noise filter additional step select bits for ch0 " "Not added,1 step,2 steps,3 steps" else group.word 0x00++0x01 line.word 0x00 "I2CDNF,I2C Auxiliary Noise Filter Setting Register" bitfld.word 0x00 14.--15. " I2CDNF7 ,Auxiliary noise filter additional step select bits for ch7 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 12.--13. " I2CDNF6 ,Auxiliary noise filter additional step select bits for ch6 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 10.--11. " I2CDNF5 ,Auxiliary noise filter additional step select bits for ch5 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 8.--9. " I2CDNF4 ,Auxiliary noise filter additional step select bits for ch4 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 6.--7. " I2CDNF3 ,Auxiliary noise filter additional step select bits for ch3 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 4.--5. " I2CDNF2 ,Auxiliary noise filter additional step select bits for ch2 " "Not added,1 step,2 steps,3 steps" textline " " bitfld.word 0x00 2.--3. " I2CDNF1 ,Auxiliary noise filter additional step select bits for ch1 " "Not added,1 step,2 steps,3 steps" bitfld.word 0x00 0.--1. " I2CDNF0 ,Auxiliary noise filter additional step select bits for ch0 " "Not added,1 step,2 steps,3 steps" endif width 0xB tree.end sif ((!cpuis("MB9AF105NA"))&&(!cpuis("MB9AF105RA"))&&(!cpuis("MB9AF11*"))&&(!cpuis("MB9AF13*"))&&(!cpuis("MB9AF14*"))&&(!cpuis("MB9AFA*"))&&(!cpuis("MB9BF11*"))&&(!cpuis("MB9BF4*"))&&(!cpuis("MB9BF12?S"))&&(!cpuis("MB9BF12?T"))) tree.open "USB (Universal Serial Bus)" tree "Clock Generation" base ad:0x40036000 width 11. group.byte 0x0++0x0 line.byte 0x00 "UCCR,USB Clock Setup Register" sif (cpuis("MB9B*S")||cpuis(MB9B*T)) bitfld.byte 0x00 5.--6. " ECSEL ,Ethernet clock selection bits" "CLKMO,USB/ETH PLL OSC,CLKPLL,?..." bitfld.byte 0x00 4. " ECEN ,Ethernet clock output enable bit" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " UCEN1 ,USB (ch.1) clock output enable bit" "Disabled,Enabled" bitfld.byte 0x00 1.--2. " UCSEL ,USB clock selection bits" "CLKMO,USB/ETH PLL OSC,CLKPLL,?..." else bitfld.byte 0x00 1. " UCSEL ,USB clock select bit" "CLKMO,PLL" endif textline " " bitfld.byte 0x00 0. " UCEN ,USB clock output enable bit" "Disabled,Enabled" group.byte 0x4++0x0 line.byte 0x00 "UPCR1,USB-PLL Control Register 1" bitfld.byte 0x00 1. " UPINC ,PLL macro input clock select bit" "CLKMO,?..." bitfld.byte 0x00 0. " UPLLEN ,USB-PLL macro oscillation enable bit" "Disabled,Enabled" group.byte 0x8++0x0 line.byte 0x00 "UPCR2,USB-PLL Control Register 2" bitfld.byte 0x00 0.--2. " UPOWT ,USB-PLL macro oscillation stabilization wait setting bit" "(2^9)/clock,(2^10)/clock,(2^11)/clock,(2^12)/clock,(2^13)/clock,(2^14)/clock,(2^15)/clock,(2^16)/clock" group.byte 0xC++0x0 line.byte 0x00 "UPCR3,USB-PLL Control Register 3" bitfld.byte 0x00 0.--4. " UPLLK ,Frequency division ratio setting bit of the USB-PLL clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" sif (cpuis("MB9AF105?A")||cpuis("MB9AFA*")||cpuis("MB9AFB*")||cpuis("MB9AF34*")||cpuis("MB9AF14*")||cpuis("MB9AF?0?N")||cpuis("MB9AF?0?R")||cpuis("MB9AF?0?NA")||cpuis("MB9AF?0?RA")||cpuis("MB9BF?0?N")||cpuis("MB9BF?0?R")||cpuis("MB9BF?0?NA")||cpuis("MB9BF?0?RA")) group.byte 0x10++0x0 line.byte 0x00 "UPCR4,USB-PLL Control Register 4" bitfld.byte 0x00 0.--4. " UPLLN ,Frequency division ratio setting bit of the USB-PLL clock" ",1/2,1/3,1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11,1/12,1/13,1/14,1/15,1/16,1/17,1/18,1/19,1/20,1/21,1/22,1/23,1/24,1/25,1/26,1/27,1/28,1/29,1/30,1/31,1/32" else group.byte 0x10++0x0 line.byte 0x00 "UPCR4,USB-PLL Control Register 4" hexmask.byte 0x00 0.--6. 1. " UPLLN ,Frequency division ratio setting bit of the USB-PLL clock" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UP_STR,USB-PLL State Register" bitfld.byte 0x00 0. " UPRDY ,USB-PLL macro oscillation stable bit" "Not stabilized,Stabilized" group.byte 0x18++0x00 line.byte 0x00 "UPINT_ENR,USB-PLL Interrupt Factor Enable Register" bitfld.byte 0x00 0. " UPCSE ,USB-PLL macro oscillation stabilization complete interrupt enable bit" "Disabled,Enabled" rgroup.byte 0x20++0x00 line.byte 0x00 "UPINT_STR,USB-PLL Interrupt Factor State Register" bitfld.byte 0x00 0. " UPCSI ,USB-PLL interrupt cause status bit" "No interrupt,Interrupt" wgroup.byte 0x1C++0x00 line.byte 0x00 "UPINT_CLR,USB-PLL Interrupt Factor Clear Register" bitfld.byte 0x00 0. " UPCSC ,USB-PLL macro oscillation stabilization interrupt cause clear bit" "No effect,Clear" sif (cpuis("MB9BF*S")||cpuis("MB9BF*T")) group.byte 0x30++0x00 line.byte 0x00 "USBEN0,USB CH0 Enable Register" bitfld.byte 0x00 0. " USBEN0 ,USB ch. 0 enable bit" "Disabled,Enabled" group.byte 0x34++0x00 line.byte 0x00 "USBEN1,USB CH1 Enable Register" bitfld.byte 0x00 0. " USBEN1 ,USB ch. 1 enable bit" "Disabled,Enabled" else group.byte 0x30++0x00 line.byte 0x00 "USBEN,USB Enable Register" bitfld.byte 0x00 0. " USBEN ,USB enable bit" "Disabled,Enabled" endif width 0xb tree.end tree "Channel 0" base ad:0x40040000 width 10. tree "Function Registers" if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80) group.word 0x2120++0x1 line.word 0x0 "UDCC,UDC Control Register" bitfld.word 0x00 7. " RST ,Function Reset Bit" "No reset,Reset" bitfld.word 0x00 6. " RESUM ,Resume Setting Bit" "No resume,Resume" bitfld.word 0x00 5. " HCONX ,Host Connection Bit" "Connected,Disconnected" bitfld.word 0x00 4. " USTP ,USB Operating Clock Stop Bit" "Not stopped,Stopped" textline " " bitfld.word 0x00 3. " STALCLREN ,Endpoint 1 to 5 STAL Bit Clear Select Bit" "Software,Hardware" bitfld.word 0x00 1. " RFBK ,Data Toggle Mode Select Bit (when to toggle PID data)" "After transfer,Unconditionally" bitfld.word 0x00 0. " PWC ,Power Control Bit" "Bus,Self" else group.word 0x2120++0x1 line.word 0x0 "UDCC,UDC Control Register" bitfld.word 0x00 7. " RST ,Function Reset Bit" "No reset,Reset" bitfld.word 0x00 6. " RESUM ,Resume Setting Bit" "No resume,Resume" bitfld.word 0x00 4. " USTP ,USB Operating Clock Stop Bit" "Not stopped,Stopped" endif if ((((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2144))&0x8000)==0x8000)&&(((d.w(ad:0x40040000+0x2148))&0x8000)==0x8000)) group.word 0x2124++0x1 line.word 0x0 "EP0C,EP0 Control Register" bitfld.word 0x00 9. " STAL ,Endpoint 0 Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS0 ,Packet Size Endpoint 0 Setting Bits" else group.word 0x2124++0x1 line.word 0x0 "EP0C,EP0 Control Register" bitfld.word 0x00 9. " STAL ,Endpoint 0 Stall Setting Bit" "Ignored,Set" endif if ((((d.b(ad:0x40040000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40040000+0x2100))&0x1)==0x0)&&(((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40040000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40040000+0x2120))&0x8)==0x0)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.b(ad:0x40040000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40040000+0x2100))&0x1)==0x0)&&(((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40040000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40040000+0x2120))&0x8)==0x0)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2130+0x24))&0x8000)==0x8000) group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2130+0x24))&0x8000)==0x8000) group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2134+0x24))&0x8000)==0x8000) group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2134+0x24))&0x8000)==0x8000) group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.w(ad:0x40040000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2138+0x24))&0x8000)==0x8000) group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40040000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40040000+0x2138+0x24))&0x8000)==0x8000) group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif rgroup.word 0x213C++0x1 line.word 0x0 "TMSP,Time Stamp Register" hexmask.word 0x00 0.--10. 1. " TMSP ,The frame number of a received SOF packet" group.byte 0x2140++0x1 line.byte 0x0 "UDCS,UDC Status Register" bitfld.byte 0x00 5. " SUSP ,Suspend detection bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 4. " SOF ,SOF Detection Bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 3. " BRST ,Bus Reset Detection Bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 2. " WKUP ,Wake-up Detection Bit" "Not detected/Cleared,Detected" textline " " bitfld.byte 0x00 1. " SETP ,Setup Stage Detection Bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 0. " CONF ,Configuration Detection Bit" "Not detected/Cleared,Detected" line.byte 0x1 "UDCIE,UDC Interrupt Enable Register" bitfld.byte 0x01 5. " SUSPIE ,Suspend Interrupt Enable Bit" "Disabled,Enabled" bitfld.byte 0x01 4. " SOFIE ,SOF Reception Interrupt Enable Bit" "Disabled,Enabled" bitfld.byte 0x01 3. " BRSTIE ,Bus Reset Interrupt Enable Bit" "Disabled,Enabled" bitfld.byte 0x01 2. " WKUPIE ,Wake-up Interrupt Enable Bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " CONFN ,Configuration Number Indication Bit" "Number 0,Number 1" bitfld.byte 0x01 0. " CONFIE ,Configuration Interrupt Enable Bit" "Disabled,Enabled" group.word 0x2144++0x1 line.word 0x0 "EP0IS,EP0I Status Register" bitfld.word 0x00 15. " BFINI ,Send Buffer Initialization Bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQIIE ,Send Data Interrupt Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " DRQI ,Send/Receive Data Interrupt Request Bit" "Cleared,Interrupt" group.word 0x2148++0x1 line.word 0x0 "EP0OS,EP0O Status Register" bitfld.word 0x00 15. " BFINI ,Receive Buffer Initialization Bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Receive Data Interrupt Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " DRQO ,Receive Data Interrupt Request Bit" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size Indication Bit" group.word 0x214C++0x1 line.word 0x0 "EP1S,EP1 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word 0x00 0.--8. 1. " SIZE ,Packet Size" group.word 0x2150++0x1 line.word 0x0 "EP2S,EP2 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.word 0x2154++0x1 line.word 0x0 "EP3S,EP3 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.word 0x2158++0x1 line.word 0x0 "EP4S,EP4 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.word 0x215C++0x1 line.word 0x0 "EP5S,EP5 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.byte 0x2160++0x1 line.byte 0x0 "EP0DTL,EP0 Low Data Register" line.byte 0x1 "EP0DTH,EP0 High Data Register" group.byte 0x2164++0x1 line.byte 0x0 "EP1DTL,EP1 Low Data Register" line.byte 0x1 "EP1DTH,EP1 High Data Register" group.byte 0x2168++0x1 line.byte 0x0 "EP2DTL,EP2 Low Data Register" line.byte 0x1 "EP2DTH,EP2 High Data Register" group.byte 0x216C++0x1 line.byte 0x0 "EP3DTL,EP3 Low Data Register" line.byte 0x1 "EP3DTH,EP3 High Data Register" group.byte 0x2170++0x1 line.byte 0x0 "EP4DTL,EP4 Low Data Register" line.byte 0x1 "EP4DTH,EP4 High Data Register" group.byte 0x2174++0x1 line.byte 0x0 "EP5DTL,EP5 Low Data Register" line.byte 0x1 "EP5DTH,EP5 High Data Register" tree.end tree "Host Registers" if (((d.b(ad:0x40040000+0x2108))&0x4)==0x4) group.byte 0x2100++0x1 line.byte 0x0 "HCNT0,Host Control Register 0" bitfld.byte 0x00 7. " RWKIRE ,Remove Wake up Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " URIRE ,Usb bus Rest Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 5. " CMPIRE ,Completion Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CNNIRE ,Connection Interrupt Request Enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " DIRE ,Disconnection Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOFIRE ,Start Of Frame Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " URST ,Usb Bus Reset" "No reset,?..." bitfld.byte 0x00 0. " HOST ,HOST Mode" "Function,Host" line.byte 0x1 "HCNT1,Host Control Register 1" bitfld.byte 0x01 2. " SOFSTEP ,SOF interrupt occurrence selection" "Compared,Not compared" bitfld.byte 0x01 1. " CANCEL ,Token CANCEL enable" "Not cancelled,Cancelled" bitfld.byte 0x01 0. " RETRY ,RETRY enable" "Not retried,Retried" else if (((d.b(ad:0x40040000+0x2100))&0x2)==0x2) rgroup.byte 0x2100++0x1 line.byte 0x0 "HCNT0,Host Control Register 0" bitfld.byte 0x00 7. " RWKIRE ,Remove Wake up Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " URIRE ,Usb bus Rest Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 5. " CMPIRE ,Completion Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CNNIRE ,Connection Interrupt Request Enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " DIRE ,Disconnection Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOFIRE ,Start Of Frame Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " URST ,Usb Bus Reset" "No reset,Reset" bitfld.byte 0x00 0. " HOST ,HOST Mode" "Function,Host" line.byte 0x1 "HCNT1,Host Control Register 1" bitfld.byte 0x01 2. " SOFSTEP ,This is a SOF interrupt occurrence selection bit" "Compared,Not compared" bitfld.byte 0x01 1. " CANCEL ,Token CANCEL enable" "Not cancelled,Cancelled" bitfld.byte 0x01 0. " RETRY ,RETRY enable" "Not retried,Retried" else group.byte 0x2100++0x1 line.byte 0x0 "HCNT0,Host Control Register 0" bitfld.byte 0x00 7. " RWKIRE ,Remove Wake up Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " URIRE ,Usb bus Rest Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 5. " CMPIRE ,Completion Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CNNIRE ,Connection Interrupt Request Enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " DIRE ,Disconnection Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOFIRE ,Start Of Frame Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " URST ,Usb Bus Reset" "No reset,Reset" bitfld.byte 0x00 0. " HOST ,HOST Mode" "Function,Host" line.byte 0x1 "HCNT1,Host Control Register 1" bitfld.byte 0x01 2. " SOFSTEP ,This is a SOF interrupt occurrence selection bit" "Compared,Not compared" bitfld.byte 0x01 1. " CANCEL ,Token CANCEL enable" "Not canceled,Canceled" bitfld.byte 0x01 0. " RETRY ,RETRY enable" "Not retried,Retried" endif endif group.byte 0x2104++0x1 line.byte 0x0 "HIRQ,Host Interrupt Register" bitfld.byte 0x00 7. " TCAN ,Token Cancel flag" "Not canceled,Canceled" bitfld.byte 0x00 5. " RWKIRQ ,Remove Wake up Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 4. " URIRQ ,Usb bus Reset Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 3. " CMPIRQ ,Completion Interrupt Request" "No interrupt,Interrupt" textline " " bitfld.byte 0x00 2. " CNNIRQ ,Connection Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 1. " DIRQ ,Disconnection Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 0. " SOFIRQ ,Start Of Frame Interrupt Request" "No interrupt,Interrupt" line.byte 0x1 "HERR,Host Error Status Register" bitfld.byte 0x01 7. " LSTSOF ,Lost SOF flag" "Not lost,Lost" bitfld.byte 0x01 6. " RERR ,Receive error flag" "No error,Error" bitfld.byte 0x01 5. " TOUT ,Timeout flag" "No timeout,Timeout" bitfld.byte 0x01 4. " CRC ,CRC error flag" "No error,Error" textline " " bitfld.byte 0x01 3. " TGERR ,Toggle error flag" "No error,Error" bitfld.byte 0x01 2. " STUFF ,Stuffing error flag" "No error,Error" bitfld.byte 0x01 0.--1. " HS ,Hand Shake status" "ACK,NAK,STALL,NULL" if (((d.b(ad:0x40040000+0x2108))&0x1)==0x1) group.byte 0x2108++0x0 line.byte 0x0 "HSTATE,Host Status Register" bitfld.byte 0x00 5. " ALIVE ,Keep-alive function in the low-speed mode" "SOF,SE0" bitfld.byte 0x00 4. " CLKSEL ,USB operation clock selection bit" "Low-speed,Full-speed" bitfld.byte 0x00 3. " SOFBUSY ,SOF busy flag" "Stopped,Busy" bitfld.byte 0x00 2. " SUSP ,Suspend setting bit" "Resume,Suspend" textline " " rbitfld.byte 0x00 1. " TMODE ,Transmission MODE" "Low speed,Full speed" rbitfld.byte 0x00 0. " CSTAT ,Connection status flag" "Disconnected,Connected" else group.byte 0x2108++0x0 line.byte 0x0 "HSTATE,Host Status Register" bitfld.byte 0x00 5. " ALIVE ,Keep-alive function in the low-speed mode" "SOF,SE0" bitfld.byte 0x00 4. " CLKSEL ,USB operation clock selection bit" "Low-speed,Full-speed" bitfld.byte 0x00 3. " SOFBUSY ,SOF busy flag" "Stopped,Busy" bitfld.byte 0x00 2. " SUSP ,Suspend setting bit" "Resume,Suspend" textline " " rbitfld.byte 0x00 0. " CSTAT ,Connection status flag" "Disconnected,Connected" endif if (((d.b(ad:0x40040000+0x2101))&0x4)==0x4) group.byte 0x2109++0x0 line.byte 0x0 "HFCOMP,SOF Interrupt Frame Compare Register" else rgroup.byte 0x2109++0x0 line.byte 0x0 "HFCOMP,SOF Interrupt Frame Compare Register" endif group.byte 0x2110++0x0 line.byte 0x0 "HRTIMER2,The Retry Timer Setup Register bits [17,16]" bitfld.byte 0x0 0.--1. " RTIMER2 ,The Retry Timer Setup Register bits [17,16]" "0,1,2,3" group.word 0x210C++0x1 line.word 0x0 "HRTIMER,The Retry Timer Setup Register bits [15,0]" hexmask.word.byte 0x0 8.--15. 1. " RTIMER1 ,The Retry Timer Setup Register bits [15,8]" hexmask.word.byte 0x0 0.--7. 1. " RTIMER0 ,The Retry Timer Setup Register bits [7,0]" group.byte 0x2111++0x0 line.byte 0x0 "HADR,Host Address Register" hexmask.byte 0x0 0.--6. 1. " ADDRESS ,Address bits" group.word 0x2114++0x1 line.word 0x0 "HEOF,EOF Setup Register" hexmask.word.byte 0x0 8.--13. 1. " EOF1 ,End Of Frame bits[13,8]" hexmask.word.byte 0x0 0.--7. 1. " EOF0 ,End Of Frame bits[7,0]" if (((d.b(ad:0x40040000+0x2108))&0x8)==0x0) group.word 0x2118++0x1 line.word 0x0 "HFRAME,Frame Setup Register" bitfld.word 0x0 8.--10. " FRAME1 ,Frame setting bits [10,8]" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 0.--7. 1. " FRAME0 ,Frame setting bits [7,0]" else rgroup.word 0x2118++0x1 line.word 0x0 "HFRAME,Frame Setup Register" bitfld.word 0x0 8.--10. " FRAME1 ,Frame setting bits [10,8]" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 0.--7. 1. " FRAME0 ,Frame setting bits [7,0]" endif group.byte 0x211C++0x0 line.byte 0x0 "HTOKEN,Host Token Endpoint Register" bitfld.byte 0x00 7. " TGGL ,Toggle bit" "DATA0,DATA1" bitfld.byte 0x00 4.--6. " TKNEN ,Token enable bits" "No data,SETUP,IN,OUT,SOF,Isochronous IN,Isochronous OUT,?..." sif (cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")||(cpu()=="MB9AF311L")||(cpu()=="MB9AF312L")||(cpu()=="MB9AF314L")||(cpu()=="MB9AF311M")||(cpu()=="MB9AF312M")||(cpu()=="MB9AF314M")||(cpu()=="MB9AF315M")||(cpu()=="MB9AF316M")||(cpu()=="MB9AF311N")||(cpu()=="MB9AF312N")||(cpu()=="MB9AF314N")||(cpu()=="MB9AF315N")||(cpu()=="MB9AF316N")||(cpu()=="MB9AF341L")||(cpu()=="MB9AF342L")||(cpu()=="MB9AF344L")||(cpu()=="MB9AF341M")||(cpu()=="MB9AF342M")||(cpu()=="MB9AF344M")||(cpu()=="MB9AF341N")||(cpu()=="MB9AF342N")||(cpu()=="MB9AF344N")||(cpu()=="MB9AFB41L")||(cpu()=="MB9AFB42L")||(cpu()=="MB9AFB44L")||(cpu()=="MB9AFB41M")||(cpu()=="MB9AFB42M")||(cpu()=="MB9AFB44M")||(cpu()=="MB9AFB41N")||(cpu()=="MB9AFB42N")||(cpu()=="MB9AFB44N")||(cpu()=="MB9BF512N")||(cpu()=="MB9BF514N")||(cpu()=="MB9BF515N")||(cpu()=="MB9BF516N")||(cpu()=="MB9BF512R")||(cpu()=="MB9BF514R")||(cpu()=="MB9BF515R")||(cpu()=="MB9BF516R")||(cpu()=="MB9BF516S")||(cpu()=="MB9BF517S")||(cpu()=="MB9BF518S")||(cpu()=="MB9BF516T")||(cpu()=="MB9BF517T")||(cpu()=="MB9BF518T")||(cpu()=="MB9BF616S")||(cpu()=="MB9BF617S")||(cpu()=="MB9BF618S")||(cpu()=="MB9BF616T")||(cpu()=="MB9BF617T")||(cpu()=="MB9BF618T") bitfld.byte 0x00 0.--3. " ENDPT ,Selects ENDPoint" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--3. " ENDPT ,END Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 0xb tree.end sif (cpuis("MB9BF2*")||cpuis("MB9BF31?S")||cpuis("MB9BF31?T")||cpuis("MB9BF5*S")||cpuis("MB9BF5*T")||cpuis("MB9BF6*")) tree "Channel 1" base ad:0x40050000 width 10. tree "Function Registers" if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80) group.word 0x2120++0x1 line.word 0x0 "UDCC,UDC Control Register" bitfld.word 0x00 7. " RST ,Function Reset Bit" "No reset,Reset" bitfld.word 0x00 6. " RESUM ,Resume Setting Bit" "No resume,Resume" bitfld.word 0x00 5. " HCONX ,Host Connection Bit" "Connected,Disconnected" bitfld.word 0x00 4. " USTP ,USB Operating Clock Stop Bit" "Not stopped,Stopped" textline " " bitfld.word 0x00 3. " STALCLREN ,Endpoint 1 to 5 STAL Bit Clear Select Bit" "Software,Hardware" bitfld.word 0x00 1. " RFBK ,Data Toggle Mode Select Bit (when to toggle PID data)" "After transfer,Unconditionally" bitfld.word 0x00 0. " PWC ,Power Control Bit" "Bus,Self" else group.word 0x2120++0x1 line.word 0x0 "UDCC,UDC Control Register" bitfld.word 0x00 7. " RST ,Function Reset Bit" "No reset,Reset" bitfld.word 0x00 6. " RESUM ,Resume Setting Bit" "No resume,Resume" bitfld.word 0x00 4. " USTP ,USB Operating Clock Stop Bit" "Not stopped,Stopped" endif if ((((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2144))&0x8000)==0x8000)&&(((d.w(ad:0x40050000+0x2148))&0x8000)==0x8000)) group.word 0x2124++0x1 line.word 0x0 "EP0C,EP0 Control Register" bitfld.word 0x00 9. " STAL ,Endpoint 0 Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS0 ,Packet Size Endpoint 0 Setting Bits" else group.word 0x2124++0x1 line.word 0x0 "EP0C,EP0 Control Register" bitfld.word 0x00 9. " STAL ,Endpoint 0 Stall Setting Bit" "Ignored,Set" endif if ((((d.b(ad:0x40050000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40050000+0x2100))&0x1)==0x0)&&(((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40050000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40050000+0x2120))&0x8)==0x0)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2128+0x24))&0x8000)==0x8000) group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word 0x00 0.--8. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2128++0x1 line.word 0x0 "EP1C,EP1 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.b(ad:0x40050000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40050000+0x2100))&0x1)==0x0)&&(((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif elif ((((d.b(ad:0x40050000+0x2100))&0x1)==0x1)&&(((d.w(ad:0x40050000+0x2120))&0x8)==0x0)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "In,Out" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x212C+0x24))&0x8000)==0x8000) group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Iso,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x212C++0x1 line.word 0x0 "EP2C,EP2 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2130+0x24))&0x8000)==0x8000) group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2130+0x24))&0x8000)==0x8000) group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2130++0x1 line.word 0x0 "EP3C,EP3 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2134+0x24))&0x8000)==0x8000) group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2134+0x24))&0x8000)==0x8000) group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2134++0x1 line.word 0x0 "EP4C,EP4 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif if ((((d.w(ad:0x40050000+0x2120))&0x8)==0x8)) if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2138+0x24))&0x8000)==0x8000) group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif else if (((d.w(ad:0x40050000+0x2120))&0x80)==0x80)&&(((d.w(ad:0x40050000+0x2138+0x24))&0x8000)==0x8000) group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 15. " EPEN ,Endpoint Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13.--14. " TYPE ,Endpoint Transfer Type Select Bits" "Disabled,Disabled,Bulk,Interrupt" bitfld.word 0x00 12. " DIR ,Endpoint Transfer Direction Select Bit" "Out,In" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Released,Set" hexmask.word.byte 0x00 0.--6. 1. " PKS ,Packet Size Setting Bits" else group.word 0x2138++0x1 line.word 0x0 "EP5C,EP5 Control Register" bitfld.word 0x00 11. " DMAE ,DMA Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " NULE ,Null Automatic Transfer Enable Bit" "Disabled,Enabled" bitfld.word 0x00 9. " STAL ,Endpoint Stall Setting Bit" "Ignored,Set" endif endif rgroup.word 0x213C++0x1 line.word 0x0 "TMSP,Time Stamp Register" hexmask.word 0x00 0.--10. 1. " TMSP ,The frame number of a received SOF packet" group.byte 0x2140++0x1 line.byte 0x0 "UDCS,UDC Status Register" bitfld.byte 0x00 5. " SUSP ,Suspend detection bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 4. " SOF ,SOF Detection Bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 3. " BRST ,Bus Reset Detection Bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 2. " WKUP ,Wake-up Detection Bit" "Not detected/Cleared,Detected" textline " " bitfld.byte 0x00 1. " SETP ,Setup Stage Detection Bit" "Not detected/Cleared,Detected" bitfld.byte 0x00 0. " CONF ,Configuration Detection Bit" "Not detected/Cleared,Detected" line.byte 0x1 "UDCIE,UDC Interrupt Enable Register" bitfld.byte 0x01 5. " SUSPIE ,Suspend Interrupt Enable Bit" "Disabled,Enabled" bitfld.byte 0x01 4. " SOFIE ,SOF Reception Interrupt Enable Bit" "Disabled,Enabled" bitfld.byte 0x01 3. " BRSTIE ,Bus Reset Interrupt Enable Bit" "Disabled,Enabled" bitfld.byte 0x01 2. " WKUPIE ,Wake-up Interrupt Enable Bit" "Disabled,Enabled" textline " " bitfld.byte 0x01 1. " CONFN ,Configuration Number Indication Bit" "Number 0,Number 1" bitfld.byte 0x01 0. " CONFIE ,Configuration Interrupt Enable Bit" "Disabled,Enabled" group.word 0x2144++0x1 line.word 0x0 "EP0IS,EP0I Status Register" bitfld.word 0x00 15. " BFINI ,Send Buffer Initialization Bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQIIE ,Send Data Interrupt Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " DRQI ,Send/Receive Data Interrupt Request Bit" "Cleared,Interrupt" group.word 0x2148++0x1 line.word 0x0 "EP0OS,EP0O Status Register" bitfld.word 0x00 15. " BFINI ,Receive Buffer Initialization Bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Receive Data Interrupt Enable Bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" bitfld.word 0x00 10. " DRQO ,Receive Data Interrupt Request Bit" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size Indication Bit" group.word 0x214C++0x1 line.word 0x0 "EP1S,EP1 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word 0x00 0.--8. 1. " SIZE ,Packet Size" group.word 0x2150++0x1 line.word 0x0 "EP2S,EP2 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.word 0x2154++0x1 line.word 0x0 "EP3S,EP3 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.word 0x2158++0x1 line.word 0x0 "EP4S,EP4 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.word 0x215C++0x1 line.word 0x0 "EP5S,EP5 Status Register" bitfld.word 0x00 15. " BFINI ,Send/Receive Buffer Initialization bit" "Cleared,Initialized" bitfld.word 0x00 14. " DRQOIE ,Packet Transfer Interrupt Enable bit" "Disabled,Enabled" bitfld.word 0x00 13. " SPKIE ,Short Packet Interrupt Enable Bit" "Disabled,Enabled" rbitfld.word 0x00 11. " BUSY ,Busy Flag Bit" "Idle,Busy" bitfld.word 0x00 10. " DRQ ,Packet Transfer Interrupt Request" "Cleared,Interrupt" textline " " bitfld.word 0x00 9. " SPK ,Short Packet Interrupt Request Bit" "No interrupt,Interrupt" hexmask.word.byte 0x00 0.--6. 1. " SIZE ,Packet Size" group.byte 0x2160++0x1 line.byte 0x0 "EP0DTL,EP0 Low Data Register" line.byte 0x1 "EP0DTH,EP0 High Data Register" group.byte 0x2164++0x1 line.byte 0x0 "EP1DTL,EP1 Low Data Register" line.byte 0x1 "EP1DTH,EP1 High Data Register" group.byte 0x2168++0x1 line.byte 0x0 "EP2DTL,EP2 Low Data Register" line.byte 0x1 "EP2DTH,EP2 High Data Register" group.byte 0x216C++0x1 line.byte 0x0 "EP3DTL,EP3 Low Data Register" line.byte 0x1 "EP3DTH,EP3 High Data Register" group.byte 0x2170++0x1 line.byte 0x0 "EP4DTL,EP4 Low Data Register" line.byte 0x1 "EP4DTH,EP4 High Data Register" group.byte 0x2174++0x1 line.byte 0x0 "EP5DTL,EP5 Low Data Register" line.byte 0x1 "EP5DTH,EP5 High Data Register" tree.end tree "Host Registers" if (((d.b(ad:0x40050000+0x2108))&0x4)==0x4) group.byte 0x2100++0x1 line.byte 0x0 "HCNT0,Host Control Register 0" bitfld.byte 0x00 7. " RWKIRE ,Remove Wake up Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " URIRE ,Usb bus Rest Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 5. " CMPIRE ,Completion Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CNNIRE ,Connection Interrupt Request Enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " DIRE ,Disconnection Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOFIRE ,Start Of Frame Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " URST ,Usb Bus Reset" "No reset,?..." bitfld.byte 0x00 0. " HOST ,HOST Mode" "Function,Host" line.byte 0x1 "HCNT1,Host Control Register 1" bitfld.byte 0x01 2. " SOFSTEP ,SOF interrupt occurrence selection" "Compared,Not compared" bitfld.byte 0x01 1. " CANCEL ,Token CANCEL enable" "Not cancelled,Cancelled" bitfld.byte 0x01 0. " RETRY ,RETRY enable" "Not retried,Retried" else if (((d.b(ad:0x40050000+0x2100))&0x2)==0x2) rgroup.byte 0x2100++0x1 line.byte 0x0 "HCNT0,Host Control Register 0" bitfld.byte 0x00 7. " RWKIRE ,Remove Wake up Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " URIRE ,Usb bus Rest Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 5. " CMPIRE ,Completion Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CNNIRE ,Connection Interrupt Request Enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " DIRE ,Disconnection Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOFIRE ,Start Of Frame Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " URST ,Usb Bus Reset" "No reset,Reset" bitfld.byte 0x00 0. " HOST ,HOST Mode" "Function,Host" line.byte 0x1 "HCNT1,Host Control Register 1" bitfld.byte 0x01 2. " SOFSTEP ,This is a SOF interrupt occurrence selection bit" "Compared,Not compared" bitfld.byte 0x01 1. " CANCEL ,Token CANCEL enable" "Not cancelled,Cancelled" bitfld.byte 0x01 0. " RETRY ,RETRY enable" "Not retried,Retried" else group.byte 0x2100++0x1 line.byte 0x0 "HCNT0,Host Control Register 0" bitfld.byte 0x00 7. " RWKIRE ,Remove Wake up Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 6. " URIRE ,Usb bus Rest Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 5. " CMPIRE ,Completion Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CNNIRE ,Connection Interrupt Request Enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " DIRE ,Disconnection Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOFIRE ,Start Of Frame Interrupt Request Enable" "Disabled,Enabled" bitfld.byte 0x00 1. " URST ,Usb Bus Reset" "No reset,Reset" bitfld.byte 0x00 0. " HOST ,HOST Mode" "Function,Host" line.byte 0x1 "HCNT1,Host Control Register 1" bitfld.byte 0x01 2. " SOFSTEP ,This is a SOF interrupt occurrence selection bit" "Compared,Not compared" bitfld.byte 0x01 1. " CANCEL ,Token CANCEL enable" "Not canceled,Canceled" bitfld.byte 0x01 0. " RETRY ,RETRY enable" "Not retried,Retried" endif endif group.byte 0x2104++0x1 line.byte 0x0 "HIRQ,Host Interrupt Register" bitfld.byte 0x00 7. " TCAN ,Token Cancel flag" "Not canceled,Canceled" bitfld.byte 0x00 5. " RWKIRQ ,Remove Wake up Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 4. " URIRQ ,Usb bus Reset Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 3. " CMPIRQ ,Completion Interrupt Request" "No interrupt,Interrupt" textline " " bitfld.byte 0x00 2. " CNNIRQ ,Connection Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 1. " DIRQ ,Disconnection Interrupt Request" "No interrupt,Interrupt" bitfld.byte 0x00 0. " SOFIRQ ,Start Of Frame Interrupt Request" "No interrupt,Interrupt" line.byte 0x1 "HERR,Host Error Status Register" bitfld.byte 0x01 7. " LSTSOF ,Lost SOF flag" "Not lost,Lost" bitfld.byte 0x01 6. " RERR ,Receive error flag" "No error,Error" bitfld.byte 0x01 5. " TOUT ,Timeout flag" "No timeout,Timeout" bitfld.byte 0x01 4. " CRC ,CRC error flag" "No error,Error" textline " " bitfld.byte 0x01 3. " TGERR ,Toggle error flag" "No error,Error" bitfld.byte 0x01 2. " STUFF ,Stuffing error flag" "No error,Error" bitfld.byte 0x01 0.--1. " HS ,Hand Shake status" "ACK,NAK,STALL,NULL" if (((d.b(ad:0x40050000+0x2108))&0x1)==0x1) group.byte 0x2108++0x0 line.byte 0x0 "HSTATE,Host Status Register" bitfld.byte 0x00 5. " ALIVE ,Keep-alive function in the low-speed mode" "SOF,SE0" bitfld.byte 0x00 4. " CLKSEL ,USB operation clock selection bit" "Low-speed,Full-speed" bitfld.byte 0x00 3. " SOFBUSY ,SOF busy flag" "Stopped,Busy" bitfld.byte 0x00 2. " SUSP ,Suspend setting bit" "Resume,Suspend" textline " " rbitfld.byte 0x00 1. " TMODE ,Transmission MODE" "Low speed,Full speed" rbitfld.byte 0x00 0. " CSTAT ,Connection status flag" "Disconnected,Connected" else group.byte 0x2108++0x0 line.byte 0x0 "HSTATE,Host Status Register" bitfld.byte 0x00 5. " ALIVE ,Keep-alive function in the low-speed mode" "SOF,SE0" bitfld.byte 0x00 4. " CLKSEL ,USB operation clock selection bit" "Low-speed,Full-speed" bitfld.byte 0x00 3. " SOFBUSY ,SOF busy flag" "Stopped,Busy" bitfld.byte 0x00 2. " SUSP ,Suspend setting bit" "Resume,Suspend" textline " " rbitfld.byte 0x00 0. " CSTAT ,Connection status flag" "Disconnected,Connected" endif if (((d.b(ad:0x40050000+0x2101))&0x4)==0x4) group.byte 0x2109++0x0 line.byte 0x0 "HFCOMP,SOF Interrupt Frame Compare Register" else rgroup.byte 0x2109++0x0 line.byte 0x0 "HFCOMP,SOF Interrupt Frame Compare Register" endif group.byte 0x2110++0x0 line.byte 0x0 "HRTIMER2,The Retry Timer Setup Register bits [17,16]" bitfld.byte 0x0 0.--1. " RTIMER2 ,The Retry Timer Setup Register bits [17,16]" "0,1,2,3" group.word 0x210C++0x1 line.word 0x0 "HRTIMER,The Retry Timer Setup Register bits [15,0]" hexmask.word.byte 0x0 8.--15. 1. " RTIMER1 ,The Retry Timer Setup Register bits [15,8]" hexmask.word.byte 0x0 0.--7. 1. " RTIMER0 ,The Retry Timer Setup Register bits [7,0]" group.byte 0x2111++0x0 line.byte 0x0 "HADR,Host Address Register" hexmask.byte 0x0 0.--6. 1. " ADDRESS ,Address bits" group.word 0x2114++0x1 line.word 0x0 "HEOF,EOF Setup Register" hexmask.word.byte 0x0 8.--13. 1. " EOF1 ,End Of Frame bits[13,8]" hexmask.word.byte 0x0 0.--7. 1. " EOF0 ,End Of Frame bits[7,0]" if (((d.b(ad:0x40050000+0x2108))&0x8)==0x0) group.word 0x2118++0x1 line.word 0x0 "HFRAME,Frame Setup Register" bitfld.word 0x0 8.--10. " FRAME1 ,Frame setting bits [10,8]" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 0.--7. 1. " FRAME0 ,Frame setting bits [7,0]" else rgroup.word 0x2118++0x1 line.word 0x0 "HFRAME,Frame Setup Register" bitfld.word 0x0 8.--10. " FRAME1 ,Frame setting bits [10,8]" "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 0.--7. 1. " FRAME0 ,Frame setting bits [7,0]" endif group.byte 0x211C++0x0 line.byte 0x0 "HTOKEN,Host Token Endpoint Register" bitfld.byte 0x00 7. " TGGL ,Toggle bit" "DATA0,DATA1" bitfld.byte 0x00 4.--6. " TKNEN ,Token enable bits" "No data,SETUP,IN,OUT,SOF,Isochronous IN,Isochronous OUT,?..." sif (cpu()=="MB9AF311K")||(cpu()=="MB9AF312K")||(cpu()=="MB9AF311L")||(cpu()=="MB9AF312L")||(cpu()=="MB9AF314L")||(cpu()=="MB9AF311M")||(cpu()=="MB9AF312M")||(cpu()=="MB9AF314M")||(cpu()=="MB9AF315M")||(cpu()=="MB9AF316M")||(cpu()=="MB9AF311N")||(cpu()=="MB9AF312N")||(cpu()=="MB9AF314N")||(cpu()=="MB9AF315N")||(cpu()=="MB9AF316N")||(cpu()=="MB9AF341L")||(cpu()=="MB9AF342L")||(cpu()=="MB9AF344L")||(cpu()=="MB9AF341M")||(cpu()=="MB9AF342M")||(cpu()=="MB9AF344M")||(cpu()=="MB9AF341N")||(cpu()=="MB9AF342N")||(cpu()=="MB9AF344N")||(cpu()=="MB9AFB41L")||(cpu()=="MB9AFB42L")||(cpu()=="MB9AFB44L")||(cpu()=="MB9AFB41M")||(cpu()=="MB9AFB42M")||(cpu()=="MB9AFB44M")||(cpu()=="MB9AFB41N")||(cpu()=="MB9AFB42N")||(cpu()=="MB9AFB44N")||(cpu()=="MB9BF512N")||(cpu()=="MB9BF514N")||(cpu()=="MB9BF515N")||(cpu()=="MB9BF516N")||(cpu()=="MB9BF512R")||(cpu()=="MB9BF514R")||(cpu()=="MB9BF515R")||(cpu()=="MB9BF516R")||(cpu()=="MB9BF516S")||(cpu()=="MB9BF517S")||(cpu()=="MB9BF518S")||(cpu()=="MB9BF516T")||(cpu()=="MB9BF517T")||(cpu()=="MB9BF518T")||(cpu()=="MB9BF616S")||(cpu()=="MB9BF617S")||(cpu()=="MB9BF618S")||(cpu()=="MB9BF616T")||(cpu()=="MB9BF617T")||(cpu()=="MB9BF618T") bitfld.byte 0x00 0.--3. " ENDPT ,Selects ENDPoint" "0,1,2,3,4,5,?..." else bitfld.byte 0x00 0.--3. " ENDPT ,END Point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif tree.end width 0xb tree.end endif tree.end endif sif (cpuis("MB9BF21?S")||cpuis("MB9BF21?T")||cpuis("MB9BF61?S")||cpuis("MB9BF61?T")) tree.open "Ethernet-MAC" tree "Ethernet System Control Block Registers" base ad:0x40066000 width 10. group.long 0x00++0x03 line.long 0x00 "ETH_MODE,Mode select register" sif (cpuis("MB9BF21?S")||cpuis("MB9BF21?T")) bitfld.long 0x00 28. " PPSSEL ,Selects the system time counter pulse output" "Channel 0," else bitfld.long 0x00 28. " PPSSEL ,Selects the system time counter pulse output" "Channel 0,Channel 1" bitfld.long 0x00 9. " RST1 ,Control hardware reset signal against Ethernet-MAC ch.1" "No reset,Reset" endif bitfld.long 0x00 8. " RST0 ,Control hardware reset signal against Ethernet-MAC ch.0" "No reset,Reset" bitfld.long 0x00 0. " IFMODE ,Select the connection of the MII/RMII mode" "MII,RMII" if (((d.l(ad:0x40066000))&0x01)==0x01) group.long 0x04++0x03 line.long 0x00 "ETH_CLKG,Clock Gating Register" sif (cpuis("MB9BF21?S")||cpuis("MB9BF21?T")) bitfld.long 0x00 0.--1. " MACEN ,Select the system clock supply to Ethernet-MAC" "Stopped,Started,?..." else bitfld.long 0x00 0.--1. " MACEN ,Select the system clock supply to Ethernet-MAC" "Stopped CH0 & CH1,Started CH0/Stopped CH1,Started CH0 & CH1,?..." endif else group.long 0x04++0x03 line.long 0x00 "ETH_CLKG,Clock Gating Register" sif (cpuis("MB9BF21?S")||cpuis("MB9BF21?T")) bitfld.long 0x00 0.--1. " MACEN ,Select the system clock supply to Ethernet-MAC" "Stopped,Started,?..." else bitfld.long 0x00 0.--1. " MACEN ,Select the system clock supply to Ethernet-MAC" "Stopped CH0 & CH1,Started CH0/Stopped CH1,?..." endif endif width 0xb tree.end tree "Channel 0" base ad:0x40064000 width 8. tree.open "GMAC Registers" if (((d.l(ad:0x40064000))&0x800)==0x800) if (((d.l(ad:0x40064000))&0x8000)==0x8000) group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit" bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 14. " FES ,Communication speed" "10 Mbps,100 Mbps" textline " " bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit" bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" textline " " bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" textline " " bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" endif else if (((d.l(ad:0x40064000))&0x8000)==0x8000) group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,..." bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 14. " FES ,Communication speed" "10 Mbps,100 Mbps" textline " " bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DR ,Disable Retry" "No,Yes" bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" bitfld.long 0x00 5.--6. " BL ,Back-off Limit" "10,8,4,1" bitfld.long 0x00 4. " DC ,Deferral Check" "No check,Check" textline " " bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,..." bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" textline " " bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" bitfld.long 0x00 9. " DR ,Disable Retry" "No,Yes" textline " " bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" bitfld.long 0x00 5.--6. " BL ,Back-off Limit" "10,8,4,1" bitfld.long 0x00 4. " DC ,Deferral Check" "No check,Check" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" endif endif if ((d.l(ad:0x40064000)&0x800)==0x800) group.long 0x0004++0x03 line.long 0x00 "MFFR,MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive All" "No,Yes" bitfld.long 0x00 10. " HPF ,Hash or Perfect Filter" "Hash,Hash/Perfect" bitfld.long 0x00 9. " SAF ,Source Address Filter" "Not filtered,Filtered" bitfld.long 0x00 8. " SAIF ,Source Address Inverse Filter" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass Control Frames" "None,All except PAUSE,All,Filtered" bitfld.long 0x00 5. " DB ,Disable Broadcast Frames" "No,Yes" bitfld.long 0x00 4. " PM ,Pass All Multicast" "No,Yes" bitfld.long 0x00 3. " DAIF , DA Inverse Filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HMC ,Hash Multicast" "Perfect,Hash" bitfld.long 0x00 1. " HUC ,Hash Unicast" "Perfect,Hash" bitfld.long 0x00 0. " PR ,Promiscuous Mode" "Disabled,Enabled" else group.long 0x0004++0x03 line.long 0x00 "MFFR,MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive All" "No,Yes" bitfld.long 0x00 10. " HPF ,Hash or Perfect Filter" "Hash,Hash/Perfect" bitfld.long 0x00 9. " SAF ,Source Address Filter" "Not filtered,Filtered" bitfld.long 0x00 8. " SAIF ,Source Address Inverse Filter" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass Control Frames" "None,,All,Filtered" bitfld.long 0x00 5. " DB ,Disable Broadcast Frames" "No,Yes" bitfld.long 0x00 4. " PM ,Pass All Multicast" "No,Yes" bitfld.long 0x00 3. " DAIF , DA Inverse Filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HMC ,Hash Multicast" "Perfect,Hash" bitfld.long 0x00 1. " HUC ,Hash Unicast" "Perfect,Hash" bitfld.long 0x00 0. " PR ,Promiscuous Mode" "Disabled,Enabled" endif group.long 0x0008++0x07 line.long 0x00 "MHTRH,MAC Hash Table Register High" line.long 0x00 "MHTRL,MAC Hash Table Register Low" group.long 0x0010++0x07 line.long 0x00 "GAR,GMII/MII Address Register" bitfld.long 0x00 11.--15. " PA ,Physical Layer Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--10. " GR ,GMII Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " CR ,Application Clock Range (SYS_CLK divider)" "/42,/62,/16,/26,/102,/122,?..." textline " " bitfld.long 0x00 1. " GW ,GMII/MII Write" "Read operation,Write operation" bitfld.long 0x00 0. " GB ,GMII/MII Busy" "Idle,Busy" line.long 0x04 "GDR,GMII/MII Data Register" hexmask.long.word 0x04 0.--15. 1. " GD ,GMII/MII Data Register" if ((d.l(ad:0x40064000)&0x800)==0x800) group.long 0x0018++0x03 line.long 0x00 "FCR,Flow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause Time" bitfld.long 0x00 3. " UP ,Unicast Pause Frame detect" "No detection,Detection" bitfld.long 0x00 2. " RFE ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TFE ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 0. " FCB ,Flow Control Busy" "Idle,Pause initiated" else group.long 0x0018++0x03 line.long 0x00 "FCR,Flow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause Time" bitfld.long 0x00 3. " UP ,Unicast Pause Frame detect" "No detection,Detection" bitfld.long 0x00 2. " RFE ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TFE ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 0. " BPA ,Backpressure Activate" "Not active,Active" endif if ((d.l(ad:0x40064000+0x001c)&0x10000)==0x10000) group.long 0x001c++0x03 line.long 0x00 "VTR,VLAN Tag Register" bitfld.long 0x00 16. " ETV ,Enable 12-Bit VLAN Tag Comparison" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " VL ,VLAN Tag Identifier" else group.long 0x001c++0x03 line.long 0x00 "VTR,VLAN Tag Register" bitfld.long 0x00 16. " ETV ,Enable 12-Bit VLAN Tag Comparison" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " VL ,VLAN Tag Identifier" endif group.long 0x0028++0x03 line.long 0x00 "RWFRR,Remote Wake-up Frame Filter Register" hgroup.long 0x002c++0x07 hide.long 0x00 "PMTR,PMT Register" in hide.long 0x04 "LPICSR,LPI Control and Status Register" in group.long 0x0034++0x03 line.long 0x00 "LPITCR,LPI Timers Control Register" hexmask.long.word 0x00 16.--25. 1. " LIT ,LPI LS TIMER" hexmask.long.word 0x00 0.--15. 1. " TWT ,LPI TW TIMER" rgroup.long 0x0038++0x03 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 10. " LPIIS ,LPI Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 9. " TSIS ,Time Stamp Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 7. " COIS ,MMC Receive Checksum Offload Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " TIS ,MMC Transmit Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " RIS ,MMC Receive Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 4. " MIS ,MMC Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " PIS ,PMT Interrupt Status" "No interrupt,Interrupt" group.long 0x003c++0x03 line.long 0x00 "IMR,Interrupt Mask Register" bitfld.long 0x00 10. " LPIIM ,LPI Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " TSIM ,Time Stamp Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 3. " PIM ,PMT Interrupt Mask" "Not masked,Masked" tree "Mask Address Registers 0-15" group.long 0x0040++0x07 line.long 0x00 "MAR0H,MAC Address0 Register High" rbitfld.long 0x00 31. " MO ,Must be one" ",One" hexmask.long.word 0x00 0.--15. 1. " A0[47:32] ,MAC Address0[47:32]" line.long 0x04 "MAR0L,MAC Address0 Register Low" group.long 0x48++0x07 line.long 0x00 "MAR1H,MAC Address1 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 1" line.long 0x04 "MAR1L,MAC Address1 Register Low" group.long 0x50++0x07 line.long 0x00 "MAR2H,MAC Address2 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 2" line.long 0x04 "MAR2L,MAC Address2 Register Low" group.long 0x58++0x07 line.long 0x00 "MAR3H,MAC Address3 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 3" line.long 0x04 "MAR3L,MAC Address3 Register Low" group.long 0x60++0x07 line.long 0x00 "MAR4H,MAC Address4 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 4" line.long 0x04 "MAR4L,MAC Address4 Register Low" group.long 0x68++0x07 line.long 0x00 "MAR5H,MAC Address5 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 5" line.long 0x04 "MAR5L,MAC Address5 Register Low" group.long 0x70++0x07 line.long 0x00 "MAR6H,MAC Address6 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 6" line.long 0x04 "MAR6L,MAC Address6 Register Low" group.long 0x78++0x07 line.long 0x00 "MAR7H,MAC Address7 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 7" line.long 0x04 "MAR7L,MAC Address7 Register Low" group.long 0x80++0x07 line.long 0x00 "MAR8H,MAC Address8 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 8" line.long 0x04 "MAR8L,MAC Address8 Register Low" group.long 0x88++0x07 line.long 0x00 "MAR9H,MAC Address9 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 9" line.long 0x04 "MAR9L,MAC Address9 Register Low" group.long 0x90++0x07 line.long 0x00 "MAR10H,MAC Address10 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 10" line.long 0x04 "MAR10L,MAC Address10 Register Low" group.long 0x98++0x07 line.long 0x00 "MAR11H,MAC Address11 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 11" line.long 0x04 "MAR11L,MAC Address11 Register Low" group.long 0xA0++0x07 line.long 0x00 "MAR12H,MAC Address12 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 12" line.long 0x04 "MAR12L,MAC Address12 Register Low" group.long 0xA8++0x07 line.long 0x00 "MAR13H,MAC Address13 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 13" line.long 0x04 "MAR13L,MAC Address13 Register Low" group.long 0xB0++0x07 line.long 0x00 "MAR14H,MAC Address14 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 14" line.long 0x04 "MAR14L,MAC Address14 Register Low" group.long 0xB8++0x07 line.long 0x00 "MAR15H,MAC Address15 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 15" line.long 0x04 "MAR15L,MAC Address15 Register Low" tree.end textline " " if ((d.l(ad:0x40064000+0x0700)&0x4000)==0x0000) group.long 0x0700++0x03 line.long 0x00 "TSCR,Time Stamp Control Register" bitfld.long 0x00 18. " TSENMF ,Enable MAC address for PTP frame filtering" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSPS ,SelectPTP packets for taking snapshots" "SYNC|Follow_Up|Delay_Req|Delay_Resp,SYNC|Follow_Up|Delay_Req|Delay_Resp|PDelay_Req|PDelay_Resp|PDelay_Resp_Follow_Up,SYNC|Delay_Req,PDelay_Req|PDelay_Resp" textline " " bitfld.long 0x00 15. " TSMRM ,Enable Snapshot for Messages Relevant to Master" "Slave,Master" bitfld.long 0x00 14. " TETSEM ,Enable Time Stamp Snapshot for Event Messages" "Not event,Event" bitfld.long 0x00 13. " TSIP4E ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled" bitfld.long 0x00 12. " TSIP6E ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TETSP ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled" bitfld.long 0x00 10. " TSV2E ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled" bitfld.long 0x00 9. " TSDB ,Time Stamp Digital or Binary rollover control" "Digital,Binary" bitfld.long 0x00 8. " TSEA ,Enable Time Stamp for All Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TARU ,Addend Register Update" "Not updated,Updated" bitfld.long 0x00 4. " TITE ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSU ,Time Stamp Update" "No update,Update" bitfld.long 0x00 2. " TSI ,Time Stamp Initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TFCU ,Time Stamp Fine or Coarse Update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time Stapm Enable" "Disabled,Enabled" elif ((d.l(ad:0x40064000+0x0700)&0x8000)==0x0000) group.long 0x0700++0x03 line.long 0x00 "TSCR,Time Stamp Control Register" bitfld.long 0x00 18. " TSENMF ,Enable MAC address for PTP frame filtering" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSPS ,SelectPTP packets for taking snapshots" "SYNC,SYNC|PDelay_Req|PDelay_Resp,SYNC|Delay_Req,PDelay_Req|PDelay_Resp" textline " " bitfld.long 0x00 15. " TSMRM ,Enable Snapshot for Messages Relevant to Master" "Slave,Master" bitfld.long 0x00 14. " TETSEM ,Enable Time Stamp Snapshot for Event Messages" "Not event,Event" bitfld.long 0x00 13. " TSIP4E ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled" bitfld.long 0x00 12. " TSIP6E ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TETSP ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled" bitfld.long 0x00 10. " TSV2E ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled" bitfld.long 0x00 9. " TSDB ,Time Stamp Digital or Binary rollover control" "Digital,Binary" bitfld.long 0x00 8. " TSEA ,Enable Time Stamp for All Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TARU ,Addend Register Update" "Not updated,Updated" bitfld.long 0x00 4. " TITE ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSU ,Time Stamp Update" "No update,Update" bitfld.long 0x00 2. " TSI ,Time Stamp Initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TFCU ,Time Stamp Fine or Coarse Update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time Stapm Enable" "Disabled,Enabled" else group.long 0x0700++0x03 line.long 0x00 "TSCR,Time Stamp Control Register" bitfld.long 0x00 18. " TSENMF ,Enable MAC address for PTP frame filtering" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSPS ,SelectPTP packets for taking snapshots" "Delay_Req,Delay_Req|PDelay_Req|PDelay_Resp,SYNC|Delay_Req,PDelay_Req|PDelay_Resp" textline " " bitfld.long 0x00 15. " TSMRM ,Enable Snapshot for Messages Relevant to Master" "Slave,Master" bitfld.long 0x00 14. " TETSEM ,Enable Time Stamp Snapshot for Event Messages" "Not event,Event" bitfld.long 0x00 13. " TSIP4E ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled" bitfld.long 0x00 12. " TSIP6E ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TETSP ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled" bitfld.long 0x00 10. " TSV2E ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled" bitfld.long 0x00 9. " TSDB ,Time Stamp Digital or Binary rollover control" "Digital,Binary" bitfld.long 0x00 8. " TSEA ,Enable Time Stamp for All Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TARU ,Addend Register Update" "Not updated,Updated" bitfld.long 0x00 4. " TITE ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSU ,Time Stamp Update" "No update,Update" bitfld.long 0x00 2. " TSI ,Time Stamp Initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TFCU ,Time Stamp Fine or Coarse Update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time Stapm Enable" "Disabled,Enabled" endif group.long 0x0704++0x3 line.long 0x00 "SSIR,Sub-Second Increment Register" hexmask.long.byte 0x00 0.--7. 1. " SSINC ,Sub-Second Increment Value" rgroup.long 0x0708++0x07 line.long 0x00 "STSR,System Time - Seconds Register" line.long 0x04 "STNR,System Time - Nanoseconds Register" hexmask.long 0x04 0.--30. 1. " TSSS ,Time Stamp Sub-Seconds" group.long 0x0710++0x17 line.long 0x00 "STSUR,System Time - Seconds Update Register" line.long 0x04 "STNUR,System Time - Nanoseconds Update Register" bitfld.long 0x04 31. " ADDSUB ,Add or Subtract Time" "Add,Substract" hexmask.long 0x04 0.--30. 1. " TSSS ,Time Stamp Sub-Seconds" line.long 0x08 "TSAR,Time Stamp Addend Register" line.long 0x0c "TTSR,Target Time Seconds Register" line.long 0x10 "TTNR,Target Time Nanoseconds Register" hexmask.long 0x10 0.--30. 1. " TSTR ,Target Time Stamp Nanoseconds Register" line.long 0x14 "STHWSR,System Time - Higher Word Seconds Register" hexmask.long.word 0x14 0.--15. 1. " TSHWR ,System Time - Higher Word Seconds Register" hgroup.long 0x0728++0x03 hide.long 0x00 "TSR,Time Stamp Status Register" in if ((d.l(ad:0x40064000+0x0700)&0x200)==0x00) group.long 0x072c++0x03 line.long 0x00 "PPSCR,PPS Control Register" bitfld.long 0x00 0.--3. " PPSCTRL ,Controls the frequency of the PPS output" ",1Hz,2Hz,4Hz,8Hz,16Hz,32Hz,64Hz,128Hz,256Hz,512Hz,1.024KHz,2.048KHz,4.096KHz,8.192KHz,16.384KHz" else group.long 0x072c++0x03 line.long 0x00 "PPSCR,PPS Control Register" bitfld.long 0x00 0.--3. " PPSCTRL ,Controls the frequency of the PPS output" ",2Hz,4Hz,8Hz,16Hz,32Hz,64Hz,128Hz,256Hz,512Hz,1.024KHz,2.048KHz,4.096KHz,8.192KHz,16.384KHz,32.768KHz" endif hgroup.long 0x0730++0x07 hide.long 0x00 "ATNR,Auxiliary Time Stamp - Nanoseconds Register" hide.long 0x04 "ATSR,Auxiliary Time Stamp - Seconds Register" tree "Mask Address Registers 16-31" group.long 0x800++0x07 line.long 0x00 "MAR16H,MAC Address16 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 16" line.long 0x04 "MAR16L,MAC Address16 Register Low" group.long 0x808++0x07 line.long 0x00 "MAR17H,MAC Address17 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 17" line.long 0x04 "MAR17L,MAC Address17 Register Low" group.long 0x810++0x07 line.long 0x00 "MAR18H,MAC Address18 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 18" line.long 0x04 "MAR18L,MAC Address18 Register Low" group.long 0x818++0x07 line.long 0x00 "MAR19H,MAC Address19 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 19" line.long 0x04 "MAR19L,MAC Address19 Register Low" group.long 0x820++0x07 line.long 0x00 "MAR20H,MAC Address20 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 20" line.long 0x04 "MAR20L,MAC Address20 Register Low" group.long 0x828++0x07 line.long 0x00 "MAR21H,MAC Address21 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 21" line.long 0x04 "MAR21L,MAC Address21 Register Low" group.long 0x830++0x07 line.long 0x00 "MAR22H,MAC Address22 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 22" line.long 0x04 "MAR22L,MAC Address22 Register Low" group.long 0x838++0x07 line.long 0x00 "MAR23H,MAC Address23 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 23" line.long 0x04 "MAR23L,MAC Address23 Register Low" group.long 0x840++0x07 line.long 0x00 "MAR24H,MAC Address24 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 24" line.long 0x04 "MAR24L,MAC Address24 Register Low" group.long 0x848++0x07 line.long 0x00 "MAR25H,MAC Address25 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 25" line.long 0x04 "MAR25L,MAC Address25 Register Low" group.long 0x850++0x07 line.long 0x00 "MAR26H,MAC Address26 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 26" line.long 0x04 "MAR26L,MAC Address26 Register Low" group.long 0x858++0x07 line.long 0x00 "MAR27H,MAC Address27 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 27" line.long 0x04 "MAR27L,MAC Address27 Register Low" group.long 0x860++0x07 line.long 0x00 "MAR28H,MAC Address28 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 28" line.long 0x04 "MAR28L,MAC Address28 Register Low" group.long 0x868++0x07 line.long 0x00 "MAR29H,MAC Address29 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 29" line.long 0x04 "MAR29L,MAC Address29 Register Low" group.long 0x870++0x07 line.long 0x00 "MAR30H,MAC Address30 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 30" line.long 0x04 "MAR30L,MAC Address30 Register Low" group.long 0x878++0x07 line.long 0x00 "MAR31H,MAC Address31 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 31" line.long 0x04 "MAR31L,MAC Address31 Register Low" tree.end textline " " tree.end tree.open "DMA Registers" if ((d.l(ad:0x40064000+0x1000)&0x1010000)==0x00) if ((d.l(ad:0x40064000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" textline " " bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif elif ((d.l(ad:0x40064000+0x1000)&0x1010000)==0x10000) if ((d.l(ad:0x40064000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif elif ((d.l(ad:0x40064000+0x1000)&0x1010000)==0x1000000) if ((d.l(ad:0x40064000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif else if ((d.l(ad:0x40064000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,?..." textline " " bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif endif group.long 0x1004++0x13 line.long 0x00 "TPDR,Transmit Poll Demand Register" line.long 0x04 "RPDR,Receive Poll Demand Register" line.long 0x08 "RDLAR,Receive Descriptor List Address Register" hexmask.long 0x08 2.--31. 1. " SRL ,Start of Receive List" line.long 0x0c "TDLAR,Receive Descriptor List Address Register" hexmask.long 0x0c 2.--31. 1. " STL ,Start of Transmit List" if (((d.l(ad:0x40064000+0x1014))&0x2000)==0x2000) group.long 0x1014++0x03 line.long 0x00 "SR,Status Register" rbitfld.long 0x00 30. " GLPII ,GMAC LPI Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 29. " TTI ,Time-Stamp Trigger Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " GPI ,GMAC PMT Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 27. " GMI ,GMAC MMC Interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x00 25. " EB[2] ,Error Bits" "Data buffer,Descriptor" rbitfld.long 0x00 24. " EB[1] ,Error Bits" "Write,Read" rbitfld.long 0x00 23. " EB[0] ,Error Bits" "Receive DMA,Transmit DMA" rbitfld.long 0x00 20.--22. " TS ,Transmit Process State" "Stopped,Fetching Transmit Transfer Descriptor,Waiting for status,Reading,Time-Stamp write,,Suspended,Closing Transmit Descriptor" textline " " rbitfld.long 0x00 17.--19. " RS ,Receive Process State" "Stopped,Fetching Receive Transfer Descriptor,,Waiting for receive packet,Suspended,Closing Receive Descriptor,Time-Stamp write,Transferring" eventfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "Low,High" eventfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "Low,High" eventfld.long 0x00 14. " ERI ,Early Receive Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " RWT ,Receive Watchdog Timeout" "No timeout,Timeout" eventfld.long 0x00 8. " RPS ,Receive process Stopped" "Running,Stopped" textline " " eventfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 6. " RI ,Receive Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " UNF ,Transmit underflow" "Not occurred,Occurred" eventfld.long 0x00 4. " OVF ,Receive Overflow" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "No timeout,Timeout" eventfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 1. " TPS ,Transmit Process Stopped" "Running,Stopped" eventfld.long 0x00 0. " TI ,Transmit Interrupt" "No interrupt,Interrupt" else group.long 0x1014++0x03 line.long 0x00 "SR,Status Register" rbitfld.long 0x00 30. " GLPII ,GMAC LPI Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 29. " TTI ,Time-Stamp Trigger Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " GPI ,GMAC PMT Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 27. " GMI ,GMAC MMC Interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x00 20.--22. " TS ,Transmit Process State" "Stopped,Fetching Transmit Transfer Descriptor,Waiting for status,Reading,Time-Stamp write,,Suspended,Closing Transmit Descriptor" rbitfld.long 0x00 17.--19. " RS ,Receive Process State" "Stopped,Fetching Receive Transfer Descriptor,,Waiting for receive packet,Suspended,Closing Receive Descriptor,Time-Stamp write,Transferring" eventfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "Low,High" eventfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "Low,High" textline " " eventfld.long 0x00 14. " ERI ,Early Receive Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " RWT ,Receive Watchdog Timeout" "No timeout,Timeout" textline " " eventfld.long 0x00 8. " RPS ,Receive process Stopped" "Running,Stopped" eventfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 6. " RI ,Receive Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " UNF ,Transmit underflow" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " OVF ,Receive Overflow" "Not occurred,Occurred" eventfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "No timeout,Timeout" eventfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 1. " TPS ,Transmit Process Stopped" "Running,Stopped" textline " " eventfld.long 0x00 0. " TI ,Transmit Interrupt" "No interrupt,Interrupt" endif if (((d.l(ad:0x40064000+0x1018))&0x200000)==0x200000) if (((d.l(ad:0x40064000+0x1018))&0x2000000)==0x2000000) group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" textline " " bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "64,32,96,128" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" else group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" textline " " bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" endif else if (((d.l(ad:0x40064000+0x1018))&0x2000000)==0x2000000) group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control [bytes]" "64,128,192,256,40,32,24,16" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" textline " " bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "64,32,96,128" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" else group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control [bytes]" "64,128,192,256,40,32,24,16" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" textline " " bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" endif endif group.long 0x101C++0x07 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 16. " NIE ,Normal Interrupt Summary Enable" "Disabled,Enabled" bitfld.long 0x00 15. " AIE ,Abnormal Interrupt Summary Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ERE ,Early Receive Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x00 13. " FBE ,Fatal Bus Error Enable" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " ETE ,Early Transmit Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x00 9. " RWE ,Receive Watchdog Timeout Enable" "No timeout,Timeout" bitfld.long 0x00 8. " RSE ,Receive process Stopped Enable" "Running,Stopped" bitfld.long 0x00 7. " RUE ,Receive Buffer Unavailable Enable" "Available,Unavailabe" textline " " bitfld.long 0x00 6. " RIE ,Receive Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x00 5. " UNE ,Transmit underflow Enable" "Not occurred,Occurred" bitfld.long 0x00 4. " OVE ,Receive Overflow Enable" "Not occurred,Occurred" bitfld.long 0x00 3. " TJE ,Transmit Jabber Timeout" "No timeout,Timeout" textline " " bitfld.long 0x00 2. " TUE ,Transmit Buffer Unavailable Enable" "Available,Unavailabe" bitfld.long 0x00 1. " TSE ,Transmit Process Stopped Enable" "Running,Stopped" eventfld.long 0x00 0. " TIE ,Transmit Interrupt Enable" "No interrupt,Interrupt" hgroup.long 0x1020++0x03 hide.long 0x00 "MFBOCR,Missed Frame and Buffer Overflow Counter Register" in group.long 0x1024++0x03 line.long 0x00 "RIWTR,Receive Interrupt Watchdog Timer Register" hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI Watchdog Timer count" rgroup.long 0x102c++0x03 line.long 0x00 "AHBSR,AHB Status Register" bitfld.long 0x00 0. " AHBS ,AHB Status" "Idle,Non-idle" rgroup.long 0x1048++0x0f line.long 0x00 "CHTDR,Current Host Transmit Descriptor Register" line.long 0x04 "CHRDR,Current Host Receive Descriptor Register" line.long 0x08 "CHTBAR,Current Host Transmit Buffer Address Register" line.long 0x0c "CHRBAR,Current Host Receive Buffer Address Register" tree.end width 22. tree "MMC Registers" group.long 0x0100++0x03 line.long 0x00 "MMC_CNT,MMC Control Register" bitfld.long 0x00 5. " FHP ,Full-Half preset" "Almost-half-value,Almost-full-value" bitfld.long 0x00 4. " CP , Counters Preset" "No preset,Preset" bitfld.long 0x00 3. " MCF ,MMC Counter Freeze" "Not frozen,Frozen" textline " " bitfld.long 0x00 2. " ROR ,Reset on read" "No reset,Reset" bitfld.long 0x00 1. " CSR ,Counter Stop Rollover" "Rollover,No rollover" bitfld.long 0x00 0. " CR ,Counter reset" "No reset,Reset" hgroup.long 0x0104++0x07 hide.long 0x00 "MMC_INTR_RX,MMC Receive Interrupt Register" in hide.long 0x04 "MMC_INTR_TX,MMC Transmit Interrupt Register" in group.long 0x010c++0x03 line.long 0x00 "MMC_INTR_MASK_RX,MMC Receive Interrupt Mask Interrupt Register" bitfld.long 0x00 23. " RXWTDEIM ,Rxwatchdogerror Counter Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 22. " RXVLFIM ,Rxvlanframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 21. " RXFOFIM ,Rxfifooverflow_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 20. " RXPFIM ,Rxpauseframes Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RXORTIM ,Rxoutofrangetype Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 18. " RXLCIM ,Rxlengtherror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 17. " RXUCFIM ,Rxunicastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 16. " RX1024_MAXIM ,Rx1024tomaxoctets_g Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " RX512_1024IM ,Rx512to1023octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 14. " RX256_511IM ,Rx256to511octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 13. " RX128_256IM ,Rx128to255maxoctects_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 12. " RX65_127IM ,Rx65to127maxoctets_gb Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RX64IM ,Rxto64octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 10. " RXOSIM ,Rxoversize_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " RXUSIM ,Rxundersize_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 8. " RXJERIM ,Rxjabbererror Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RXRUNTERIM ,Rxrunterror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 6. " RXALTERIM ,Rxallignmenterror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 5. " RXCRCERIM ,Rxcrcerror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 4. " RXMCFIM ,Rxmulticastframes_g Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " RXBCFIM ,Rxbroadcastframes_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 2. " RXOCGIM ,Rxoctetcounter_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " RXOCGBIM ,Rxoctetcounter_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 0. " RXFCIM ,Rxframecount_gb Counter Interrupt Mask" "Not masked,Masked" group.long 0x0110++0x03 line.long 0x00 "MMC_INTR_MASK_TX,MMC Transmit Interrupt Mask Register" bitfld.long 0x00 24. " TXVLFIM ,Txvlanframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 23. " TXPFIM ,Txpauseframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 22. " TXOCIM ,Txoexcessdef Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 21. " TXFCIM ,Txframecount Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 20. " TXOCIM ,Txoctetcount Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 19. " TXCERIM ,Txcarriererror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 18. " TXLXSIM ,Txlexesscol Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 17. " YXLCIM ,Txlatecol Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 16. " TXDEFIM ,Txdeffer Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 15. " TXMCIM ,Txmulticol_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 14. " TXSCIM ,Txsinglecol_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 13. " TXUFERIM ,Txunderflowerror Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 12. " TXBCFGBIM ,Txbroadcastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 11. " TXMCFGBIM ,Txmulticastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 10. " TXUCFIM ,Txunicastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " TX1024_MAXIM ,Tx1024tomaxoctets_g Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " TX512_1023IM ,Tx512to1023octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 7. " TX256_511IM ,Tx256to511octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 6. " TX128_256IM ,Tx128to255maxoctects_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 5. " TX65_127IM ,Tx65to127maxoctets_gb Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " TX64IM ,Txto64octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 3. " TXMCFGIM ,Txmalticastframes_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 2. " TXBCGIM ,Txbroadcastframes_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " TXFCGBIM ,Txframecount_gb Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " TXOCGBIM ,Txoctetcount_gb Counter Interrupt Mask" "Not masked,Masked" group.long 0x0200++0x03 line.long 0x00 "MMC_IPC_INTR_MASK_RX,MMC Receive Checksum Offload Interrupt Mask Register" bitfld.long 0x00 29. " RXICMPEOIM ,Rxicmp_err_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 28. " RXICMPGDOIM ,Rxicmp_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 27. " RXTCPEOIM ,Rxtcp_err_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 26. " RXTCPGDOIM ,Rxtcp_gd_octets Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 25. " RXUDPEOIM ,Rxudp_err_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 24. " RXUDPGDOIM ,Rxudp_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 23. " RXIP6NPOIM ,Rxipv6_nopay_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 22. " RXIP6HDREOIM ,Rxipv6_hdrerr_octets Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 21. " RXIP6GDOIM ,Rxipv6_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 20. " RXIP4UDSBOIE ,Rxipv4_udsbl_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 19. " RXIP4FOIM ,Rxipv4_frag_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 18. " RXIP4NPOIM ,Rxipv4_nopay_octets Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 17. " RXIP4HDREOIM ,Rxipv4_hdrerr_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 16. " RXIP4GDOIM ,Rxipv4_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 13. " RXICMPEFIM ,Rxicmp_err_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 12. " RXICMPGDFIM ,Rxicmp_gd_frms Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RXTCPEFIM ,Rxtcp_err_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 10. " RXTCPGDFIM ,Rxtcp_gd_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " RXUDPEFIM ,Rxudp_err_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 8. " RXUDPGDFIM ,Rxudp_gd_frms Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RXIP6NPFIM ,Rxipv6_nopay_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 6. " RXIP6HDREFIM ,Rxipv6_hdrerr_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 5. " RXIP6GDFIM ,Rxipv6_gd_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 4. " RXIP4UDSBFIM ,Rxipv4_udsbl_frms Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " RXIPV4FFIM ,Rxipv4_frag_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 2. " RXIP4NPFIM ,Rxipv4_nopay_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " RXIP4HDREFIM ,Rxipv4_hdrerr_frms counter Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 0. " RXIP4GDFIM ,Rxipv4_gd_frms Counter Interrupt Mask" "Not masked,Masked" hgroup.long 0x208++0x03 hide.long 0x00 "MMC_IPC_INTR_RX,MMC Receive Checksum Offload Interrupt Register" in tree "MMC Counters" group.long 0x114++0x63 line.long 0x00 "TXOCTETCOUNT_GB,Number of bytes transmitted" line.long 0x04 "TXFRAMECOUNT_GB,Number of good and bad frames transmitted" line.long 0x08 "TXBROADCASTFRAMES_G,Number of good broadcast frames transmitted" line.long 0x0c "TXMULTICASTFRAMES_G,Number of good multicast frames transmitted." line.long 0x10 "TX64OCTETS_GB,Number of good and bad frames transmitted with length of 64 bytes" line.long 0x14 "TX65TO127OCTETS_GB,Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes" line.long 0x18 "TX128TO255OCTETS_GB,Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes," line.long 0x1c "TX256TO511OCTETS_GB,Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes" line.long 0x20 "TX512TO1023OCTETS_GB,Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes" line.long 0x24 "TX1024TOMAXOCTETS_GB,Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes," line.long 0x28 "TXUNICASTFRAMES_GB,Number of good and bad unicast frames transmittedr" line.long 0x2c "TXMULTICASTFRAMES_GB,Number of good and bad multicast frames transmitted" line.long 0x30 "TXBROADCASTFRAMES_GB,Number of good and bad broadcast frames transmitted." line.long 0x34 "TXUNDERFLOWERROR,Number of frames aborted due to frame underflow error" line.long 0x38 "TXSINGLECOL_G,Number of successfully transmitted frames after a single collision in Half-duplex mode" line.long 0x3c "TXMULTICOL_G,Number of successfully transmitted frames after more than a single collision in Half-duplex mode" line.long 0x40 "TXDEFERRED,Number of successfully transmitted frames after a deferral in Half-duplex mode" line.long 0x44 "TXLATECOL,Number of frames aborted due to late collision error." line.long 0x48 "TXEXESSCOL,Number of frames aborted due to excessive (16) collision errors" line.long 0x4c "TXCARRIERERRROR,Number of frames aborted due to carrier sense error" line.long 0x50 "TXOCTETCOUNT_G,Number of bytes transmitted, exclusive of preamble, in good frames only" line.long 0x54 "TXFRAMECOUNT_G,Number of good frames transmitted" line.long 0x58 "TXEXECESSDEF,Number of frames aborted due to excessive deferral error" line.long 0x5c "TXPAUSEFRAMES,Number of good PAUSE frames transmitted" line.long 0x60 "TXVLANFRAMES,Number of good VLAN frames transmitted" group.long 0x180++0x5f line.long 0x00 "RXFRAMECOUNT_GB,Number of good and bad frames received" line.long 0x04 "RXOCTETCOUNT_GB,Number of bytes received" line.long 0x08 "RXOCTETCOUNT_G,Number of bytes received, exclusive of preamble, only in good frames" line.long 0x0c "RXBROADCASTFRAMES_G,Number of good broadcast frames received" line.long 0x10 "RXMULTICASTFRAMES_G,Number of good multicast frames received" line.long 0x14 "RXCRCERROR,Number of frames received with CRC error" line.long 0x18 "RXALLIGNMENTERROR,Number of frames received with alignment (dribble) error" line.long 0x1c "RXRUNTERROR,Number of frames received with runt error" line.long 0x20 "RXJABBERERROR,Number of frames received with length greater than 1518 bytes with CRC error" line.long 0x24 "RXUNDERSIZE_G,Number of frames received with length less than 64 bytes, without any errors" line.long 0x28 "RXOVERSIZE_G,Number of frames received with length greater than the maxsize without error" line.long 0x2c "RX64OCTETS_GB,Number of good and bad frames received with length 64 bytes, exclusive of preamble" line.long 0x30 "RX65TO127OCTETS_GB,Number of good and bad frames received with length 64 bytes, exclusive of preamble" line.long 0x34 "RX128TO255OCTETS_GB,Number of good and bad frames received with length between 128 and 255 (inclusive) bytes" line.long 0x38 "RX256TO511OCTETS_GB,Number of good and bad frames received with length between 256 and 511 (inclusive) bytes" line.long 0x3c "RX512TO1023OCTETS_GB,Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes" line.long 0x40 "RX1024TOMAXOCTETS_GB,Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes" line.long 0x44 "RXUNICASTFRAMES_G,Number of good unicast frames received" line.long 0x48 "RXLENGTHERROR,Number of frames received with length error" line.long 0x4c "RXOUTOFRANGETYPE,Number of frames received with length/type field not equal to the valid frame size" line.long 0x50 "RXPAUSEFRAMES,Number of good and valid PAUSE frames received" line.long 0x54 "RXFIFOOVERFLOW,Number of missed received frames due to FIFO overflow" line.long 0x58 "RXVLANFRAMES_GB,Number of good and bad VLAN frames received" line.long 0x5c "RXWATCHDOGERROR,Number of frames received with error due to watchdog timeout error" group.long 0x210++0x37 line.long 0x00 "RXIPV4_GD_FRMS,Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload" line.long 0x04 "RXIPV4_HDRERR_FRMS,Number of IPv4 datagrams received with header errors" line.long 0x08 "RXIPV4_NOPAY_FRMS,Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine" line.long 0x0c "RXIPV4_FRAG_FRMS,Number of good IPv4 datagrams with fragmentation" line.long 0x10 "RXIPV4_UDSBL_FRMS,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled" line.long 0x14 "RXIPV6_GD_FRMS,Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads" line.long 0x18 "RXIPV6_HDRERR_FRMS,Number of IPv6 datagrams received with header errors" line.long 0x1c "RXIPV6_NOPAY_FRMS,Number of IPv6 datagram frames received without a TCP, UDP, or ICMP payload" line.long 0x20 "RXUDP_GD_FRMS,Number of good IP datagrams with a good UDP payload" line.long 0x24 "RXUDP_ERR_FRMS,Number of good IP datagrams whose UDP payload has a checksum error" line.long 0x28 "RXTCP_GD_FRMS,Number of good IP datagrams with a good TCP payload" line.long 0x2c "RXTCP_ERR_FRMS,Number of good IP datagrams whose TCP payload has a checksum error" line.long 0x30 "RXICMP_GD_FRMS,Number of good IP datagrams with a good ICMP payload" line.long 0x34 "RXICMP_ERR_FRMS,Number of good IP datagrams whose ICMP payload has a checksum error" group.long 0x250++0x37 line.long 0x00 "RXIPV4_GD_OCTETS,Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data" line.long 0x04 "RXIPV4_HDRERR_OCTETS,Number of bytes received in IPv4 datagrams with header errors" line.long 0x08 "RXIPV4_NOPAY_OCTETS,Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload" line.long 0x0c "RXIPV4_FRAG_OCTETS,Number of bytes received in fragmented IPv4 datagrams" line.long 0x10 "RXIPV4_UDSBL_OCTETS,Number of bytes received in a UDP segment that had the UDP checksum disabled" line.long 0x14 "RXIPV6_GD_OCTETS,Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data" line.long 0x18 "RXIPV6_HDRERR_OCTETS,Number of bytes received in IPv6 datagrams with header errors" line.long 0x1c "RXIPV6_NOPAY_OCTETS,Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload" line.long 0x20 "RXUDP_GD_OCTETS,Number of bytes received in a good UDP segment" line.long 0x24 "RXUDP_ERR_OCTETS,Number of bytes received in a UDP segment that had checksum errors" line.long 0x28 "RXTCP_GD_OCTETS,Number of bytes received in a good TCP segment" line.long 0x2c "RXTCP_ERR_OCTETS,Number of bytes received in a TCP segment with checksum errors" line.long 0x30 "RXICMP_GD_OCTETS,Number of bytes received in a good ICMP segment" line.long 0x34 "RXICMP_ERR_OCTETS,Number of bytes received in an ICMP segment with checksum errors" tree.end tree.end width 0xb tree.end sif (cpuis("MB9BF61?S")||cpuis("MB9BF61?T")) tree "Channel 1" base ad:0x40067000 width 8. tree.open "GMAC Registers" if (((d.l(ad:0x40067000))&0x800)==0x800) if (((d.l(ad:0x40067000))&0x8000)==0x8000) group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit" bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 14. " FES ,Communication speed" "10 Mbps,100 Mbps" textline " " bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,56 bit,48 bit,40 bit" bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" textline " " bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" textline " " bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" endif else if (((d.l(ad:0x40067000))&0x8000)==0x8000) group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,..." bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 14. " FES ,Communication speed" "10 Mbps,100 Mbps" textline " " bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DR ,Disable Retry" "No,Yes" bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" bitfld.long 0x00 5.--6. " BL ,Back-off Limit" "10,8,4,1" bitfld.long 0x00 4. " DC ,Deferral Check" "No check,Check" textline " " bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "MCR,MAC Configuration Register" bitfld.long 0x00 25. " CST ,CRC stripping for Type frames" "No,Yes" bitfld.long 0x00 23. " WD ,Watchdog Disable" "No,Yes" bitfld.long 0x00 22. " JD ,Jabber Disable" "No,Yes" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17.--19. " IFG ,Inter-Frame GAP" "96 bit,88 bit,80 bit,72 bit,64 bit,..." bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense During Transaction" "No,Yes" bitfld.long 0x00 15. " PS ,Port Select" "MII,RMII" bitfld.long 0x00 13. " DO ,Disable Receive Own" "No,Yes" textline " " bitfld.long 0x00 12. " LM ,Loop-back Mode" "Normal,Loop-back" bitfld.long 0x00 11. " DM ,Duplex mode" "Half-duplex,Full-duplex" bitfld.long 0x00 10. " IPC ,Checksum Offload Enable" "Disabled,Enabled" bitfld.long 0x00 9. " DR ,Disable Retry" "No,Yes" textline " " bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "No stripping,Stripping" bitfld.long 0x00 5.--6. " BL ,Back-off Limit" "10,8,4,1" bitfld.long 0x00 4. " DC ,Deferral Check" "No check,Check" bitfld.long 0x00 3. " TE ,Transmitter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RE ,Receiver Enable" "Disabled,Enabled" endif endif if ((d.l(ad:0x40067000)&0x800)==0x800) group.long 0x0004++0x03 line.long 0x00 "MFFR,MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive All" "No,Yes" bitfld.long 0x00 10. " HPF ,Hash or Perfect Filter" "Hash,Hash/Perfect" bitfld.long 0x00 9. " SAF ,Source Address Filter" "Not filtered,Filtered" bitfld.long 0x00 8. " SAIF ,Source Address Inverse Filter" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass Control Frames" "None,All except PAUSE,All,Filtered" bitfld.long 0x00 5. " DB ,Disable Broadcast Frames" "No,Yes" bitfld.long 0x00 4. " PM ,Pass All Multicast" "No,Yes" bitfld.long 0x00 3. " DAIF , DA Inverse Filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HMC ,Hash Multicast" "Perfect,Hash" bitfld.long 0x00 1. " HUC ,Hash Unicast" "Perfect,Hash" bitfld.long 0x00 0. " PR ,Promiscuous Mode" "Disabled,Enabled" else group.long 0x0004++0x03 line.long 0x00 "MFFR,MAC Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive All" "No,Yes" bitfld.long 0x00 10. " HPF ,Hash or Perfect Filter" "Hash,Hash/Perfect" bitfld.long 0x00 9. " SAF ,Source Address Filter" "Not filtered,Filtered" bitfld.long 0x00 8. " SAIF ,Source Address Inverse Filter" "Not inverted,Inverted" textline " " bitfld.long 0x00 6.--7. " PCF ,Pass Control Frames" "None,,All,Filtered" bitfld.long 0x00 5. " DB ,Disable Broadcast Frames" "No,Yes" bitfld.long 0x00 4. " PM ,Pass All Multicast" "No,Yes" bitfld.long 0x00 3. " DAIF , DA Inverse Filtering" "Not inverted,Inverted" textline " " bitfld.long 0x00 2. " HMC ,Hash Multicast" "Perfect,Hash" bitfld.long 0x00 1. " HUC ,Hash Unicast" "Perfect,Hash" bitfld.long 0x00 0. " PR ,Promiscuous Mode" "Disabled,Enabled" endif group.long 0x0008++0x07 line.long 0x00 "MHTRH,MAC Hash Table Register High" line.long 0x00 "MHTRL,MAC Hash Table Register Low" group.long 0x0010++0x07 line.long 0x00 "GAR,GMII/MII Address Register" bitfld.long 0x00 11.--15. " PA ,Physical Layer Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--10. " GR ,GMII Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " CR ,Application Clock Range (SYS_CLK divider)" "/42,/62,/16,/26,/102,/122,?..." textline " " bitfld.long 0x00 1. " GW ,GMII/MII Write" "Read operation,Write operation" bitfld.long 0x00 0. " GB ,GMII/MII Busy" "Idle,Busy" line.long 0x04 "GDR,GMII/MII Data Register" hexmask.long.word 0x04 0.--15. 1. " GD ,GMII/MII Data Register" if ((d.l(ad:0x40067000)&0x800)==0x800) group.long 0x0018++0x03 line.long 0x00 "FCR,Flow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause Time" bitfld.long 0x00 3. " UP ,Unicast Pause Frame detect" "No detection,Detection" bitfld.long 0x00 2. " RFE ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TFE ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 0. " FCB ,Flow Control Busy" "Idle,Pause initiated" else group.long 0x0018++0x03 line.long 0x00 "FCR,Flow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause Time" bitfld.long 0x00 3. " UP ,Unicast Pause Frame detect" "No detection,Detection" bitfld.long 0x00 2. " RFE ,Receive Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TFE ,Transmit Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 0. " BPA ,Backpressure Activate" "Not active,Active" endif if ((d.l(ad:0x40067000+0x001c)&0x10000)==0x10000) group.long 0x001c++0x03 line.long 0x00 "VTR,VLAN Tag Register" bitfld.long 0x00 16. " ETV ,Enable 12-Bit VLAN Tag Comparison" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " VL ,VLAN Tag Identifier" else group.long 0x001c++0x03 line.long 0x00 "VTR,VLAN Tag Register" bitfld.long 0x00 16. " ETV ,Enable 12-Bit VLAN Tag Comparison" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " VL ,VLAN Tag Identifier" endif group.long 0x0028++0x03 line.long 0x00 "RWFRR,Remote Wake-up Frame Filter Register" hgroup.long 0x002c++0x07 hide.long 0x00 "PMTR,PMT Register" in hide.long 0x04 "LPICSR,LPI Control and Status Register" in group.long 0x0034++0x03 line.long 0x00 "LPITCR,LPI Timers Control Register" hexmask.long.word 0x00 16.--25. 1. " LIT ,LPI LS TIMER" hexmask.long.word 0x00 0.--15. 1. " TWT ,LPI TW TIMER" rgroup.long 0x0038++0x03 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 10. " LPIIS ,LPI Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 9. " TSIS ,Time Stamp Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 7. " COIS ,MMC Receive Checksum Offload Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 6. " TIS ,MMC Transmit Interrupt Status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " RIS ,MMC Receive Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 4. " MIS ,MMC Interrupt Status" "No interrupt,Interrupt" bitfld.long 0x00 3. " PIS ,PMT Interrupt Status" "No interrupt,Interrupt" group.long 0x003c++0x03 line.long 0x00 "IMR,Interrupt Mask Register" bitfld.long 0x00 10. " LPIIM ,LPI Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " TSIM ,Time Stamp Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 3. " PIM ,PMT Interrupt Mask" "Not masked,Masked" tree "Mask Address Registers 0-15" group.long 0x0040++0x07 line.long 0x00 "MAR0H,MAC Address0 Register High" rbitfld.long 0x00 31. " MO ,Must be one" ",One" hexmask.long.word 0x00 0.--15. 1. " A0[47:32] ,MAC Address0[47:32]" line.long 0x04 "MAR0L,MAC Address0 Register Low" group.long 0x48++0x07 line.long 0x00 "MAR1H,MAC Address1 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 1" line.long 0x04 "MAR1L,MAC Address1 Register Low" group.long 0x50++0x07 line.long 0x00 "MAR2H,MAC Address2 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 2" line.long 0x04 "MAR2L,MAC Address2 Register Low" group.long 0x58++0x07 line.long 0x00 "MAR3H,MAC Address3 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 3" line.long 0x04 "MAR3L,MAC Address3 Register Low" group.long 0x60++0x07 line.long 0x00 "MAR4H,MAC Address4 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 4" line.long 0x04 "MAR4L,MAC Address4 Register Low" group.long 0x68++0x07 line.long 0x00 "MAR5H,MAC Address5 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 5" line.long 0x04 "MAR5L,MAC Address5 Register Low" group.long 0x70++0x07 line.long 0x00 "MAR6H,MAC Address6 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 6" line.long 0x04 "MAR6L,MAC Address6 Register Low" group.long 0x78++0x07 line.long 0x00 "MAR7H,MAC Address7 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 7" line.long 0x04 "MAR7L,MAC Address7 Register Low" group.long 0x80++0x07 line.long 0x00 "MAR8H,MAC Address8 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 8" line.long 0x04 "MAR8L,MAC Address8 Register Low" group.long 0x88++0x07 line.long 0x00 "MAR9H,MAC Address9 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 9" line.long 0x04 "MAR9L,MAC Address9 Register Low" group.long 0x90++0x07 line.long 0x00 "MAR10H,MAC Address10 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 10" line.long 0x04 "MAR10L,MAC Address10 Register Low" group.long 0x98++0x07 line.long 0x00 "MAR11H,MAC Address11 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 11" line.long 0x04 "MAR11L,MAC Address11 Register Low" group.long 0xA0++0x07 line.long 0x00 "MAR12H,MAC Address12 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 12" line.long 0x04 "MAR12L,MAC Address12 Register Low" group.long 0xA8++0x07 line.long 0x00 "MAR13H,MAC Address13 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 13" line.long 0x04 "MAR13L,MAC Address13 Register Low" group.long 0xB0++0x07 line.long 0x00 "MAR14H,MAC Address14 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 14" line.long 0x04 "MAR14L,MAC Address14 Register Low" group.long 0xB8++0x07 line.long 0x00 "MAR15H,MAC Address15 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Address" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 15" line.long 0x04 "MAR15L,MAC Address15 Register Low" tree.end textline " " if ((d.l(ad:0x40067000+0x0700)&0x4000)==0x0000) group.long 0x0700++0x03 line.long 0x00 "TSCR,Time Stamp Control Register" bitfld.long 0x00 18. " TSENMF ,Enable MAC address for PTP frame filtering" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSPS ,SelectPTP packets for taking snapshots" "SYNC|Follow_Up|Delay_Req|Delay_Resp,SYNC|Follow_Up|Delay_Req|Delay_Resp|PDelay_Req|PDelay_Resp|PDelay_Resp_Follow_Up,SYNC|Delay_Req,PDelay_Req|PDelay_Resp" textline " " bitfld.long 0x00 15. " TSMRM ,Enable Snapshot for Messages Relevant to Master" "Slave,Master" bitfld.long 0x00 14. " TETSEM ,Enable Time Stamp Snapshot for Event Messages" "Not event,Event" bitfld.long 0x00 13. " TSIP4E ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled" bitfld.long 0x00 12. " TSIP6E ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TETSP ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled" bitfld.long 0x00 10. " TSV2E ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled" bitfld.long 0x00 9. " TSDB ,Time Stamp Digital or Binary rollover control" "Digital,Binary" bitfld.long 0x00 8. " TSEA ,Enable Time Stamp for All Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TARU ,Addend Register Update" "Not updated,Updated" bitfld.long 0x00 4. " TITE ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSU ,Time Stamp Update" "No update,Update" bitfld.long 0x00 2. " TSI ,Time Stamp Initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TFCU ,Time Stamp Fine or Coarse Update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time Stapm Enable" "Disabled,Enabled" elif ((d.l(ad:0x40067000+0x0700)&0x8000)==0x0000) group.long 0x0700++0x03 line.long 0x00 "TSCR,Time Stamp Control Register" bitfld.long 0x00 18. " TSENMF ,Enable MAC address for PTP frame filtering" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSPS ,SelectPTP packets for taking snapshots" "SYNC,SYNC|PDelay_Req|PDelay_Resp,SYNC|Delay_Req,PDelay_Req|PDelay_Resp" textline " " bitfld.long 0x00 15. " TSMRM ,Enable Snapshot for Messages Relevant to Master" "Slave,Master" bitfld.long 0x00 14. " TETSEM ,Enable Time Stamp Snapshot for Event Messages" "Not event,Event" bitfld.long 0x00 13. " TSIP4E ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled" bitfld.long 0x00 12. " TSIP6E ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TETSP ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled" bitfld.long 0x00 10. " TSV2E ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled" bitfld.long 0x00 9. " TSDB ,Time Stamp Digital or Binary rollover control" "Digital,Binary" bitfld.long 0x00 8. " TSEA ,Enable Time Stamp for All Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TARU ,Addend Register Update" "Not updated,Updated" bitfld.long 0x00 4. " TITE ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSU ,Time Stamp Update" "No update,Update" bitfld.long 0x00 2. " TSI ,Time Stamp Initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TFCU ,Time Stamp Fine or Coarse Update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time Stapm Enable" "Disabled,Enabled" else group.long 0x0700++0x03 line.long 0x00 "TSCR,Time Stamp Control Register" bitfld.long 0x00 18. " TSENMF ,Enable MAC address for PTP frame filtering" "Disabled,Enabled" bitfld.long 0x00 16.--17. " TSPS ,SelectPTP packets for taking snapshots" "Delay_Req,Delay_Req|PDelay_Req|PDelay_Resp,SYNC|Delay_Req,PDelay_Req|PDelay_Resp" textline " " bitfld.long 0x00 15. " TSMRM ,Enable Snapshot for Messages Relevant to Master" "Slave,Master" bitfld.long 0x00 14. " TETSEM ,Enable Time Stamp Snapshot for Event Messages" "Not event,Event" bitfld.long 0x00 13. " TSIP4E ,Enable Time Stamp Snapshot for IPv4 frames" "Disabled,Enabled" bitfld.long 0x00 12. " TSIP6E ,Enable Time Stamp Snapshot for IPv6 frames" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " TETSP ,Enable Time Stamp Snapshot for PTP over Ethernet frames" "Disabled,Enabled" bitfld.long 0x00 10. " TSV2E ,Enable PTP packet snooping for version 2 format" "Disabled,Enabled" bitfld.long 0x00 9. " TSDB ,Time Stamp Digital or Binary rollover control" "Digital,Binary" bitfld.long 0x00 8. " TSEA ,Enable Time Stamp for All Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TARU ,Addend Register Update" "Not updated,Updated" bitfld.long 0x00 4. " TITE ,Time Stamp Interrupt Trigger Enable" "Disabled,Enabled" bitfld.long 0x00 3. " TSU ,Time Stamp Update" "No update,Update" bitfld.long 0x00 2. " TSI ,Time Stamp Initialize" "Not initialized,Initialized" textline " " bitfld.long 0x00 1. " TFCU ,Time Stamp Fine or Coarse Update" "Coarse,Fine" bitfld.long 0x00 0. " TSE ,Time Stapm Enable" "Disabled,Enabled" endif group.long 0x0704++0x3 line.long 0x00 "SSIR,Sub-Second Increment Register" hexmask.long.byte 0x00 0.--7. 1. " SSINC ,Sub-Second Increment Value" rgroup.long 0x0708++0x07 line.long 0x00 "STSR,System Time - Seconds Register" line.long 0x04 "STNR,System Time - Nanoseconds Register" hexmask.long 0x04 0.--30. 1. " TSSS ,Time Stamp Sub-Seconds" group.long 0x0710++0x17 line.long 0x00 "STSUR,System Time - Seconds Update Register" line.long 0x04 "STNUR,System Time - Nanoseconds Update Register" bitfld.long 0x04 31. " ADDSUB ,Add or Subtract Time" "Add,Substract" hexmask.long 0x04 0.--30. 1. " TSSS ,Time Stamp Sub-Seconds" line.long 0x08 "TSAR,Time Stamp Addend Register" line.long 0x0c "TTSR,Target Time Seconds Register" line.long 0x10 "TTNR,Target Time Nanoseconds Register" hexmask.long 0x10 0.--30. 1. " TSTR ,Target Time Stamp Nanoseconds Register" line.long 0x14 "STHWSR,System Time - Higher Word Seconds Register" hexmask.long.word 0x14 0.--15. 1. " TSHWR ,System Time - Higher Word Seconds Register" hgroup.long 0x0728++0x03 hide.long 0x00 "TSR,Time Stamp Status Register" in if ((d.l(ad:0x40067000+0x0700)&0x200)==0x00) group.long 0x072c++0x03 line.long 0x00 "PPSCR,PPS Control Register" bitfld.long 0x00 0.--3. " PPSCTRL ,Controls the frequency of the PPS output" ",1Hz,2Hz,4Hz,8Hz,16Hz,32Hz,64Hz,128Hz,256Hz,512Hz,1.024KHz,2.048KHz,4.096KHz,8.192KHz,16.384KHz" else group.long 0x072c++0x03 line.long 0x00 "PPSCR,PPS Control Register" bitfld.long 0x00 0.--3. " PPSCTRL ,Controls the frequency of the PPS output" ",2Hz,4Hz,8Hz,16Hz,32Hz,64Hz,128Hz,256Hz,512Hz,1.024KHz,2.048KHz,4.096KHz,8.192KHz,16.384KHz,32.768KHz" endif hgroup.long 0x0730++0x07 hide.long 0x00 "ATNR,Auxiliary Time Stamp - Nanoseconds Register" hide.long 0x04 "ATSR,Auxiliary Time Stamp - Seconds Register" tree "Mask Address Registers 16-31" group.long 0x800++0x07 line.long 0x00 "MAR16H,MAC Address16 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 16" line.long 0x04 "MAR16L,MAC Address16 Register Low" group.long 0x808++0x07 line.long 0x00 "MAR17H,MAC Address17 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 17" line.long 0x04 "MAR17L,MAC Address17 Register Low" group.long 0x810++0x07 line.long 0x00 "MAR18H,MAC Address18 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 18" line.long 0x04 "MAR18L,MAC Address18 Register Low" group.long 0x818++0x07 line.long 0x00 "MAR19H,MAC Address19 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 19" line.long 0x04 "MAR19L,MAC Address19 Register Low" group.long 0x820++0x07 line.long 0x00 "MAR20H,MAC Address20 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 20" line.long 0x04 "MAR20L,MAC Address20 Register Low" group.long 0x828++0x07 line.long 0x00 "MAR21H,MAC Address21 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 21" line.long 0x04 "MAR21L,MAC Address21 Register Low" group.long 0x830++0x07 line.long 0x00 "MAR22H,MAC Address22 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 22" line.long 0x04 "MAR22L,MAC Address22 Register Low" group.long 0x838++0x07 line.long 0x00 "MAR23H,MAC Address23 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 23" line.long 0x04 "MAR23L,MAC Address23 Register Low" group.long 0x840++0x07 line.long 0x00 "MAR24H,MAC Address24 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 24" line.long 0x04 "MAR24L,MAC Address24 Register Low" group.long 0x848++0x07 line.long 0x00 "MAR25H,MAC Address25 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 25" line.long 0x04 "MAR25L,MAC Address25 Register Low" group.long 0x850++0x07 line.long 0x00 "MAR26H,MAC Address26 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 26" line.long 0x04 "MAR26L,MAC Address26 Register Low" group.long 0x858++0x07 line.long 0x00 "MAR27H,MAC Address27 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 27" line.long 0x04 "MAR27L,MAC Address27 Register Low" group.long 0x860++0x07 line.long 0x00 "MAR28H,MAC Address28 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 28" line.long 0x04 "MAR28L,MAC Address28 Register Low" group.long 0x868++0x07 line.long 0x00 "MAR29H,MAC Address29 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 29" line.long 0x04 "MAR29L,MAC Address29 Register Low" group.long 0x870++0x07 line.long 0x00 "MAR30H,MAC Address30 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 30" line.long 0x04 "MAR30L,MAC Address30 Register Low" group.long 0x878++0x07 line.long 0x00 "MAR31H,MAC Address31 Register High" bitfld.long 0x00 31. " AE ,Address Enable" "Disabled,Enabled" bitfld.long 0x00 30. " SA ,Source Adress" "Destination,Source" bitfld.long 0x00 29. " MBC[5] ,Mask Byte Control MAC Address[47:40]" "Not masked,Masked" bitfld.long 0x00 28. " MBC[4] ,Mask Byte Control MAC Address[39:32]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " MBC[3] ,Mask Byte Control MAC Address[31:24]" "Not masked,Masked" bitfld.long 0x00 26. " MBC[2] ,Mask Byte Control MAC Address[23:16]" "Not masked,Masked" bitfld.long 0x00 25. " MBC[1] ,Mask Byte Control MAC Address[15:8]" "Not masked,Masked" bitfld.long 0x00 24. " MBC[0] ,Mask Byte Control MAC Address[7:0]" "Not masked,Masked" textline " " hexmask.long.word 0x00 0.--15. 1. " A[47:32] ,Upper 16 bits of MAC Address 31" line.long 0x04 "MAR31L,MAC Address31 Register Low" tree.end textline " " tree.end tree.open "DMA Registers" if ((d.l(ad:0x40067000+0x1000)&0x1010000)==0x00) if ((d.l(ad:0x40067000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" textline " " bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif elif ((d.l(ad:0x40067000+0x1000)&0x1010000)==0x10000) if ((d.l(ad:0x40067000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,32,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif elif ((d.l(ad:0x40067000+0x1000)&0x1010000)==0x1000000) if ((d.l(ad:0x40067000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,?..." bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." textline " " bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif else if ((d.l(ad:0x40067000+0x1000)&0x800000)==0x800000) group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "1,2,4,8,16,?..." textline " " bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" else group.long 0x1000++0x03 line.long 0x00 "BMR,Bus Mode Register" bitfld.long 0x00 27. " TXPR ,Transmit Priority" "Normal,High" bitfld.long 0x00 26. " MB ,Mixed Burst" "No,Yes" bitfld.long 0x00 24. " 8xPBL ,8xPBL Mode" "Not multiplied,Multiplied" bitfld.long 0x00 23. " USP ,Use Separate PBL" "No,Yes" textline " " bitfld.long 0x00 17.--22. " RPBL ,RxDMA PBL" "1,2,4,8,16,32,?..." bitfld.long 0x00 16. " FB ,Fixed Burst" "SINGLE|INCR,SINGLE|INCR4|INCR8|INCR16" bitfld.long 0x00 14.--15. " PR ,Rx:Tx priority ratio" "1:1,2:1,3:1,4:1" bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "16 bytes,32 bytes" textline " " bitfld.long 0x00 3.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--2. " DA ,Arbitration scheme" "Weighted Round-robin,Fixed priority,?..." bitfld.long 0x00 0. " SWR ,Software Reset" "No reset,Reset" endif endif group.long 0x1004++0x13 line.long 0x00 "TPDR,Transmit Poll Demand Register" line.long 0x04 "RPDR,Receive Poll Demand Register" line.long 0x08 "RDLAR,Receive Descriptor List Address Register" hexmask.long 0x08 2.--31. 1. " SRL ,Start of Receive List" line.long 0x0c "TDLAR,Receive Descriptor List Address Register" hexmask.long 0x0c 2.--31. 1. " STL ,Start of Transmit List" if (((d.l(ad:0x40067000+0x1014))&0x2000)==0x2000) group.long 0x1014++0x03 line.long 0x00 "SR,Status Register" rbitfld.long 0x00 30. " GLPII ,GMAC LPI Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 29. " TTI ,Time-Stamp Trigger Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " GPI ,GMAC PMT Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 27. " GMI ,GMAC MMC Interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x00 25. " EB[2] ,Error Bits" "Data buffer,Descriptor" rbitfld.long 0x00 24. " EB[1] ,Error Bits" "Write,Read" rbitfld.long 0x00 23. " EB[0] ,Error Bits" "Receive DMA,Transmit DMA" rbitfld.long 0x00 20.--22. " TS ,Transmit Process State" "Stopped,Fetching Transmit Transfer Descriptor,Waiting for status,Reading,Time-Stamp write,,Suspended,Closing Transmit Descriptor" textline " " rbitfld.long 0x00 17.--19. " RS ,Receive Process State" "Stopped,Fetching Receive Transfer Descriptor,,Waiting for receive packet,Suspended,Closing Receive Descriptor,Time-Stamp write,Transferring" eventfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "Low,High" eventfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "Low,High" eventfld.long 0x00 14. " ERI ,Early Receive Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " RWT ,Receive Watchdog Timeout" "No timeout,Timeout" eventfld.long 0x00 8. " RPS ,Receive process Stopped" "Running,Stopped" textline " " eventfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 6. " RI ,Receive Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " UNF ,Transmit underflow" "Not occurred,Occurred" eventfld.long 0x00 4. " OVF ,Receive Overflow" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "No timeout,Timeout" eventfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 1. " TPS ,Transmit Process Stopped" "Running,Stopped" eventfld.long 0x00 0. " TI ,Transmit Interrupt" "No interrupt,Interrupt" else group.long 0x1014++0x03 line.long 0x00 "SR,Status Register" rbitfld.long 0x00 30. " GLPII ,GMAC LPI Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 29. " TTI ,Time-Stamp Trigger Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 28. " GPI ,GMAC PMT Interrupt" "No interrupt,Interrupt" rbitfld.long 0x00 27. " GMI ,GMAC MMC Interrupt" "No interrupt,Interrupt" textline " " rbitfld.long 0x00 20.--22. " TS ,Transmit Process State" "Stopped,Fetching Transmit Transfer Descriptor,Waiting for status,Reading,Time-Stamp write,,Suspended,Closing Transmit Descriptor" rbitfld.long 0x00 17.--19. " RS ,Receive Process State" "Stopped,Fetching Receive Transfer Descriptor,,Waiting for receive packet,Suspended,Closing Receive Descriptor,Time-Stamp write,Transferring" eventfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "Low,High" eventfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "Low,High" textline " " eventfld.long 0x00 14. " ERI ,Early Receive Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " RWT ,Receive Watchdog Timeout" "No timeout,Timeout" textline " " eventfld.long 0x00 8. " RPS ,Receive process Stopped" "Running,Stopped" eventfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 6. " RI ,Receive Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " UNF ,Transmit underflow" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " OVF ,Receive Overflow" "Not occurred,Occurred" eventfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "No timeout,Timeout" eventfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "Available,Unavailabe" eventfld.long 0x00 1. " TPS ,Transmit Process Stopped" "Running,Stopped" textline " " eventfld.long 0x00 0. " TI ,Transmit Interrupt" "No interrupt,Interrupt" endif if (((d.l(ad:0x40067000+0x1018))&0x200000)==0x200000) if (((d.l(ad:0x40067000+0x1018))&0x2000000)==0x2000000) group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" textline " " bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "64,32,96,128" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" else group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" textline " " bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" endif else if (((d.l(ad:0x40067000+0x1018))&0x2000000)==0x2000000) group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control [bytes]" "64,128,192,256,40,32,24,16" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" textline " " bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "64,32,96,128" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" else group.long 0x1018++0x07 line.long 0x00 "OMR,Operation Mode Register" bitfld.long 0x00 26.--27. " DT ,Disable Dropping of TCP/IP Checksum Error Frames" "0,1,2,3" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "Cut-Through,MLT-receive FIFO write" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "No,Yes" bitfld.long 0x00 21. " TSF ,Transmit Store Forward" "No,Yes" textline " " eventfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "No effect,Flushed" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control [bytes]" "64,128,192,256,40,32,24,16" bitfld.long 0x00 13. " ST ,Start/Stop Transmission Command" "Stopped,Started" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "Drop,Forward" textline " " bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "Drop,Forward" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "First frame,Second frame" bitfld.long 0x00 1. " SR ,Start/Stop Receive" "Stopped,Started" endif endif group.long 0x101C++0x07 line.long 0x00 "IER,Interrupt Enable Register" bitfld.long 0x00 16. " NIE ,Normal Interrupt Summary Enable" "Disabled,Enabled" bitfld.long 0x00 15. " AIE ,Abnormal Interrupt Summary Enable" "Disabled,Enabled" bitfld.long 0x00 14. " ERE ,Early Receive Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x00 13. " FBE ,Fatal Bus Error Enable" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " ETE ,Early Transmit Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x00 9. " RWE ,Receive Watchdog Timeout Enable" "No timeout,Timeout" bitfld.long 0x00 8. " RSE ,Receive process Stopped Enable" "Running,Stopped" bitfld.long 0x00 7. " RUE ,Receive Buffer Unavailable Enable" "Available,Unavailabe" textline " " bitfld.long 0x00 6. " RIE ,Receive Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x00 5. " UNE ,Transmit underflow Enable" "Not occurred,Occurred" bitfld.long 0x00 4. " OVE ,Receive Overflow Enable" "Not occurred,Occurred" bitfld.long 0x00 3. " TJE ,Transmit Jabber Timeout" "No timeout,Timeout" textline " " bitfld.long 0x00 2. " TUE ,Transmit Buffer Unavailable Enable" "Available,Unavailabe" bitfld.long 0x00 1. " TSE ,Transmit Process Stopped Enable" "Running,Stopped" eventfld.long 0x00 0. " TIE ,Transmit Interrupt Enable" "No interrupt,Interrupt" hgroup.long 0x1020++0x03 hide.long 0x00 "MFBOCR,Missed Frame and Buffer Overflow Counter Register" in group.long 0x1024++0x03 line.long 0x00 "RIWTR,Receive Interrupt Watchdog Timer Register" hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI Watchdog Timer count" rgroup.long 0x102c++0x03 line.long 0x00 "AHBSR,AHB Status Register" bitfld.long 0x00 0. " AHBS ,AHB Status" "Idle,Non-idle" rgroup.long 0x1048++0x0f line.long 0x00 "CHTDR,Current Host Transmit Descriptor Register" line.long 0x04 "CHRDR,Current Host Receive Descriptor Register" line.long 0x08 "CHTBAR,Current Host Transmit Buffer Address Register" line.long 0x0c "CHRBAR,Current Host Receive Buffer Address Register" tree.end width 22. tree "MMC Registers" group.long 0x0100++0x03 line.long 0x00 "MMC_CNT,MMC Control Register" bitfld.long 0x00 5. " FHP ,Full-Half preset" "Almost-half-value,Almost-full-value" bitfld.long 0x00 4. " CP , Counters Preset" "No preset,Preset" bitfld.long 0x00 3. " MCF ,MMC Counter Freeze" "Not frozen,Frozen" textline " " bitfld.long 0x00 2. " ROR ,Reset on read" "No reset,Reset" bitfld.long 0x00 1. " CSR ,Counter Stop Rollover" "Rollover,No rollover" bitfld.long 0x00 0. " CR ,Counter reset" "No reset,Reset" hgroup.long 0x0104++0x07 hide.long 0x00 "MMC_INTR_RX,MMC Receive Interrupt Register" in hide.long 0x04 "MMC_INTR_TX,MMC Transmit Interrupt Register" in group.long 0x010c++0x03 line.long 0x00 "MMC_INTR_MASK_RX,MMC Receive Interrupt Mask Interrupt Register" bitfld.long 0x00 23. " RXWTDEIM ,Rxwatchdogerror Counter Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 22. " RXVLFIM ,Rxvlanframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 21. " RXFOFIM ,Rxfifooverflow_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 20. " RXPFIM ,Rxpauseframes Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RXORTIM ,Rxoutofrangetype Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 18. " RXLCIM ,Rxlengtherror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 17. " RXUCFIM ,Rxunicastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 16. " RX1024_MAXIM ,Rx1024tomaxoctets_g Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " RX512_1024IM ,Rx512to1023octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 14. " RX256_511IM ,Rx256to511octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 13. " RX128_256IM ,Rx128to255maxoctects_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 12. " RX65_127IM ,Rx65to127maxoctets_gb Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RX64IM ,Rxto64octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 10. " RXOSIM ,Rxoversize_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " RXUSIM ,Rxundersize_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 8. " RXJERIM ,Rxjabbererror Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RXRUNTERIM ,Rxrunterror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 6. " RXALTERIM ,Rxallignmenterror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 5. " RXCRCERIM ,Rxcrcerror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 4. " RXMCFIM ,Rxmulticastframes_g Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " RXBCFIM ,Rxbroadcastframes_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 2. " RXOCGIM ,Rxoctetcounter_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " RXOCGBIM ,Rxoctetcounter_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 0. " RXFCIM ,Rxframecount_gb Counter Interrupt Mask" "Not masked,Masked" group.long 0x0110++0x03 line.long 0x00 "MMC_INTR_MASK_TX,MMC Transmit Interrupt Mask Register" bitfld.long 0x00 24. " TXVLFIM ,Txvlanframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 23. " TXPFIM ,Txpauseframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 22. " TXOCIM ,Txoexcessdef Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 21. " TXFCIM ,Txframecount Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 20. " TXOCIM ,Txoctetcount Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 19. " TXCERIM ,Txcarriererror Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 18. " TXLXSIM ,Txlexesscol Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 17. " YXLCIM ,Txlatecol Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 16. " TXDEFIM ,Txdeffer Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 15. " TXMCIM ,Txmulticol_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 14. " TXSCIM ,Txsinglecol_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 13. " TXUFERIM ,Txunderflowerror Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 12. " TXBCFGBIM ,Txbroadcastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 11. " TXMCFGBIM ,Txmulticastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 10. " TXUCFIM ,Txunicastframes_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " TX1024_MAXIM ,Tx1024tomaxoctets_g Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " TX512_1023IM ,Tx512to1023octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 7. " TX256_511IM ,Tx256to511octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 6. " TX128_256IM ,Tx128to255maxoctects_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 5. " TX65_127IM ,Tx65to127maxoctets_gb Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " TX64IM ,Txto64octets_gb Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 3. " TXMCFGIM ,Txmalticastframes_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 2. " TXBCGIM ,Txbroadcastframes_g Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " TXFCGBIM ,Txframecount_gb Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " TXOCGBIM ,Txoctetcount_gb Counter Interrupt Mask" "Not masked,Masked" group.long 0x0200++0x03 line.long 0x00 "MMC_IPC_INTR_MASK_RX,MMC Receive Checksum Offload Interrupt Mask Register" bitfld.long 0x00 29. " RXICMPEOIM ,Rxicmp_err_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 28. " RXICMPGDOIM ,Rxicmp_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 27. " RXTCPEOIM ,Rxtcp_err_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 26. " RXTCPGDOIM ,Rxtcp_gd_octets Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 25. " RXUDPEOIM ,Rxudp_err_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 24. " RXUDPGDOIM ,Rxudp_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 23. " RXIP6NPOIM ,Rxipv6_nopay_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 22. " RXIP6HDREOIM ,Rxipv6_hdrerr_octets Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 21. " RXIP6GDOIM ,Rxipv6_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 20. " RXIP4UDSBOIE ,Rxipv4_udsbl_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 19. " RXIP4FOIM ,Rxipv4_frag_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 18. " RXIP4NPOIM ,Rxipv4_nopay_octets Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 17. " RXIP4HDREOIM ,Rxipv4_hdrerr_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 16. " RXIP4GDOIM ,Rxipv4_gd_octets Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 13. " RXICMPEFIM ,Rxicmp_err_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 12. " RXICMPGDFIM ,Rxicmp_gd_frms Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RXTCPEFIM ,Rxtcp_err_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 10. " RXTCPGDFIM ,Rxtcp_gd_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 9. " RXUDPEFIM ,Rxudp_err_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 8. " RXUDPGDFIM ,Rxudp_gd_frms Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RXIP6NPFIM ,Rxipv6_nopay_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 6. " RXIP6HDREFIM ,Rxipv6_hdrerr_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 5. " RXIP6GDFIM ,Rxipv6_gd_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 4. " RXIP4UDSBFIM ,Rxipv4_udsbl_frms Counter Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " RXIPV4FFIM ,Rxipv4_frag_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 2. " RXIP4NPFIM ,Rxipv4_nopay_frms Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 1. " RXIP4HDREFIM ,Rxipv4_hdrerr_frms counter Counter Interrupt Mask" "Not masked,Masked" bitfld.long 0x00 0. " RXIP4GDFIM ,Rxipv4_gd_frms Counter Interrupt Mask" "Not masked,Masked" hgroup.long 0x208++0x03 hide.long 0x00 "MMC_IPC_INTR_RX,MMC Receive Checksum Offload Interrupt Register" in tree "MMC Counters" group.long 0x114++0x63 line.long 0x00 "TXOCTETCOUNT_GB,Number of bytes transmitted" line.long 0x04 "TXFRAMECOUNT_GB,Number of good and bad frames transmitted" line.long 0x08 "TXBROADCASTFRAMES_G,Number of good broadcast frames transmitted" line.long 0x0c "TXMULTICASTFRAMES_G,Number of good multicast frames transmitted." line.long 0x10 "TX64OCTETS_GB,Number of good and bad frames transmitted with length of 64 bytes" line.long 0x14 "TX65TO127OCTETS_GB,Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes" line.long 0x18 "TX128TO255OCTETS_GB,Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes," line.long 0x1c "TX256TO511OCTETS_GB,Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes" line.long 0x20 "TX512TO1023OCTETS_GB,Number of good and bad frames transmitted with length between 512 and 1023 (inclusive) bytes" line.long 0x24 "TX1024TOMAXOCTETS_GB,Number of good and bad frames transmitted with length between 1024 and Maxsize (inclusive) bytes," line.long 0x28 "TXUNICASTFRAMES_GB,Number of good and bad unicast frames transmittedr" line.long 0x2c "TXMULTICASTFRAMES_GB,Number of good and bad multicast frames transmitted" line.long 0x30 "TXBROADCASTFRAMES_GB,Number of good and bad broadcast frames transmitted." line.long 0x34 "TXUNDERFLOWERROR,Number of frames aborted due to frame underflow error" line.long 0x38 "TXSINGLECOL_G,Number of successfully transmitted frames after a single collision in Half-duplex mode" line.long 0x3c "TXMULTICOL_G,Number of successfully transmitted frames after more than a single collision in Half-duplex mode" line.long 0x40 "TXDEFERRED,Number of successfully transmitted frames after a deferral in Half-duplex mode" line.long 0x44 "TXLATECOL,Number of frames aborted due to late collision error." line.long 0x48 "TXEXESSCOL,Number of frames aborted due to excessive (16) collision errors" line.long 0x4c "TXCARRIERERRROR,Number of frames aborted due to carrier sense error" line.long 0x50 "TXOCTETCOUNT_G,Number of bytes transmitted, exclusive of preamble, in good frames only" line.long 0x54 "TXFRAMECOUNT_G,Number of good frames transmitted" line.long 0x58 "TXEXECESSDEF,Number of frames aborted due to excessive deferral error" line.long 0x5c "TXPAUSEFRAMES,Number of good PAUSE frames transmitted" line.long 0x60 "TXVLANFRAMES,Number of good VLAN frames transmitted" group.long 0x180++0x5f line.long 0x00 "RXFRAMECOUNT_GB,Number of good and bad frames received" line.long 0x04 "RXOCTETCOUNT_GB,Number of bytes received" line.long 0x08 "RXOCTETCOUNT_G,Number of bytes received, exclusive of preamble, only in good frames" line.long 0x0c "RXBROADCASTFRAMES_G,Number of good broadcast frames received" line.long 0x10 "RXMULTICASTFRAMES_G,Number of good multicast frames received" line.long 0x14 "RXCRCERROR,Number of frames received with CRC error" line.long 0x18 "RXALLIGNMENTERROR,Number of frames received with alignment (dribble) error" line.long 0x1c "RXRUNTERROR,Number of frames received with runt error" line.long 0x20 "RXJABBERERROR,Number of frames received with length greater than 1518 bytes with CRC error" line.long 0x24 "RXUNDERSIZE_G,Number of frames received with length less than 64 bytes, without any errors" line.long 0x28 "RXOVERSIZE_G,Number of frames received with length greater than the maxsize without error" line.long 0x2c "RX64OCTETS_GB,Number of good and bad frames received with length 64 bytes, exclusive of preamble" line.long 0x30 "RX65TO127OCTETS_GB,Number of good and bad frames received with length 64 bytes, exclusive of preamble" line.long 0x34 "RX128TO255OCTETS_GB,Number of good and bad frames received with length between 128 and 255 (inclusive) bytes" line.long 0x38 "RX256TO511OCTETS_GB,Number of good and bad frames received with length between 256 and 511 (inclusive) bytes" line.long 0x3c "RX512TO1023OCTETS_GB,Number of good and bad frames received with length between 512 and 1023 (inclusive) bytes" line.long 0x40 "RX1024TOMAXOCTETS_GB,Number of good and bad frames received with length between 1024 and maxsize (inclusive) bytes" line.long 0x44 "RXUNICASTFRAMES_G,Number of good unicast frames received" line.long 0x48 "RXLENGTHERROR,Number of frames received with length error" line.long 0x4c "RXOUTOFRANGETYPE,Number of frames received with length/type field not equal to the valid frame size" line.long 0x50 "RXPAUSEFRAMES,Number of good and valid PAUSE frames received" line.long 0x54 "RXFIFOOVERFLOW,Number of missed received frames due to FIFO overflow" line.long 0x58 "RXVLANFRAMES_GB,Number of good and bad VLAN frames received" line.long 0x5c "RXWATCHDOGERROR,Number of frames received with error due to watchdog timeout error" group.long 0x210++0x37 line.long 0x00 "RXIPV4_GD_FRMS,Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload" line.long 0x04 "RXIPV4_HDRERR_FRMS,Number of IPv4 datagrams received with header errors" line.long 0x08 "RXIPV4_NOPAY_FRMS,Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine" line.long 0x0c "RXIPV4_FRAG_FRMS,Number of good IPv4 datagrams with fragmentation" line.long 0x10 "RXIPV4_UDSBL_FRMS,Number of good IPv4 datagrams received that had a UDP payload with checksum disabled" line.long 0x14 "RXIPV6_GD_FRMS,Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads" line.long 0x18 "RXIPV6_HDRERR_FRMS,Number of IPv6 datagrams received with header errors" line.long 0x1c "RXIPV6_NOPAY_FRMS,Number of IPv6 datagram frames received without a TCP, UDP, or ICMP payload" line.long 0x20 "RXUDP_GD_FRMS,Number of good IP datagrams with a good UDP payload" line.long 0x24 "RXUDP_ERR_FRMS,Number of good IP datagrams whose UDP payload has a checksum error" line.long 0x28 "RXTCP_GD_FRMS,Number of good IP datagrams with a good TCP payload" line.long 0x2c "RXTCP_ERR_FRMS,Number of good IP datagrams whose TCP payload has a checksum error" line.long 0x30 "RXICMP_GD_FRMS,Number of good IP datagrams with a good ICMP payload" line.long 0x34 "RXICMP_ERR_FRMS,Number of good IP datagrams whose ICMP payload has a checksum error" group.long 0x250++0x37 line.long 0x00 "RXIPV4_GD_OCTETS,Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data" line.long 0x04 "RXIPV4_HDRERR_OCTETS,Number of bytes received in IPv4 datagrams with header errors" line.long 0x08 "RXIPV4_NOPAY_OCTETS,Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload" line.long 0x0c "RXIPV4_FRAG_OCTETS,Number of bytes received in fragmented IPv4 datagrams" line.long 0x10 "RXIPV4_UDSBL_OCTETS,Number of bytes received in a UDP segment that had the UDP checksum disabled" line.long 0x14 "RXIPV6_GD_OCTETS,Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data" line.long 0x18 "RXIPV6_HDRERR_OCTETS,Number of bytes received in IPv6 datagrams with header errors" line.long 0x1c "RXIPV6_NOPAY_OCTETS,Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload" line.long 0x20 "RXUDP_GD_OCTETS,Number of bytes received in a good UDP segment" line.long 0x24 "RXUDP_ERR_OCTETS,Number of bytes received in a UDP segment that had checksum errors" line.long 0x28 "RXTCP_GD_OCTETS,Number of bytes received in a good TCP segment" line.long 0x2c "RXTCP_ERR_OCTETS,Number of bytes received in a TCP segment with checksum errors" line.long 0x30 "RXICMP_GD_OCTETS,Number of bytes received in a good ICMP segment" line.long 0x34 "RXICMP_ERR_OCTETS,Number of bytes received in an ICMP segment with checksum errors" tree.end tree.end width 0xb tree.end endif tree.end endif sif (cpuis("MB9BF4*")||cpuis("MB9BF5*")||cpuis("MB9BF6*")||cpuis("MB9BFD16S")||cpuis("MB9BFD16T")||cpuis("MB9BFD17S")||cpuis("MB9BFD17T")||cpuis("MB9BFD18S")||cpuis("MB9BFD18T")||cpuis("MB9AF421K")||cpuis("MB9AF421L")) tree.open "CAN" tree "Prescaler" base ad:0x40037000 width 8. group.byte 0x0++0x0 line.byte 0x0 "CANPRE,CAN Prescaler Register" bitfld.byte 0x00 0.--3. " CANPRE ,CAN prescaler setting bits (at input of 80/60 MHz prescaler clock)" "Not divided,1/2,1/4,1/4,1/8,1/8,1/8,1/8,2/3,1/3,1/6,1/12,1/5,1/5,1/10,1/10" width 12. tree.end sif (!cpuis("MB9BF524K")&&!cpuis("MB9BF524L")&&!cpuis("MB9BF524M")&&!cpuis("MB9BF522K")&&!cpuis("MB9BF522L")&&!cpuis("MB9BF522M")&&!cpuis("MB9BF521K")&&!cpuis("MB9BF521L")&&!cpuis("MB9BF521M")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")) tree "Channel 0" base ad:0x40062000 width 9. tree "Total Control Registers" if (((d.w(ad:0x40062000))&0x1)==0x1) group.word 0x0++0x1 line.word 0x0 "CTRLR,CAN Control Register" bitfld.word 0x0 7. " TEST ,Test Mode Enable" "Disabled,Enabled" bitfld.word 0x0 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.word 0x0 5. " DAR ,Disable Automatic Retransmission" "No,Yes" textline " " bitfld.word 0x0 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 1. " IE ,Module Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 0. " INIT ,Initialization" "Normal,Initialization" else group.word 0x0++0x1 line.word 0x0 "CTRLR,CAN Control Register" bitfld.word 0x0 7. " TEST ,Test Mode Enable" "Disabled,?..." bitfld.word 0x0 6. " CCE ,Configuration Change Enable" "No effect,No effect" bitfld.word 0x0 5. " DAR ,Disable Automatic Retransmission" "No,Yes" textline " " bitfld.word 0x0 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 1. " IE ,Module Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 0. " INIT ,Initialization" "Normal,Initialization" endif group.word 0x2++0x1 line.word 0x0 "STATR,Status Register" rbitfld.word 0x00 7. " BOFF ,CAN bus busoff state" "Disabled,Enabled" rbitfld.word 0x00 6. " EWARN ,Send/receive counter" "<96,>=96" rbitfld.word 0x00 5. " EPASS ,Error passive state" "Below 128,128-255" textline " " bitfld.word 0x00 4. " RXOK ,Successful message reception" "Not successful,Successful" bitfld.word 0x00 3. " TXOK ,Successful message transmission" "Not successful,Successful" bitfld.word 0x00 0.--2. " LEC ,Last error code" "Normal,Stuff error,Form error,Ack error,Bit 1 error,Bit 0 error,CRC error,Undetected" rgroup.word 0x4++0x1 line.word 0x0 "ERRCNT,Error Counter" bitfld.word 0x0 15. " RP ,Receive Error Passive" "Below level,Reached level" hexmask.word.byte 0x0 8.--14. 0x1 " REC[6:0] ,Receive Error Counter" hexmask.word.byte 0x0 0.--7. 0x1 " TEC[7:0] ,Transmit Error Counter" group.word 0x6++0x1 line.word 0x0 "BTR,Bit Timing Register" bitfld.word 0x0 12.--14. " TSEG2 ,The time segment after sample point" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--11. " TSEG1 ,The time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0 6.--7. " SJW ,(Re)Synchronisation Jump Width" "0,1,2,3" textline " " bitfld.word 0x0 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hgroup.word 0x8++0x1 hide.word 0x0 "INTR,Interrupt Register (indicates message interrupt code and status interrupt code)" in group.word 0xA++0x3 line.word 0x0 "TESTR,Test Register" rbitfld.word 0x0 7. " RX ,Monitors the actual value of the CAN_RX Pin" "Dominant,Recessive" bitfld.word 0x0 5.--6. " TX[1:0] ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.word 0x0 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" textline " " bitfld.word 0x0 3. " SILENT ,Silent Mode" "Disabled,Enabled" bitfld.word 0x0 2. " BASIC ,Basic Mode" "Disabled,Enabled" line.word 0x2 "BRPER,BRP Extension Register" bitfld.word 0x2 0.--3. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Message Interface Registers" tree "IF1 Registers" group.word 0x10++0x1 line.word 0x0 "IF1CREQ,IF1 Command Request Register" bitfld.word 0x0 15. " BUSY ,Busy Flag" "Not busy,Busy" hexmask.word.byte 0x0 0.--7. 0x1 " MSGN ,Message Number" if ((d.w(ad:0x40062000+0xA)&0x04)==0x04) hgroup.word (0x10+0x2)++0x1 hide.word 0x0 "IF1CMSK,IF1 Command Mask Register" elif (((d.w(ad:0x40062000+0x10+0x2))&0x80)==0x80) group.word (0x10+0x2)++0x1 line.word 0x0 "IF1CMSK,IF1 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 2. " TXREQ ,Message transmission request bit" "Not requested,Requested" bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" textline " " bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" else group.word (0x10+0x2)++0x1 line.word 0x0 "IF1CMSK,IF1 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 3. " CIP ,Clear Interrupt Pending Bit (INTPND)" "No effect,Clear" bitfld.word 0x0 2. " TXREQ ,Data update bit" "Not cleared,Cleared" textline " " bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" endif group.word (0x10+0x4)++0x7 line.word 0x0 "IF1MSK1,IF1 Mask Registers 1" bitfld.word 0x0 15. " MSK_[15] ,Identifier Mask bit 15" "Not masked,Masked" bitfld.word 0x0 14. " [14] ,Identifier Mask bit 14" "Not masked,Masked" bitfld.word 0x0 13. " [13] ,Identifier Mask bit 13" "Not masked,Masked" bitfld.word 0x0 12. " [12] ,Identifier Mask bit 12" "Not masked,Masked" bitfld.word 0x0 11. " [11] ,Identifier Mask bit 11" "Not masked,Masked" bitfld.word 0x0 10. " [10] ,Identifier Mask bit 10" "Not masked,Masked" textline " " bitfld.word 0x0 9. " [9] ,Identifier Mask bit 9" "Not masked,Masked" bitfld.word 0x0 8. " [8] ,Identifier Mask bit 8" "Not masked,Masked" bitfld.word 0x0 7. " [7] ,Identifier Mask bit 7" "Not masked,Masked" bitfld.word 0x0 6. " [6] ,Identifier Mask bit 6" "Not masked,Masked" bitfld.word 0x0 5. " [5] ,Identifier Mask bit 5" "Not masked,Masked" bitfld.word 0x0 4. " [4] ,Identifier Mask bit 4" "Not masked,Masked" textline " " bitfld.word 0x0 3. " [3] ,Identifier Mask bit 3" "Not masked,Masked" bitfld.word 0x0 2. " [2] ,Identifier Mask bit 2" "Not masked,Masked" bitfld.word 0x0 1. " [1] ,Identifier Mask bit 1" "Not masked,Masked" bitfld.word 0x0 0. " [0] ,Identifier Mask bit 0" "Not masked,Masked" line.word 0x2 "IF1MSK2,IF1 Mask Registers 2 (Mask bits of Message Object)" bitfld.word 0x2 15. " MXTD ,Mask Extended Identifier" "No compare,Compare" bitfld.word 0x2 14. " MDIR ,Mask Message Direction (effect of DIR in filtering)" "Masked,Not masked" textline " " bitfld.word 0x2 12. " MSK_[28] ,Identifier Mask bit 27" "Not masked,Masked" bitfld.word 0x2 11. " [27] ,Identifier Mask bit 26" "Not masked,Masked" bitfld.word 0x2 10. " [26] ,Identifier Mask bit 25" "Not masked,Masked" bitfld.word 0x2 9. " [25] ,Identifier Mask bit 24" "Not masked,Masked" bitfld.word 0x2 8. " [24] ,Identifier Mask bit 23" "Not masked,Masked" bitfld.word 0x2 7. " [23] ,Identifier Mask bit 22" "Not masked,Masked" textline " " bitfld.word 0x2 6. " [22] ,Identifier Mask bit 21" "Not masked,Masked" bitfld.word 0x2 5. " [21] ,Identifier Mask bit 20" "Not masked,Masked" bitfld.word 0x2 4. " [20] ,Identifier Mask bit 19" "Not masked,Masked" bitfld.word 0x2 3. " [19] ,Identifier Mask bit 18" "Not masked,Masked" bitfld.word 0x2 2. " [18] ,Identifier Mask bit 17" "Not masked,Masked" bitfld.word 0x2 1. " [17] ,Identifier Mask bit 16" "Not masked,Masked" textline " " bitfld.word 0x2 0. " [16] ,Identifier Mask bit " "Not masked,Masked" line.word 0x4 "IF1ARB1,IF1 Arbitration Register 1" line.word 0x6 "IF1ARB2,IF1 Arbitration Registers 2" bitfld.word 0x6 15. " MSGVAL ,Message Valid (Message Object is:)" "Invalid,Valid" bitfld.word 0x6 14. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.word 0x6 13. " DIR ,Message Direction" "Receive,Transmit" textline " " hexmask.word 0x6 0.--12. 1. " ID[28-16] ,Message Identifier bits 28...16" if (((d.w(ad:0x40062000+0x10+0xA))&0x2000)==0x2000) if (((d.b(ad:0x40062000+0x10+0x2))&0x04)==0x04) group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif else if (((d.b(ad:0x40062000+0x10+0x2))&0x04)==0x04) group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif endif group.word (0x10+0x10)++0x7 line.word 0x0 "IF1DTA1,IF1 Data A Register 1" hexmask.word.byte 0x0 8.--15. 1. " DATA0 ,IF1 Data A Register 1 Data(0)" hexmask.word.byte 0x0 0.--7. 1. " DATA1 ,IF1 Data A Register 1 Data(1)" line.word 0x2 "IF1DTA2,IF1 Data A Register 2" hexmask.word.byte 0x2 8.--15. 1. " DATA2 ,IF1 Data A Register 2 Data(2)" hexmask.word.byte 0x2 0.--7. 1. " DATA3 ,IF1 Data A Register 2 Data(3)" line.word 0x4 "IF1DTB1,IF1 Data B Register 1" hexmask.word.byte 0x4 8.--15. 1. " DATA4 ,IF1 Data B Register 1 Data(4)" hexmask.word.byte 0x4 0.--7. 1. " DATA5 ,IF1 Data B Register 1 Data(5)" line.word 0x6 "IF1DTB2,IF1 Data B Register 2" hexmask.word.byte 0x6 8.--15. 1. " DATA6 ,IF1 Data B Register 2 Data(6)" hexmask.word.byte 0x6 0.--7. 1. " DATA7 ,IF1 Data B Register 2 Data(7)" group.word (0x10+0x20)++0x7 line.word 0x0 "IF1DTA2,IF1 Data A Register 2" hexmask.word.byte 0x0 8.--15. 1. " DATA8 ,IF1 Data A Register 1 Data(8)" hexmask.word.byte 0x0 0.--7. 1. " DATA9 ,IF1 Data A Register 1 Data(9)" line.word 0x2 "IF1DTA1,IF1 Data A Register 1" hexmask.word.byte 0x2 8.--15. 1. " DATA10 ,IF1 Data A Register 2 Data(10)" hexmask.word.byte 0x2 0.--7. 1. " DATA11 ,IF1 Data A Register 2 Data(11)" line.word 0x4 "IF1DTB2,IF1 Data B Register 2" hexmask.word.byte 0x4 8.--15. 1. " DATA12 ,IF1 Data B Register 1 Data(12)" hexmask.word.byte 0x4 0.--7. 1. " DATA13 ,IF1 Data B Register 1 Data(13)" line.word 0x6 "IF1DTB1,IF1 Data B Register 1" hexmask.word.byte 0x6 8.--15. 1. " DATA14 ,IF1 Data B Register 2 Data(14)" hexmask.word.byte 0x6 0.--7. 1. " DATA15 ,IF1 Data B Register 2 Data(15)" tree.end tree "IF2 Registers" group.word 0x40++0x1 line.word 0x0 "IF2CREQ,IF2 Command Request Register" bitfld.word 0x0 15. " BUSY ,Busy Flag" "Not busy,Busy" hexmask.word.byte 0x0 0.--7. 0x1 " MSGN ,Message Number" if ((d.w(ad:0x40062000+0xA)&0x04)==0x04) hgroup.word (0x40+0x2)++0x1 hide.word 0x0 "IF2CMSK,IF2 Command Mask Register" elif (((d.w(ad:0x40062000+0x40+0x2))&0x80)==0x80) group.word (0x40+0x2)++0x1 line.word 0x0 "IF2CMSK,IF2 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 2. " TXREQ ,Message transmission request bit" "Not requested,Requested" bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" textline " " bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" else group.word (0x40+0x2)++0x1 line.word 0x0 "IF2CMSK,IF2 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 3. " CIP ,Clear Interrupt Pending Bit (INTPND)" "No effect,Clear" bitfld.word 0x0 2. " TXREQ ,Data update bit" "Not cleared,Cleared" textline " " bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" endif group.word (0x40+0x4)++0x7 line.word 0x0 "IF2MSK1,IF2 Mask Registers 1" bitfld.word 0x0 15. " MSK_[15] ,Identifier Mask bit 15" "Not masked,Masked" bitfld.word 0x0 14. " [14] ,Identifier Mask bit 14" "Not masked,Masked" bitfld.word 0x0 13. " [13] ,Identifier Mask bit 13" "Not masked,Masked" bitfld.word 0x0 12. " [12] ,Identifier Mask bit 12" "Not masked,Masked" bitfld.word 0x0 11. " [11] ,Identifier Mask bit 11" "Not masked,Masked" bitfld.word 0x0 10. " [10] ,Identifier Mask bit 10" "Not masked,Masked" textline " " bitfld.word 0x0 9. " [9] ,Identifier Mask bit 9" "Not masked,Masked" bitfld.word 0x0 8. " [8] ,Identifier Mask bit 8" "Not masked,Masked" bitfld.word 0x0 7. " [7] ,Identifier Mask bit 7" "Not masked,Masked" bitfld.word 0x0 6. " [6] ,Identifier Mask bit 6" "Not masked,Masked" bitfld.word 0x0 5. " [5] ,Identifier Mask bit 5" "Not masked,Masked" bitfld.word 0x0 4. " [4] ,Identifier Mask bit 4" "Not masked,Masked" textline " " bitfld.word 0x0 3. " [3] ,Identifier Mask bit 3" "Not masked,Masked" bitfld.word 0x0 2. " [2] ,Identifier Mask bit 2" "Not masked,Masked" bitfld.word 0x0 1. " [1] ,Identifier Mask bit 1" "Not masked,Masked" bitfld.word 0x0 0. " [0] ,Identifier Mask bit 0" "Not masked,Masked" line.word 0x2 "IF2MSK2,IF2 Mask Registers 2 (Mask bits of Message Object)" bitfld.word 0x2 15. " MXTD ,Mask Extended Identifier" "No compare,Compare" bitfld.word 0x2 14. " MDIR ,Mask Message Direction (effect of DIR in filtering)" "Masked,Not masked" textline " " bitfld.word 0x2 12. " MSK_[28] ,Identifier Mask bit 27" "Not masked,Masked" bitfld.word 0x2 11. " [27] ,Identifier Mask bit 26" "Not masked,Masked" bitfld.word 0x2 10. " [26] ,Identifier Mask bit 25" "Not masked,Masked" bitfld.word 0x2 9. " [25] ,Identifier Mask bit 24" "Not masked,Masked" bitfld.word 0x2 8. " [24] ,Identifier Mask bit 23" "Not masked,Masked" bitfld.word 0x2 7. " [23] ,Identifier Mask bit 22" "Not masked,Masked" textline " " bitfld.word 0x2 6. " [22] ,Identifier Mask bit 21" "Not masked,Masked" bitfld.word 0x2 5. " [21] ,Identifier Mask bit 20" "Not masked,Masked" bitfld.word 0x2 4. " [20] ,Identifier Mask bit 19" "Not masked,Masked" bitfld.word 0x2 3. " [19] ,Identifier Mask bit 18" "Not masked,Masked" bitfld.word 0x2 2. " [18] ,Identifier Mask bit 17" "Not masked,Masked" bitfld.word 0x2 1. " [17] ,Identifier Mask bit 16" "Not masked,Masked" textline " " bitfld.word 0x2 0. " [16] ,Identifier Mask bit " "Not masked,Masked" line.word 0x4 "IF2ARB1,IF2 Arbitration Register 1" line.word 0x6 "IF2ARB2,IF2 Arbitration Registers 2" bitfld.word 0x6 15. " MSGVAL ,Message Valid (Message Object is:)" "Invalid,Valid" bitfld.word 0x6 14. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.word 0x6 13. " DIR ,Message Direction" "Receive,Transmit" textline " " hexmask.word 0x6 0.--12. 1. " ID[28-16] ,Message Identifier bits 28...16" if (((d.w(ad:0x40062000+0x40+0xA))&0x2000)==0x2000) if (((d.b(ad:0x40062000+0x40+0x2))&0x04)==0x04) group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif else if (((d.b(ad:0x40062000+0x40+0x2))&0x04)==0x04) group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif endif group.word (0x40+0x10)++0x7 line.word 0x0 "IF2DTA1,IF2 Data A Register 1" hexmask.word.byte 0x0 8.--15. 1. " DATA0 ,IF2 Data A Register 1 Data(0)" hexmask.word.byte 0x0 0.--7. 1. " DATA1 ,IF2 Data A Register 1 Data(1)" line.word 0x2 "IF2DTA2,IF2 Data A Register 2" hexmask.word.byte 0x2 8.--15. 1. " DATA2 ,IF2 Data A Register 2 Data(2)" hexmask.word.byte 0x2 0.--7. 1. " DATA3 ,IF2 Data A Register 2 Data(3)" line.word 0x4 "IF2DTB1,IF2 Data B Register 1" hexmask.word.byte 0x4 8.--15. 1. " DATA4 ,IF2 Data B Register 1 Data(4)" hexmask.word.byte 0x4 0.--7. 1. " DATA5 ,IF2 Data B Register 1 Data(5)" line.word 0x6 "IF2DTB2,IF2 Data B Register 2" hexmask.word.byte 0x6 8.--15. 1. " DATA6 ,IF2 Data B Register 2 Data(6)" hexmask.word.byte 0x6 0.--7. 1. " DATA7 ,IF2 Data B Register 2 Data(7)" group.word (0x40+0x20)++0x7 line.word 0x0 "IF2DTA2,IF2 Data A Register 2" hexmask.word.byte 0x0 8.--15. 1. " DATA8 ,IF2 Data A Register 1 Data(8)" hexmask.word.byte 0x0 0.--7. 1. " DATA9 ,IF2 Data A Register 1 Data(9)" line.word 0x2 "IF2DTA1,IF2 Data A Register 1" hexmask.word.byte 0x2 8.--15. 1. " DATA10 ,IF2 Data A Register 2 Data(10)" hexmask.word.byte 0x2 0.--7. 1. " DATA11 ,IF2 Data A Register 2 Data(11)" line.word 0x4 "IF2DTB2,IF2 Data B Register 2" hexmask.word.byte 0x4 8.--15. 1. " DATA12 ,IF2 Data B Register 1 Data(12)" hexmask.word.byte 0x4 0.--7. 1. " DATA13 ,IF2 Data B Register 1 Data(13)" line.word 0x6 "IF2DTB1,IF2 Data B Register 1" hexmask.word.byte 0x6 8.--15. 1. " DATA14 ,IF2 Data B Register 2 Data(14)" hexmask.word.byte 0x6 0.--7. 1. " DATA15 ,IF2 Data B Register 2 Data(15)" tree.end tree.end tree "Message Handler Registers" rgroup.word 0x80++0x4 line.word 0x2 "TREQR2,Transmission Request Register for Message Objects 32-17" bitfld.word 0x2 15. " TXRQST_[32] ,Transmission Request MO 32" "Idle,Busy" bitfld.word 0x2 14. " [31] ,Transmission Request MO 31" "Idle,Busy" bitfld.word 0x2 13. " [30] ,Transmission Request MO 30" "Idle,Busy" bitfld.word 0x2 12. " [29] ,Transmission Request MO 29" "Idle,Busy" bitfld.word 0x2 11. " [28] ,Transmission Request MO 28" "Idle,Busy" bitfld.word 0x2 10. " [27] ,Transmission Request MO 27" "Idle,Busy" textline " " bitfld.word 0x2 9. " [26] ,Transmission Request MO 26" "Idle,Busy" bitfld.word 0x2 8. " [25] ,Transmission Request MO 25" "Idle,Busy" bitfld.word 0x2 7. " [24] ,Transmission Request MO 24" "Idle,Busy" bitfld.word 0x2 6. " [23] ,Transmission Request MO 23" "Idle,Busy" bitfld.word 0x2 5. " [22] ,Transmission Request MO 22" "Idle,Busy" bitfld.word 0x2 4. " [21] ,Transmission Request MO 21" "Idle,Busy" textline " " bitfld.word 0x2 3. " [20] ,Transmission Request MO 20" "Idle,Busy" bitfld.word 0x2 2. " [19] ,Transmission Request MO 19" "Idle,Busy" bitfld.word 0x2 1. " [18] ,Transmission Request MO 18" "Idle,Busy" bitfld.word 0x2 0. " [17] ,Transmission Request MO 17" "Idle,Busy" line.word 0x0 "TREQR1,Transmission Request Register for Message Objects 16-1" bitfld.word 0x0 15. " TXRQST_[16] ,Transmission Request MO 16" "Idle,Busy" bitfld.word 0x0 14. " [15] ,Transmission Request MO 15" "Idle,Busy" bitfld.word 0x0 13. " [14] ,Transmission Request MO 14" "Idle,Busy" bitfld.word 0x0 12. " [13] ,Transmission Request MO 13" "Idle,Busy" bitfld.word 0x0 11. " [12] ,Transmission Request MO 12" "Idle,Busy" bitfld.word 0x0 10. " [11] ,Transmission Request MO 11" "Idle,Busy" textline " " bitfld.word 0x0 9. " [10] ,Transmission Request MO 10" "Idle,Busy" bitfld.word 0x0 8. " [9] ,Transmission Request MO 9" "Idle,Busy" bitfld.word 0x0 7. " [8] ,Transmission Request MO 8" "Idle,Busy" bitfld.word 0x0 6. " [7] ,Transmission Request MO 7" "Idle,Busy" bitfld.word 0x0 5. " [6] ,Transmission Request MO 6" "Idle,Busy" bitfld.word 0x0 4. " [5] ,Transmission Request MO 5" "Idle,Busy" textline " " bitfld.word 0x0 3. " [4] ,Transmission Request MO 4" "Idle,Busy" bitfld.word 0x0 2. " [3] ,Transmission Request MO 3" "Idle,Busy" bitfld.word 0x0 1. " [2] ,Transmission Request MO 2" "Idle,Busy" bitfld.word 0x0 0. " [1] ,Transmission Request MO 1" "Idle,Busy" rgroup.word 0x90++0x3 line.word 0x2 "NEWDT2,New Data Register for Message Objects 32-17" bitfld.word 0x2 15. " NEWDAT_[32] ,New Data on MO 32" "No valid data,Valid data" bitfld.word 0x2 14. " [31] ,New Data on MO 31" "No valid data,Valid data" bitfld.word 0x2 13. " [30] ,New Data on MO 30" "No valid data,Valid data" bitfld.word 0x2 12. " [29] ,New Data on MO 29" "No valid data,Valid data" bitfld.word 0x2 11. " [28] ,New Data on MO 28" "No valid data,Valid data" textline " " bitfld.word 0x2 10. " [27] ,New Data on MO 27" "No valid data,Valid data" bitfld.word 0x2 9. " [26] ,New Data on MO 26" "No valid data,Valid data" bitfld.word 0x2 8. " [25] ,New Data on MO 25" "No valid data,Valid data" bitfld.word 0x2 7. " [24] ,New Data on MO 24" "No valid data,Valid data" bitfld.word 0x2 6. " [23] ,New Data on MO 23" "No valid data,Valid data" textline " " bitfld.word 0x2 5. " [22] ,New Data on MO 22" "No valid data,Valid data" bitfld.word 0x2 4. " [21] ,New Data on MO 21" "No valid data,Valid data" bitfld.word 0x2 3. " [20] ,New Data on MO 20" "No valid data,Valid data" bitfld.word 0x2 2. " [19] ,New Data on MO 19" "No valid data,Valid data" bitfld.word 0x2 1. " [18] ,New Data on MO 18" "No valid data,Valid data" textline " " bitfld.word 0x2 0. " [17] ,New Data on MO 17" "No valid data,Valid data" line.word 0x0 "NEWDT1,New Data Register for Message Objects 16-1" bitfld.word 0x0 15. " NEWDAT_[16] ,New Data on MO 16" "No valid data,Valid data" bitfld.word 0x0 14. " [15] ,New Data on MO 15" "No valid data,Valid data" bitfld.word 0x0 13. " [14] ,New Data on MO 14" "No valid data,Valid data" bitfld.word 0x0 12. " [13] ,New Data on MO 13" "No valid data,Valid data" bitfld.word 0x0 11. " [12] ,New Data on MO 12" "No valid data,Valid data" textline " " bitfld.word 0x0 10. " [11] ,New Data on MO 11" "No valid data,Valid data" bitfld.word 0x0 9. " [10] ,New Data on MO 10" "No valid data,Valid data" bitfld.word 0x0 8. " [9] ,New Data on MO 9" "No valid data,Valid data" bitfld.word 0x0 7. " [8] ,New Data on MO 8" "No valid data,Valid data" bitfld.word 0x0 6. " [7] ,New Data on MO 7" "No valid data,Valid data" textline " " bitfld.word 0x0 5. " [6] ,New Data on MO 6" "No valid data,Valid data" bitfld.word 0x0 4. " [5] ,New Data on MO 5" "No valid data,Valid data" bitfld.word 0x0 3. " [4] ,New Data on MO 4" "No valid data,Valid data" bitfld.word 0x0 2. " [3] ,New Data on MO 3" "No valid data,Valid data" bitfld.word 0x0 1. " [2] ,New Data on MO 2" "No valid data,Valid data" textline " " bitfld.word 0x0 0. " [1] ,New Data on MO 1" "No valid data,Valid data" rgroup.word 0xA0++0x3 line.word 0x2 "INTPND2,Interrupt Pending Register for Message Objects 32-17" bitfld.word 0x2 15. " INTPND_[32] ,MO 32 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 14. " [31] ,MO 31 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 13. " [30] ,MO 30 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 12. " [29] ,MO 29 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 11. " [28] ,MO 28 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 10. " [27] ,MO 27 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x2 9. " [26] ,MO 26 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 8. " [25] ,MO 25 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 7. " [24] ,MO 24 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 6. " [23] ,MO 23 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 5. " [22] ,MO 22 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 4. " [21] ,MO 21 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x2 3. " [20] ,MO 20 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 2. " [19] ,MO 19 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 1. " [18] ,MO 18 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 0. " [17] ,MO 17 Interrupt Pending" "Not pending,Pending" line.word 0x0 "INTPND1,Interrupt Pending Register for Message Objects 16-1" bitfld.word 0x0 15. " INTPND_[16] ,MO 16 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 14. " [15] ,MO 15 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 13. " [14] ,MO 14 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " [13] ,MO 13 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 11. " [12] ,MO 12 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 10. " [11] ,MO 11 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 9. " [10] ,MO 10 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 8. " [9] ,MO 9 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 7. " [8] ,MO 8 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 6. " [7] ,MO 7 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 5. " [6] ,MO 6 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 4. " [5] ,MO 5 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 3. " [4] ,MO 4 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 2. " [3] ,MO 3 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 1. " [2] ,MO 2 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 0. " [1] ,MO 1 Interrupt Pending" "Not pending,Pending" rgroup.word 0xB0++0x3 line.word 0x2 "MSGVAL2,Message Valid Register for Message Objects 32-17" bitfld.word 0x2 15. " MSGVAL_[32] ,Validity status of MO 32" "Not valid,Valid" bitfld.word 0x2 14. " [31] ,Validity status of MO 31" "Not valid,Valid" bitfld.word 0x2 13. " [30] ,Validity status of MO 30" "Not valid,Valid" bitfld.word 0x2 12. " [29] ,Validity status of MO 29" "Not valid,Valid" bitfld.word 0x2 11. " [28] ,Validity status of MO 28" "Not valid,Valid" bitfld.word 0x2 10. " [27] ,Validity status of MO 27" "Not valid,Valid" textline " " bitfld.word 0x2 9. " [26] ,Validity status of MO 26" "Not valid,Valid" bitfld.word 0x2 8. " [25] ,Validity status of MO 25" "Not valid,Valid" bitfld.word 0x2 7. " [24] ,Validity status of MO 24" "Not valid,Valid" bitfld.word 0x2 6. " [23] ,Validity status of MO 23" "Not valid,Valid" bitfld.word 0x2 5. " [22] ,Validity status of MO 22" "Not valid,Valid" bitfld.word 0x2 4. " [21] ,Validity status of MO 21" "Not valid,Valid" textline " " bitfld.word 0x2 3. " [20] ,Validity status of MO 20" "Not valid,Valid" bitfld.word 0x2 2. " [19] ,Validity status of MO 19" "Not valid,Valid" bitfld.word 0x2 1. " [18] ,Validity status of MO 18" "Not valid,Valid" bitfld.word 0x2 0. " [17] ,Validity status of MO 17" "Not valid,Valid" line.word 0x0 "MSGVAL1,Message Valid Register for Message Objects 16-1" bitfld.word 0x0 15. " MSGVAL_[16] ,Validity status of MO 16" "Not valid,Valid" bitfld.word 0x0 14. " [15] ,Validity status of MO 15" "Not valid,Valid" bitfld.word 0x0 13. " [14] ,Validity status of MO 14" "Not valid,Valid" bitfld.word 0x0 12. " [13] ,Validity status of MO 13" "Not valid,Valid" bitfld.word 0x0 11. " [12] ,Validity status of MO 12" "Not valid,Valid" bitfld.word 0x0 10. " [11] ,Validity status of MO 11" "Not valid,Valid" textline " " bitfld.word 0x0 9. " [10] ,Validity status of MO 10" "Not valid,Valid" bitfld.word 0x0 8. " [9] ,Validity status of MO 9" "Not valid,Valid" bitfld.word 0x0 7. " [8] ,Validity status of MO 8" "Not valid,Valid" bitfld.word 0x0 6. " [7] ,Validity status of MO 7" "Not valid,Valid" bitfld.word 0x0 5. " [6] ,Validity status of MO 6" "Not valid,Valid" bitfld.word 0x0 4. " [5] ,Validity status of MO 5" "Not valid,Valid" textline " " bitfld.word 0x0 3. " [4] ,Validity status of MO 4" "Not valid,Valid" bitfld.word 0x0 2. " [3] ,Validity status of MO 3" "Not valid,Valid" bitfld.word 0x0 1. " [2] ,Validity status of MO 2" "Not valid,Valid" bitfld.word 0x0 0. " [1] ,Validity status of MO 1" "Not valid,Valid" tree.end width 12. tree.end endif sif (!cpuis("MB9BF429S")&&!cpuis("MB9BF429T")&&!cpuis("MB9BF428S")&&!cpuis("MB9BF428T")&&!cpuis("MB9BF529S")&&!cpuis("MB9BF529T")&&!cpuis("MB9BF528S")&&!cpuis("MB9BF528T")) tree "Channel 1" base ad:0x40063000 width 9. tree "Total Control Registers" if (((d.w(ad:0x40063000))&0x1)==0x1) group.word 0x0++0x1 line.word 0x0 "CTRLR,CAN Control Register" bitfld.word 0x0 7. " TEST ,Test Mode Enable" "Disabled,Enabled" bitfld.word 0x0 6. " CCE ,Configuration Change Enable" "Disabled,Enabled" bitfld.word 0x0 5. " DAR ,Disable Automatic Retransmission" "No,Yes" textline " " bitfld.word 0x0 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 1. " IE ,Module Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 0. " INIT ,Initialization" "Normal,Initialization" else group.word 0x0++0x1 line.word 0x0 "CTRLR,CAN Control Register" bitfld.word 0x0 7. " TEST ,Test Mode Enable" "Disabled,?..." bitfld.word 0x0 6. " CCE ,Configuration Change Enable" "No effect,No effect" bitfld.word 0x0 5. " DAR ,Disable Automatic Retransmission" "No,Yes" textline " " bitfld.word 0x0 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 1. " IE ,Module Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 0. " INIT ,Initialization" "Normal,Initialization" endif group.word 0x2++0x1 line.word 0x0 "STATR,Status Register" rbitfld.word 0x00 7. " BOFF ,CAN bus busoff state" "Disabled,Enabled" rbitfld.word 0x00 6. " EWARN ,Send/receive counter" "<96,>=96" rbitfld.word 0x00 5. " EPASS ,Error passive state" "Below 128,128-255" textline " " bitfld.word 0x00 4. " RXOK ,Successful message reception" "Not successful,Successful" bitfld.word 0x00 3. " TXOK ,Successful message transmission" "Not successful,Successful" bitfld.word 0x00 0.--2. " LEC ,Last error code" "Normal,Stuff error,Form error,Ack error,Bit 1 error,Bit 0 error,CRC error,Undetected" rgroup.word 0x4++0x1 line.word 0x0 "ERRCNT,Error Counter" bitfld.word 0x0 15. " RP ,Receive Error Passive" "Below level,Reached level" hexmask.word.byte 0x0 8.--14. 0x1 " REC[6:0] ,Receive Error Counter" hexmask.word.byte 0x0 0.--7. 0x1 " TEC[7:0] ,Transmit Error Counter" group.word 0x6++0x1 line.word 0x0 "BTR,Bit Timing Register" bitfld.word 0x0 12.--14. " TSEG2 ,The time segment after sample point" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--11. " TSEG1 ,The time segment before sample point" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0 6.--7. " SJW ,(Re)Synchronisation Jump Width" "0,1,2,3" textline " " bitfld.word 0x0 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hgroup.word 0x8++0x1 hide.word 0x0 "INTR,Interrupt Register (indicates message interrupt code and status interrupt code)" in group.word 0xA++0x3 line.word 0x0 "TESTR,Test Register" rbitfld.word 0x0 7. " RX ,Monitors the actual value of the CAN_RX Pin" "Dominant,Recessive" bitfld.word 0x0 5.--6. " TX[1:0] ,Control of CAN_TX pin" "Normal,Sample point,Dominant,Recessive" bitfld.word 0x0 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" textline " " bitfld.word 0x0 3. " SILENT ,Silent Mode" "Disabled,Enabled" bitfld.word 0x0 2. " BASIC ,Basic Mode" "Disabled,Enabled" line.word 0x2 "BRPER,BRP Extension Register" bitfld.word 0x2 0.--3. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "Message Interface Registers" tree "IF1 Registers" group.word 0x10++0x1 line.word 0x0 "IF1CREQ,IF1 Command Request Register" bitfld.word 0x0 15. " BUSY ,Busy Flag" "Not busy,Busy" hexmask.word.byte 0x0 0.--7. 0x1 " MSGN ,Message Number" if ((d.w(ad:0x40063000+0xA)&0x04)==0x04) hgroup.word (0x10+0x2)++0x1 hide.word 0x0 "IF1CMSK,IF1 Command Mask Register" elif (((d.w(ad:0x40063000+0x10+0x2))&0x80)==0x80) group.word (0x10+0x2)++0x1 line.word 0x0 "IF1CMSK,IF1 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 2. " TXREQ ,Message transmission request bit" "Not requested,Requested" bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" textline " " bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" else group.word (0x10+0x2)++0x1 line.word 0x0 "IF1CMSK,IF1 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 3. " CIP ,Clear Interrupt Pending Bit (INTPND)" "No effect,Clear" bitfld.word 0x0 2. " TXREQ ,Data update bit" "Not cleared,Cleared" textline " " bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" endif group.word (0x10+0x4)++0x7 line.word 0x0 "IF1MSK1,IF1 Mask Registers 1" bitfld.word 0x0 15. " MSK_[15] ,Identifier Mask bit 15" "Not masked,Masked" bitfld.word 0x0 14. " [14] ,Identifier Mask bit 14" "Not masked,Masked" bitfld.word 0x0 13. " [13] ,Identifier Mask bit 13" "Not masked,Masked" bitfld.word 0x0 12. " [12] ,Identifier Mask bit 12" "Not masked,Masked" bitfld.word 0x0 11. " [11] ,Identifier Mask bit 11" "Not masked,Masked" bitfld.word 0x0 10. " [10] ,Identifier Mask bit 10" "Not masked,Masked" textline " " bitfld.word 0x0 9. " [9] ,Identifier Mask bit 9" "Not masked,Masked" bitfld.word 0x0 8. " [8] ,Identifier Mask bit 8" "Not masked,Masked" bitfld.word 0x0 7. " [7] ,Identifier Mask bit 7" "Not masked,Masked" bitfld.word 0x0 6. " [6] ,Identifier Mask bit 6" "Not masked,Masked" bitfld.word 0x0 5. " [5] ,Identifier Mask bit 5" "Not masked,Masked" bitfld.word 0x0 4. " [4] ,Identifier Mask bit 4" "Not masked,Masked" textline " " bitfld.word 0x0 3. " [3] ,Identifier Mask bit 3" "Not masked,Masked" bitfld.word 0x0 2. " [2] ,Identifier Mask bit 2" "Not masked,Masked" bitfld.word 0x0 1. " [1] ,Identifier Mask bit 1" "Not masked,Masked" bitfld.word 0x0 0. " [0] ,Identifier Mask bit 0" "Not masked,Masked" line.word 0x2 "IF1MSK2,IF1 Mask Registers 2 (Mask bits of Message Object)" bitfld.word 0x2 15. " MXTD ,Mask Extended Identifier" "No compare,Compare" bitfld.word 0x2 14. " MDIR ,Mask Message Direction (effect of DIR in filtering)" "Masked,Not masked" textline " " bitfld.word 0x2 12. " MSK_[28] ,Identifier Mask bit 27" "Not masked,Masked" bitfld.word 0x2 11. " [27] ,Identifier Mask bit 26" "Not masked,Masked" bitfld.word 0x2 10. " [26] ,Identifier Mask bit 25" "Not masked,Masked" bitfld.word 0x2 9. " [25] ,Identifier Mask bit 24" "Not masked,Masked" bitfld.word 0x2 8. " [24] ,Identifier Mask bit 23" "Not masked,Masked" bitfld.word 0x2 7. " [23] ,Identifier Mask bit 22" "Not masked,Masked" textline " " bitfld.word 0x2 6. " [22] ,Identifier Mask bit 21" "Not masked,Masked" bitfld.word 0x2 5. " [21] ,Identifier Mask bit 20" "Not masked,Masked" bitfld.word 0x2 4. " [20] ,Identifier Mask bit 19" "Not masked,Masked" bitfld.word 0x2 3. " [19] ,Identifier Mask bit 18" "Not masked,Masked" bitfld.word 0x2 2. " [18] ,Identifier Mask bit 17" "Not masked,Masked" bitfld.word 0x2 1. " [17] ,Identifier Mask bit 16" "Not masked,Masked" textline " " bitfld.word 0x2 0. " [16] ,Identifier Mask bit " "Not masked,Masked" line.word 0x4 "IF1ARB1,IF1 Arbitration Register 1" line.word 0x6 "IF1ARB2,IF1 Arbitration Registers 2" bitfld.word 0x6 15. " MSGVAL ,Message Valid (Message Object is:)" "Invalid,Valid" bitfld.word 0x6 14. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.word 0x6 13. " DIR ,Message Direction" "Receive,Transmit" textline " " hexmask.word 0x6 0.--12. 1. " ID[28-16] ,Message Identifier bits 28...16" if (((d.w(ad:0x40063000+0x10+0xA))&0x2000)==0x2000) if (((d.b(ad:0x40063000+0x10+0x2))&0x04)==0x04) group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif else if (((d.b(ad:0x40063000+0x10+0x2))&0x04)==0x04) group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x10+0xC)++0x1 line.word 0x0 "IF1MCTR,IF1 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif endif group.word (0x10+0x10)++0x7 line.word 0x0 "IF1DTA1,IF1 Data A Register 1" hexmask.word.byte 0x0 8.--15. 1. " DATA0 ,IF1 Data A Register 1 Data(0)" hexmask.word.byte 0x0 0.--7. 1. " DATA1 ,IF1 Data A Register 1 Data(1)" line.word 0x2 "IF1DTA2,IF1 Data A Register 2" hexmask.word.byte 0x2 8.--15. 1. " DATA2 ,IF1 Data A Register 2 Data(2)" hexmask.word.byte 0x2 0.--7. 1. " DATA3 ,IF1 Data A Register 2 Data(3)" line.word 0x4 "IF1DTB1,IF1 Data B Register 1" hexmask.word.byte 0x4 8.--15. 1. " DATA4 ,IF1 Data B Register 1 Data(4)" hexmask.word.byte 0x4 0.--7. 1. " DATA5 ,IF1 Data B Register 1 Data(5)" line.word 0x6 "IF1DTB2,IF1 Data B Register 2" hexmask.word.byte 0x6 8.--15. 1. " DATA6 ,IF1 Data B Register 2 Data(6)" hexmask.word.byte 0x6 0.--7. 1. " DATA7 ,IF1 Data B Register 2 Data(7)" group.word (0x10+0x20)++0x7 line.word 0x0 "IF1DTA2,IF1 Data A Register 2" hexmask.word.byte 0x0 8.--15. 1. " DATA8 ,IF1 Data A Register 1 Data(8)" hexmask.word.byte 0x0 0.--7. 1. " DATA9 ,IF1 Data A Register 1 Data(9)" line.word 0x2 "IF1DTA1,IF1 Data A Register 1" hexmask.word.byte 0x2 8.--15. 1. " DATA10 ,IF1 Data A Register 2 Data(10)" hexmask.word.byte 0x2 0.--7. 1. " DATA11 ,IF1 Data A Register 2 Data(11)" line.word 0x4 "IF1DTB2,IF1 Data B Register 2" hexmask.word.byte 0x4 8.--15. 1. " DATA12 ,IF1 Data B Register 1 Data(12)" hexmask.word.byte 0x4 0.--7. 1. " DATA13 ,IF1 Data B Register 1 Data(13)" line.word 0x6 "IF1DTB1,IF1 Data B Register 1" hexmask.word.byte 0x6 8.--15. 1. " DATA14 ,IF1 Data B Register 2 Data(14)" hexmask.word.byte 0x6 0.--7. 1. " DATA15 ,IF1 Data B Register 2 Data(15)" tree.end tree "IF2 Registers" group.word 0x40++0x1 line.word 0x0 "IF2CREQ,IF2 Command Request Register" bitfld.word 0x0 15. " BUSY ,Busy Flag" "Not busy,Busy" hexmask.word.byte 0x0 0.--7. 0x1 " MSGN ,Message Number" if ((d.w(ad:0x40063000+0xA)&0x04)==0x04) hgroup.word (0x40+0x2)++0x1 hide.word 0x0 "IF2CMSK,IF2 Command Mask Register" elif (((d.w(ad:0x40063000+0x40+0x2))&0x80)==0x80) group.word (0x40+0x2)++0x1 line.word 0x0 "IF2CMSK,IF2 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 2. " TXREQ ,Message transmission request bit" "Not requested,Requested" bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" textline " " bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" else group.word (0x40+0x2)++0x1 line.word 0x0 "IF2CMSK,IF2 Command Mask Register" bitfld.word 0x0 7. " WRRD ,Write/Read" "Read,Write" bitfld.word 0x0 6. " MASK ,Mask data update bit" "Not updated,Updated" bitfld.word 0x0 5. " ARB ,Arbitration data update bit" "Not updated,Updated" textline " " bitfld.word 0x0 4. " CONTROL ,Control data update bit" "Not updated,Updated" bitfld.word 0x0 3. " CIP ,Clear Interrupt Pending Bit (INTPND)" "No effect,Clear" bitfld.word 0x0 2. " TXREQ ,Data update bit" "Not cleared,Cleared" textline " " bitfld.word 0x0 1. " DATAA ,Data 0-3 update bit" "Not updated,Updated" bitfld.word 0x0 0. " DATAB ,Data 4-7 update bit" "Not updated,Updated" endif group.word (0x40+0x4)++0x7 line.word 0x0 "IF2MSK1,IF2 Mask Registers 1" bitfld.word 0x0 15. " MSK_[15] ,Identifier Mask bit 15" "Not masked,Masked" bitfld.word 0x0 14. " [14] ,Identifier Mask bit 14" "Not masked,Masked" bitfld.word 0x0 13. " [13] ,Identifier Mask bit 13" "Not masked,Masked" bitfld.word 0x0 12. " [12] ,Identifier Mask bit 12" "Not masked,Masked" bitfld.word 0x0 11. " [11] ,Identifier Mask bit 11" "Not masked,Masked" bitfld.word 0x0 10. " [10] ,Identifier Mask bit 10" "Not masked,Masked" textline " " bitfld.word 0x0 9. " [9] ,Identifier Mask bit 9" "Not masked,Masked" bitfld.word 0x0 8. " [8] ,Identifier Mask bit 8" "Not masked,Masked" bitfld.word 0x0 7. " [7] ,Identifier Mask bit 7" "Not masked,Masked" bitfld.word 0x0 6. " [6] ,Identifier Mask bit 6" "Not masked,Masked" bitfld.word 0x0 5. " [5] ,Identifier Mask bit 5" "Not masked,Masked" bitfld.word 0x0 4. " [4] ,Identifier Mask bit 4" "Not masked,Masked" textline " " bitfld.word 0x0 3. " [3] ,Identifier Mask bit 3" "Not masked,Masked" bitfld.word 0x0 2. " [2] ,Identifier Mask bit 2" "Not masked,Masked" bitfld.word 0x0 1. " [1] ,Identifier Mask bit 1" "Not masked,Masked" bitfld.word 0x0 0. " [0] ,Identifier Mask bit 0" "Not masked,Masked" line.word 0x2 "IF2MSK2,IF2 Mask Registers 2 (Mask bits of Message Object)" bitfld.word 0x2 15. " MXTD ,Mask Extended Identifier" "No compare,Compare" bitfld.word 0x2 14. " MDIR ,Mask Message Direction (effect of DIR in filtering)" "Masked,Not masked" textline " " bitfld.word 0x2 12. " MSK_[28] ,Identifier Mask bit 27" "Not masked,Masked" bitfld.word 0x2 11. " [27] ,Identifier Mask bit 26" "Not masked,Masked" bitfld.word 0x2 10. " [26] ,Identifier Mask bit 25" "Not masked,Masked" bitfld.word 0x2 9. " [25] ,Identifier Mask bit 24" "Not masked,Masked" bitfld.word 0x2 8. " [24] ,Identifier Mask bit 23" "Not masked,Masked" bitfld.word 0x2 7. " [23] ,Identifier Mask bit 22" "Not masked,Masked" textline " " bitfld.word 0x2 6. " [22] ,Identifier Mask bit 21" "Not masked,Masked" bitfld.word 0x2 5. " [21] ,Identifier Mask bit 20" "Not masked,Masked" bitfld.word 0x2 4. " [20] ,Identifier Mask bit 19" "Not masked,Masked" bitfld.word 0x2 3. " [19] ,Identifier Mask bit 18" "Not masked,Masked" bitfld.word 0x2 2. " [18] ,Identifier Mask bit 17" "Not masked,Masked" bitfld.word 0x2 1. " [17] ,Identifier Mask bit 16" "Not masked,Masked" textline " " bitfld.word 0x2 0. " [16] ,Identifier Mask bit " "Not masked,Masked" line.word 0x4 "IF2ARB1,IF2 Arbitration Register 1" line.word 0x6 "IF2ARB2,IF2 Arbitration Registers 2" bitfld.word 0x6 15. " MSGVAL ,Message Valid (Message Object is:)" "Invalid,Valid" bitfld.word 0x6 14. " XTD ,Extended Identifier" "11-bit,29-bit" bitfld.word 0x6 13. " DIR ,Message Direction" "Receive,Transmit" textline " " hexmask.word 0x6 0.--12. 1. " ID[28-16] ,Message Identifier bits 28...16" if (((d.w(ad:0x40063000+0x40+0xA))&0x2000)==0x2000) if (((d.b(ad:0x40063000+0x40+0x2))&0x04)==0x04) group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" textline " " bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif else if (((d.b(ad:0x40063000+0x40+0x2))&0x04)==0x04) group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" rbitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" else group.word (0x40+0xC)++0x1 line.word 0x0 "IF2MCTR,IF2 Message Control Register" bitfld.word 0x0 15. " NEWDAT ,New Data" "No new data,New data" bitfld.word 0x0 14. " MSGLST ,Message Lost" "Not lost,Lost" bitfld.word 0x0 13. " INTPND ,Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.word 0x0 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.word 0x0 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.word 0x0 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.word 0x0 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.word 0x0 7. " EOB ,End of FIFO Buffer" "No EOB,EOB" textline " " bitfld.word 0x0 0.--3. " DLC[3:0] ,Data Length Code (in bytes)" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" endif endif group.word (0x40+0x10)++0x7 line.word 0x0 "IF2DTA1,IF2 Data A Register 1" hexmask.word.byte 0x0 8.--15. 1. " DATA0 ,IF2 Data A Register 1 Data(0)" hexmask.word.byte 0x0 0.--7. 1. " DATA1 ,IF2 Data A Register 1 Data(1)" line.word 0x2 "IF2DTA2,IF2 Data A Register 2" hexmask.word.byte 0x2 8.--15. 1. " DATA2 ,IF2 Data A Register 2 Data(2)" hexmask.word.byte 0x2 0.--7. 1. " DATA3 ,IF2 Data A Register 2 Data(3)" line.word 0x4 "IF2DTB1,IF2 Data B Register 1" hexmask.word.byte 0x4 8.--15. 1. " DATA4 ,IF2 Data B Register 1 Data(4)" hexmask.word.byte 0x4 0.--7. 1. " DATA5 ,IF2 Data B Register 1 Data(5)" line.word 0x6 "IF2DTB2,IF2 Data B Register 2" hexmask.word.byte 0x6 8.--15. 1. " DATA6 ,IF2 Data B Register 2 Data(6)" hexmask.word.byte 0x6 0.--7. 1. " DATA7 ,IF2 Data B Register 2 Data(7)" group.word (0x40+0x20)++0x7 line.word 0x0 "IF2DTA2,IF2 Data A Register 2" hexmask.word.byte 0x0 8.--15. 1. " DATA8 ,IF2 Data A Register 1 Data(8)" hexmask.word.byte 0x0 0.--7. 1. " DATA9 ,IF2 Data A Register 1 Data(9)" line.word 0x2 "IF2DTA1,IF2 Data A Register 1" hexmask.word.byte 0x2 8.--15. 1. " DATA10 ,IF2 Data A Register 2 Data(10)" hexmask.word.byte 0x2 0.--7. 1. " DATA11 ,IF2 Data A Register 2 Data(11)" line.word 0x4 "IF2DTB2,IF2 Data B Register 2" hexmask.word.byte 0x4 8.--15. 1. " DATA12 ,IF2 Data B Register 1 Data(12)" hexmask.word.byte 0x4 0.--7. 1. " DATA13 ,IF2 Data B Register 1 Data(13)" line.word 0x6 "IF2DTB1,IF2 Data B Register 1" hexmask.word.byte 0x6 8.--15. 1. " DATA14 ,IF2 Data B Register 2 Data(14)" hexmask.word.byte 0x6 0.--7. 1. " DATA15 ,IF2 Data B Register 2 Data(15)" tree.end tree.end tree "Message Handler Registers" rgroup.word 0x80++0x4 line.word 0x2 "TREQR2,Transmission Request Register for Message Objects 32-17" bitfld.word 0x2 15. " TXRQST_[32] ,Transmission Request MO 32" "Idle,Busy" bitfld.word 0x2 14. " [31] ,Transmission Request MO 31" "Idle,Busy" bitfld.word 0x2 13. " [30] ,Transmission Request MO 30" "Idle,Busy" bitfld.word 0x2 12. " [29] ,Transmission Request MO 29" "Idle,Busy" bitfld.word 0x2 11. " [28] ,Transmission Request MO 28" "Idle,Busy" bitfld.word 0x2 10. " [27] ,Transmission Request MO 27" "Idle,Busy" textline " " bitfld.word 0x2 9. " [26] ,Transmission Request MO 26" "Idle,Busy" bitfld.word 0x2 8. " [25] ,Transmission Request MO 25" "Idle,Busy" bitfld.word 0x2 7. " [24] ,Transmission Request MO 24" "Idle,Busy" bitfld.word 0x2 6. " [23] ,Transmission Request MO 23" "Idle,Busy" bitfld.word 0x2 5. " [22] ,Transmission Request MO 22" "Idle,Busy" bitfld.word 0x2 4. " [21] ,Transmission Request MO 21" "Idle,Busy" textline " " bitfld.word 0x2 3. " [20] ,Transmission Request MO 20" "Idle,Busy" bitfld.word 0x2 2. " [19] ,Transmission Request MO 19" "Idle,Busy" bitfld.word 0x2 1. " [18] ,Transmission Request MO 18" "Idle,Busy" bitfld.word 0x2 0. " [17] ,Transmission Request MO 17" "Idle,Busy" line.word 0x0 "TREQR1,Transmission Request Register for Message Objects 16-1" bitfld.word 0x0 15. " TXRQST_[16] ,Transmission Request MO 16" "Idle,Busy" bitfld.word 0x0 14. " [15] ,Transmission Request MO 15" "Idle,Busy" bitfld.word 0x0 13. " [14] ,Transmission Request MO 14" "Idle,Busy" bitfld.word 0x0 12. " [13] ,Transmission Request MO 13" "Idle,Busy" bitfld.word 0x0 11. " [12] ,Transmission Request MO 12" "Idle,Busy" bitfld.word 0x0 10. " [11] ,Transmission Request MO 11" "Idle,Busy" textline " " bitfld.word 0x0 9. " [10] ,Transmission Request MO 10" "Idle,Busy" bitfld.word 0x0 8. " [9] ,Transmission Request MO 9" "Idle,Busy" bitfld.word 0x0 7. " [8] ,Transmission Request MO 8" "Idle,Busy" bitfld.word 0x0 6. " [7] ,Transmission Request MO 7" "Idle,Busy" bitfld.word 0x0 5. " [6] ,Transmission Request MO 6" "Idle,Busy" bitfld.word 0x0 4. " [5] ,Transmission Request MO 5" "Idle,Busy" textline " " bitfld.word 0x0 3. " [4] ,Transmission Request MO 4" "Idle,Busy" bitfld.word 0x0 2. " [3] ,Transmission Request MO 3" "Idle,Busy" bitfld.word 0x0 1. " [2] ,Transmission Request MO 2" "Idle,Busy" bitfld.word 0x0 0. " [1] ,Transmission Request MO 1" "Idle,Busy" rgroup.word 0x90++0x3 line.word 0x2 "NEWDT2,New Data Register for Message Objects 32-17" bitfld.word 0x2 15. " NEWDAT_[32] ,New Data on MO 32" "No valid data,Valid data" bitfld.word 0x2 14. " [31] ,New Data on MO 31" "No valid data,Valid data" bitfld.word 0x2 13. " [30] ,New Data on MO 30" "No valid data,Valid data" bitfld.word 0x2 12. " [29] ,New Data on MO 29" "No valid data,Valid data" bitfld.word 0x2 11. " [28] ,New Data on MO 28" "No valid data,Valid data" textline " " bitfld.word 0x2 10. " [27] ,New Data on MO 27" "No valid data,Valid data" bitfld.word 0x2 9. " [26] ,New Data on MO 26" "No valid data,Valid data" bitfld.word 0x2 8. " [25] ,New Data on MO 25" "No valid data,Valid data" bitfld.word 0x2 7. " [24] ,New Data on MO 24" "No valid data,Valid data" bitfld.word 0x2 6. " [23] ,New Data on MO 23" "No valid data,Valid data" textline " " bitfld.word 0x2 5. " [22] ,New Data on MO 22" "No valid data,Valid data" bitfld.word 0x2 4. " [21] ,New Data on MO 21" "No valid data,Valid data" bitfld.word 0x2 3. " [20] ,New Data on MO 20" "No valid data,Valid data" bitfld.word 0x2 2. " [19] ,New Data on MO 19" "No valid data,Valid data" bitfld.word 0x2 1. " [18] ,New Data on MO 18" "No valid data,Valid data" textline " " bitfld.word 0x2 0. " [17] ,New Data on MO 17" "No valid data,Valid data" line.word 0x0 "NEWDT1,New Data Register for Message Objects 16-1" bitfld.word 0x0 15. " NEWDAT_[16] ,New Data on MO 16" "No valid data,Valid data" bitfld.word 0x0 14. " [15] ,New Data on MO 15" "No valid data,Valid data" bitfld.word 0x0 13. " [14] ,New Data on MO 14" "No valid data,Valid data" bitfld.word 0x0 12. " [13] ,New Data on MO 13" "No valid data,Valid data" bitfld.word 0x0 11. " [12] ,New Data on MO 12" "No valid data,Valid data" textline " " bitfld.word 0x0 10. " [11] ,New Data on MO 11" "No valid data,Valid data" bitfld.word 0x0 9. " [10] ,New Data on MO 10" "No valid data,Valid data" bitfld.word 0x0 8. " [9] ,New Data on MO 9" "No valid data,Valid data" bitfld.word 0x0 7. " [8] ,New Data on MO 8" "No valid data,Valid data" bitfld.word 0x0 6. " [7] ,New Data on MO 7" "No valid data,Valid data" textline " " bitfld.word 0x0 5. " [6] ,New Data on MO 6" "No valid data,Valid data" bitfld.word 0x0 4. " [5] ,New Data on MO 5" "No valid data,Valid data" bitfld.word 0x0 3. " [4] ,New Data on MO 4" "No valid data,Valid data" bitfld.word 0x0 2. " [3] ,New Data on MO 3" "No valid data,Valid data" bitfld.word 0x0 1. " [2] ,New Data on MO 2" "No valid data,Valid data" textline " " bitfld.word 0x0 0. " [1] ,New Data on MO 1" "No valid data,Valid data" rgroup.word 0xA0++0x3 line.word 0x2 "INTPND2,Interrupt Pending Register for Message Objects 32-17" bitfld.word 0x2 15. " INTPND_[32] ,MO 32 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 14. " [31] ,MO 31 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 13. " [30] ,MO 30 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 12. " [29] ,MO 29 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 11. " [28] ,MO 28 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 10. " [27] ,MO 27 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x2 9. " [26] ,MO 26 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 8. " [25] ,MO 25 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 7. " [24] ,MO 24 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 6. " [23] ,MO 23 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 5. " [22] ,MO 22 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 4. " [21] ,MO 21 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x2 3. " [20] ,MO 20 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 2. " [19] ,MO 19 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 1. " [18] ,MO 18 Interrupt Pending" "Not pending,Pending" bitfld.word 0x2 0. " [17] ,MO 17 Interrupt Pending" "Not pending,Pending" line.word 0x0 "INTPND1,Interrupt Pending Register for Message Objects 16-1" bitfld.word 0x0 15. " INTPND_[16] ,MO 16 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 14. " [15] ,MO 15 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 13. " [14] ,MO 14 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 12. " [13] ,MO 13 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 11. " [12] ,MO 12 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 10. " [11] ,MO 11 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 9. " [10] ,MO 10 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 8. " [9] ,MO 9 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 7. " [8] ,MO 8 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 6. " [7] ,MO 7 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 5. " [6] ,MO 6 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 4. " [5] ,MO 5 Interrupt Pending" "Not pending,Pending" textline " " bitfld.word 0x0 3. " [4] ,MO 4 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 2. " [3] ,MO 3 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 1. " [2] ,MO 2 Interrupt Pending" "Not pending,Pending" bitfld.word 0x0 0. " [1] ,MO 1 Interrupt Pending" "Not pending,Pending" rgroup.word 0xB0++0x3 line.word 0x2 "MSGVAL2,Message Valid Register for Message Objects 32-17" bitfld.word 0x2 15. " MSGVAL_[32] ,Validity status of MO 32" "Not valid,Valid" bitfld.word 0x2 14. " [31] ,Validity status of MO 31" "Not valid,Valid" bitfld.word 0x2 13. " [30] ,Validity status of MO 30" "Not valid,Valid" bitfld.word 0x2 12. " [29] ,Validity status of MO 29" "Not valid,Valid" bitfld.word 0x2 11. " [28] ,Validity status of MO 28" "Not valid,Valid" bitfld.word 0x2 10. " [27] ,Validity status of MO 27" "Not valid,Valid" textline " " bitfld.word 0x2 9. " [26] ,Validity status of MO 26" "Not valid,Valid" bitfld.word 0x2 8. " [25] ,Validity status of MO 25" "Not valid,Valid" bitfld.word 0x2 7. " [24] ,Validity status of MO 24" "Not valid,Valid" bitfld.word 0x2 6. " [23] ,Validity status of MO 23" "Not valid,Valid" bitfld.word 0x2 5. " [22] ,Validity status of MO 22" "Not valid,Valid" bitfld.word 0x2 4. " [21] ,Validity status of MO 21" "Not valid,Valid" textline " " bitfld.word 0x2 3. " [20] ,Validity status of MO 20" "Not valid,Valid" bitfld.word 0x2 2. " [19] ,Validity status of MO 19" "Not valid,Valid" bitfld.word 0x2 1. " [18] ,Validity status of MO 18" "Not valid,Valid" bitfld.word 0x2 0. " [17] ,Validity status of MO 17" "Not valid,Valid" line.word 0x0 "MSGVAL1,Message Valid Register for Message Objects 16-1" bitfld.word 0x0 15. " MSGVAL_[16] ,Validity status of MO 16" "Not valid,Valid" bitfld.word 0x0 14. " [15] ,Validity status of MO 15" "Not valid,Valid" bitfld.word 0x0 13. " [14] ,Validity status of MO 14" "Not valid,Valid" bitfld.word 0x0 12. " [13] ,Validity status of MO 13" "Not valid,Valid" bitfld.word 0x0 11. " [12] ,Validity status of MO 12" "Not valid,Valid" bitfld.word 0x0 10. " [11] ,Validity status of MO 11" "Not valid,Valid" textline " " bitfld.word 0x0 9. " [10] ,Validity status of MO 10" "Not valid,Valid" bitfld.word 0x0 8. " [9] ,Validity status of MO 9" "Not valid,Valid" bitfld.word 0x0 7. " [8] ,Validity status of MO 8" "Not valid,Valid" bitfld.word 0x0 6. " [7] ,Validity status of MO 7" "Not valid,Valid" bitfld.word 0x0 5. " [6] ,Validity status of MO 6" "Not valid,Valid" bitfld.word 0x0 4. " [5] ,Validity status of MO 5" "Not valid,Valid" textline " " bitfld.word 0x0 3. " [4] ,Validity status of MO 4" "Not valid,Valid" bitfld.word 0x0 2. " [3] ,Validity status of MO 3" "Not valid,Valid" bitfld.word 0x0 1. " [2] ,Validity status of MO 2" "Not valid,Valid" bitfld.word 0x0 0. " [1] ,Validity status of MO 1" "Not valid,Valid" tree.end width 12. tree.end endif tree.end endif sif (!cpuis("MB9AF13*")&&!cpuis("MB9AFA3*")&&!cpuis("MB9AF121K")&&!cpuis("MB9AF121L")&&!cpuis("MB9AF421K")&&!cpuis("MB9AF421L")&&!cpuis("MB9BF121J")&&!cpuis("MB9AFAA1L")&&!cpuis("MB9AFAA1M")&&!cpuis("MB9AFAA1N")&&!cpuis("MB9AFAA2L")&&!cpuis("MB9AFAA2M")&&!cpuis("MB9AFAA2N")&&!cpuis("MB9AF1A1L")&&!cpuis("MB9AF1A1M")&&!cpuis("MB9AF1A1N")&&!cpuis("MB9AF1A2L")&&!cpuis("MB9AF1A2M")&&!cpuis("MB9AF1A2N")) tree "CRC Registers" base ad:0x40039000 width 9. group.byte 0x0++0x0 line.byte 0x0 "CRCCR,CRC Control Register" bitfld.byte 0x00 6. " FXOR ,Final XOR control bit" "None,Yes" bitfld.byte 0x00 5. " CRCLSF ,CRC result bit-order setting bit" "MSB First,LSB First" bitfld.byte 0x00 4. " CRCLTE ,CRC result byte-order setting bit (which endian)" "Big,Little" textline " " bitfld.byte 0x00 3. " LSBFST ,Bit-order setting bit" "MSB First,LSB First" bitfld.byte 0x00 2. " LTLEND ,Byte-order setting bit (which endian)" "Big,Little" bitfld.byte 0x00 1. " CRC32 ,CRC mode selection bit" "CRC16,CRC32" textline " " bitfld.byte 0x00 0. " INIT ,Initialization bit" "Invalid,Initialization" group.long 0x4++0xB line.long 0x0 "CRCINIT,Initial Value Register (save the initial values for CRC calculation)" line.long 0x4 "CRCIN,Input Data Register (set input data for CRC calculation)" line.long 0x8 "CRCR,CRC Register (read the CRC calculation result)" width 12. tree.end endif sif ((!cpuis("MB9AF*K"))&&(!cpuis("MB9AF*L"))&&(!cpuis("MB9AF11?M"))&&(!cpuis("MB9AF11?N"))&&(!cpuis("MB9AF13?M"))&&(!cpuis("MB9AF13?N"))&&(!cpuis("MB9AFA3?M"))&&(!cpuis("MB9AFA3?N"))) tree "External Bus Interface" base ad:0x4003F000 width 7. group.long 0x0++0x1F line.long 0x0 "MODE0,Mode Register 0" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x0 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x0 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x0 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x0 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x0 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x0 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x0 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x0 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x0 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x0 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x0 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x0 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x0 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x0 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x0 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0x4 "MODE1,Mode Register 1" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x4 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x4 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x4 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x4 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x4 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x4 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x4 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x4 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x4 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x4 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x4 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x4 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x4 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x4 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x4 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0x8 "MODE2,Mode Register 2" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x8 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x8 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x8 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x8 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x8 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x8 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x8 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x8 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x8 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x8 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x8 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x8 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x8 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x8 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x8 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0xC "MODE3,Mode Register 3" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0xC 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0xC 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0xC 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0xC 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0xC 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0xC 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0xC 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0xC 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0xC 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0xC 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0xC 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0xC 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0xC 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0xC 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0xC 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0x10 "MODE4,Mode Register 4" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x10 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x10 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x10 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x10 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x10 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x10 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x10 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x10 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x10 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x10 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x10 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x10 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x10 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x10 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x10 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0x14 "MODE5,Mode Register 5" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x14 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x14 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x14 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x14 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x14 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x14 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x14 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x14 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x14 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x14 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x14 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x14 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x14 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x14 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x14 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0x18 "MODE6,Mode Register 6" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x18 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x18 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x18 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x18 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x18 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x18 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x18 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x18 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x18 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x18 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x18 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x18 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x18 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x18 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x18 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif line.long 0x1C "MODE7,Mode Register 7" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) bitfld.long 0x1C 13. " MOEXEUP ,MOEX width select" "RACC-RADC,FRADC" bitfld.long 0x1C 12. " MPXCSOF ,Asserts MCSX in ALC cycle period" "Enabled,Disabled" bitfld.long 0x1C 11. " MPXDOFF ,Outputs the address to the data lines" "Enabled,Disabled" textline " " bitfld.long 0x1C 9. " ALEINV ,ALE signal polarity" "Positive,Negative" bitfld.long 0x1C 8. " MPXMODE ,Multiplex mode" "Separate,Multiplex" bitfld.long 0x1C 7. " SHRTDOUT ,Idle cycle the write data output is extended select" "Last,First" textline " " bitfld.long 0x1C 6. " RDY ,External RDY mode" "Disabled,Enabled" bitfld.long 0x1C 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif ((!cpuis("MB9AF31?M"))&&(!cpuis("MB9AF14?M"))&&(!cpuis("MB9AF34?M"))&&(!cpuis("MB9AFA4?M"))&&(!cpuis("MB9AFB4?M"))&&(!cpuis("MB9AF31?N"))&&(!cpuis("MB9AF14?N"))&&(!cpuis("MB9AF34?N"))&&(!cpuis("MB9AFA4?N"))&&(!cpuis("MB9AFB4?N"))&&(!cpuis("MB9BF11?N"))&&(!cpuis("MB9BF31?N"))&&(!cpuis("MB9BF41?N"))&&(!cpuis("MB9BF51?N"))) bitfld.long 0x1C 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif else bitfld.long 0x1C 5. " PAGE ,NOR flash memory page access mode" "Disabled,Enabled" sif (cpu()==("MB9AF105NA")) bitfld.long 0x1C 4. " NAND ,NAND flash memory mode" "Disabled,Enabled" endif endif textline " " bitfld.long 0x1C 3. " WEOFF ,Write Enable OFF" "Yes,No" bitfld.long 0x1C 2. " RBMON ,Read Byte Mask ON" "Disabled,Enabled" sif ((cpuis("MB9AF31?M"))||(cpuis("MB9AF14?M"))||(cpuis("MB9AF34?M"))||(cpuis("MB9AFA4?M"))||(cpuis("MB9AFB4?M"))) bitfld.long 0x1C 0.--1. " WDTH ,Data Width" "8 bits,?..." else bitfld.long 0x1C 0.--1. " WDTH ,Data Width" "8 bits,16 bits,?..." endif textline "" if (((d.l(ad:0x4003F000+0x20-0x20))&0x2020)==0x0) group.long 0x20++0x03 line.long 0x00 "TIM0,Timing Register 0" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x20-0x20))&0x2020)==0x2000) group.long 0x20++0x03 line.long 0x00 "TIM0,Timing Register 0" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x20-0x20))&0x2020)==0x0020) group.long 0x20++0x03 line.long 0x00 "TIM0,Timing Register 0" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x20++0x03 line.long 0x00 "TIM0,Timing Register 0" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x24-0x20))&0x2020)==0x0) group.long 0x24++0x03 line.long 0x00 "TIM1,Timing Register 1" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x24-0x20))&0x2020)==0x2000) group.long 0x24++0x03 line.long 0x00 "TIM1,Timing Register 1" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x24-0x20))&0x2020)==0x0020) group.long 0x24++0x03 line.long 0x00 "TIM1,Timing Register 1" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x24++0x03 line.long 0x00 "TIM1,Timing Register 1" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x28-0x20))&0x2020)==0x0) group.long 0x28++0x03 line.long 0x00 "TIM2,Timing Register 2" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x28-0x20))&0x2020)==0x2000) group.long 0x28++0x03 line.long 0x00 "TIM2,Timing Register 2" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x28-0x20))&0x2020)==0x0020) group.long 0x28++0x03 line.long 0x00 "TIM2,Timing Register 2" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x28++0x03 line.long 0x00 "TIM2,Timing Register 2" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x2C-0x20))&0x2020)==0x0) group.long 0x2C++0x03 line.long 0x00 "TIM3,Timing Register 3" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x2C-0x20))&0x2020)==0x2000) group.long 0x2C++0x03 line.long 0x00 "TIM3,Timing Register 3" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x2C-0x20))&0x2020)==0x0020) group.long 0x2C++0x03 line.long 0x00 "TIM3,Timing Register 3" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x2C++0x03 line.long 0x00 "TIM3,Timing Register 3" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x30-0x20))&0x2020)==0x0) group.long 0x30++0x03 line.long 0x00 "TIM4,Timing Register 4" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x30-0x20))&0x2020)==0x2000) group.long 0x30++0x03 line.long 0x00 "TIM4,Timing Register 4" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x30-0x20))&0x2020)==0x0020) group.long 0x30++0x03 line.long 0x00 "TIM4,Timing Register 4" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x30++0x03 line.long 0x00 "TIM4,Timing Register 4" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x34-0x20))&0x2020)==0x0) group.long 0x34++0x03 line.long 0x00 "TIM5,Timing Register 5" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x34-0x20))&0x2020)==0x2000) group.long 0x34++0x03 line.long 0x00 "TIM5,Timing Register 5" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x34-0x20))&0x2020)==0x0020) group.long 0x34++0x03 line.long 0x00 "TIM5,Timing Register 5" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x34++0x03 line.long 0x00 "TIM5,Timing Register 5" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x38-0x20))&0x2020)==0x0) group.long 0x38++0x03 line.long 0x00 "TIM6,Timing Register 6" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x38-0x20))&0x2020)==0x2000) group.long 0x38++0x03 line.long 0x00 "TIM6,Timing Register 6" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x38-0x20))&0x2020)==0x0020) group.long 0x38++0x03 line.long 0x00 "TIM6,Timing Register 6" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x38++0x03 line.long 0x00 "TIM6,Timing Register 6" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif if (((d.l(ad:0x4003F000+0x3C-0x20))&0x2020)==0x0) group.long 0x3C++0x03 line.long 0x00 "TIM7,Timing Register 7" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x3C-0x20))&0x2020)==0x2000) group.long 0x3C++0x03 line.long 0x00 "TIM7,Timing Register 7" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" elif (((d.l(ad:0x4003F000+0x3C-0x20))&0x2020)==0x0020) group.long 0x3C++0x03 line.long 0x00 "TIM7,Timing Register 7" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 8.--11. " FRADC ,First Read Address Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else group.long 0x3C++0x03 line.long 0x00 "TIM7,Timing Register 7" bitfld.long 0x00 28.--31. " WIDLC ,Write Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 24.--27. " WWEC ,Write Enable Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 20.--23. " WADC ,Write Address Setup cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,?..." bitfld.long 0x00 16.--19. " WACC ,Write Access Cycle" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x00 12.--15. " RIDLC ,Read Idle Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " RADC ,Read Address Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " RACC ,Read Access Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif textline "" group.long 0x40++0x03 line.long 0x00 "AREA0,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x44++0x03 line.long 0x00 "AREA1,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x48++0x03 line.long 0x00 "AREA2,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x4C++0x03 line.long 0x00 "AREA3,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x50++0x03 line.long 0x00 "AREA4,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x54++0x03 line.long 0x00 "AREA5,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x58++0x03 line.long 0x00 "AREA6,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" group.long 0x5C++0x03 line.long 0x00 "AREA7,Area Register" bitfld.long 0x00 22. " MASK ,These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 21. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 20. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 19. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 18. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 17. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 16. ",These bits set the value to mask the value set in ADDR" "0,1" bitfld.long 0x00 7. " ADDR ,These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 6. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 5. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 4. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 3. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 2. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 1. ",These bits specify the address to set the corresponding MCSX area" "0,1" bitfld.long 0x00 0. ",These bits specify the address to set the corresponding MCSX area" "0,1" sif ((cpu()!="MB9AF105NA")&&(cpu()!="MB9AF105RA")) if (((d.l(ad:0x4003F000+0x60-0x60))&0x100)==0x100) group.long 0x60++0x03 line.long 0x00 "ATIM0,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x60++0x03 hide.long 0x00 "ATIM0,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x64-0x60))&0x100)==0x100) group.long 0x64++0x03 line.long 0x00 "ATIM1,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x64++0x03 hide.long 0x00 "ATIM1,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x68-0x60))&0x100)==0x100) group.long 0x68++0x03 line.long 0x00 "ATIM2,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x68++0x03 hide.long 0x00 "ATIM2,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x6C-0x60))&0x100)==0x100) group.long 0x6C++0x03 line.long 0x00 "ATIM3,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x6C++0x03 hide.long 0x00 "ATIM3,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x70-0x60))&0x100)==0x100) group.long 0x70++0x03 line.long 0x00 "ATIM4,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x70++0x03 hide.long 0x00 "ATIM4,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x74-0x60))&0x100)==0x100) group.long 0x74++0x03 line.long 0x00 "ATIM5,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x74++0x03 hide.long 0x00 "ATIM5,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x78-0x60))&0x100)==0x100) group.long 0x78++0x03 line.long 0x00 "ATIM6,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x78++0x03 hide.long 0x00 "ATIM6,ALE Timing Register" endif if (((d.l(ad:0x4003F000+0x7C-0x60))&0x100)==0x100) group.long 0x7C++0x03 line.long 0x00 "ATIM7,ALE Timing Register" bitfld.long 0x00 8.--11. " ALEW ,Address Latch Enable Width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 4.--7. " ALES ,Address Latch Enable Setup cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " ALC ,Address Latch Cycle" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" else hgroup.long 0x7C++0x03 hide.long 0x00 "ATIM7,ALE Timing Register" endif group.long 0x300++0x03 line.long 0x00 "DCLKR,Division Clock Register" bitfld.long 0x00 4. " MCLKON ,MCLK division value" "Fixed to 1,MDIV" bitfld.long 0x00 0.--3. " MDIV ,MCLK Division Ratio Setup" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" endif width 12. tree.end endif sif (cpuis("MB9BF?28?")||cpuis("MB9BF?29?")||cpuis("MB9AF421?")||cpuis("MB9AF121?")||cpuis("MB9BF121J")||cpuis("MB9BF1?1K")||cpuis("MB9BF12?K")||cpuis("MB9BF12?L")||cpuis("MB9BF12?M")||cpuis("MB9BF32?K")||cpuis("MB9BF32?L")||cpuis("MB9BF32?M")||cpuis("MB9BF52?K")||cpuis("MB9BF52?L")||cpuis("MB9BF52?M")||cpuis("MB9AF15?M")||cpuis("MB9AF15?N")||cpuis("MB9AF15?R")) tree "Unique ID" base ad:0x40000200 width 7. rgroup.long 0x00++0x07 line.long 0x00 "UIDR0,Unique ID Register 0" hexmask.long 0x00 4.--31. 1. " UID ,Unique ID register[27:0]" line.long 0x04 "UIDR1,Unique ID Register 1" hexmask.long.word 0x04 0.--12. 1. " UID ,Unique ID register[40:28]" width 0x0B tree.end endif textline ""