; -------------------------------------------------------------------------------- ; @Title: AT91CAP7E/AT91CAP7S450A/AT91CAP7S250A On-Chip Peripherals ; @Props: Released ; @Author: BOB ; @Changelog: 2009-04-24 BOB ; @Manufacturer: ATMEL - Atmel Corporation ; @Doc: at91cap7e_ds_pre.pdf (2008-10); at91cap7s_ds_pre.pdf (2008-10) ; @Core: ARM7TDMI ; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perat91cap7.per 12607 2020-12-01 09:20:15Z pegold $ config 16. 8. width 0x0b tree "SC (System Controller)" base ad:0xFFFFFD00 width 13. group.long 0x50++0x3 line.long 0x00 "SYSC_OSCMR,Oscillator Mode Register" bitfld.long 0x00 3. " OSC32K_SEL ,Slow clock source select" "Internal,External" bitfld.long 0x00 1. " OSC32K_XT_EN ,Enable external crystal oscillator" "No effect,Enabled" textline " " bitfld.long 0x00 0. " OSC32K_RC_EN ,Enable internal RC oscillator" "No effect,Enabled" group.long 0x60++0x4f line.long 0x0 "SYSC_GPBR1 ,General Purpose Backup Register 1 " line.long 0x4 "SYSC_GPBR2 ,General Purpose Backup Register 2 " line.long 0x8 "SYSC_GPBR3 ,General Purpose Backup Register 3 " line.long 0xC "SYSC_GPBR4 ,General Purpose Backup Register 4 " line.long 0x10 "SYSC_GPBR5 ,General Purpose Backup Register 5 " line.long 0x14 "SYSC_GPBR6 ,General Purpose Backup Register 6 " line.long 0x18 "SYSC_GPBR7 ,General Purpose Backup Register 7 " line.long 0x1C "SYSC_GPBR8 ,General Purpose Backup Register 8 " line.long 0x20 "SYSC_GPBR9 ,General Purpose Backup Register 9 " line.long 0x24 "SYSC_GPBR10,General Purpose Backup Register 10" line.long 0x28 "SYSC_GPBR11,General Purpose Backup Register 11" line.long 0x2C "SYSC_GPBR12,General Purpose Backup Register 12" line.long 0x30 "SYSC_GPBR13,General Purpose Backup Register 13" line.long 0x34 "SYSC_GPBR14,General Purpose Backup Register 14" line.long 0x38 "SYSC_GPBR15,General Purpose Backup Register 15" line.long 0x3C "SYSC_GPBR16,General Purpose Backup Register 16" line.long 0x40 "SYSC_GPBR17,General Purpose Backup Register 17" line.long 0x44 "SYSC_GPBR18,General Purpose Backup Register 18" line.long 0x48 "SYSC_GPBR19,General Purpose Backup Register 19" line.long 0x4C "SYSC_GPBR20,General Purpose Backup Register 20" width 0xb tree.end tree "RSTC (Reset Controller)" base ad:0xFFFFFD00 width 9. wgroup.long 0x00++0x03 line.long 0x00 "RSTC_CR,Control Register" hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password" bitfld.long 0x00 3. " EXTRST ,External Reset" "No effect,NRST asserted" bitfld.long 0x00 2. " PERRST ,Peripheral Reset" "No effect,Peripherals reset" textline " " bitfld.long 0x00 0. " PROCRST ,Processor Reset" "No effect,Processor reset" hgroup.long 0x04++0x03 hide.long 0x00 "RSTC_SR,Status Register" in group.long 0x08++0x03 line.long 0x00 "RSTC_MR,Mode Register" hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password" bitfld.long 0x00 8.--11. " ERSTL ,External Reset Length" "2 slow clock cycles (60 us),4 slow clock cycles (120 us),8 slow clock cycles (240 us),16 slow clock cycles (480 us),32 slow clock cycles (960 us),64 slow clock cycles (1.92 ms),128 slow clock cycles (3.84 ms),256 slow clock cycles (7.68 ms),512 slow clock cycles (15.36 ms),1024 slow clock cycles (30.72 ms),2048 slow clock cycles (61.44 ms),4096 slow clock cycles (122.88 ms),8192 slow clock cycles (245.76 ms),16384 slow clock cycles (491.52 ms),32768 slow clock cycles (0.98304 s),65536 slow clock cycles (1.96608 s)" textline " " bitfld.long 0x00 4. " URSTIEN ,User Reset Interrupt Enable" "No effect,Enabled" bitfld.long 0x00 0. " URSTEN ,User Reset Enable" "Disabled,Enabled" width 0xb tree.end tree "RTT (Real-time Timer)" base ad:0xFFFFFD20 width 0x08 group.long 0x00++0x07 line.long 0x00 "RTT_MR,Real-Time Timer Mode Register" bitfld.long 0x00 18. " RTTRST ,Real-Time Timer Restart" "Not restarted,Restarted" bitfld.long 0x00 17. " RTTINCIEN ,Real-Time Timer Increment Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 16. " ALMIEN ,Alarm Interrupt Enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-Time Timer Prescaler Value" line.long 0x04 "RTT_AR,Real-Time Timer Alarm Register" rgroup.long 0x08++0x3 line.long 0x00 "RTT_VR,Real-Time Timer Value Register" hgroup.long 0xC++0x3 hide.long 0x0 "RTT_SR,Real-Time Timer Status Register" in base vm:0x0 wgroup 0x0++0x0 width 0xB tree.end tree "PIT (Periodic Interval Timer)" base ad:0xFFFFFD30 width 0xa group.long 0x00++0x03 line.long 0x00 "PIT_MR,Periodic Interval Timer Mode Register" bitfld.long 0x00 25. " PITIEN ,Periodic Interval Timer Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 24. " PITEN ,Period Interval Timer Enable" "Disabled,Enabled" hexmask.long.tbyte 0x00 0.--19. 1. 1. " PIV ,Periodic Interval Value" rgroup.long 0x04++0x3 line.long 0x00 "PIT_SR,Periodic Interval Timer Status Register" bitfld.long 0x00 0. " PITS ,Period Interval Timer Status" "Not Reached,Reached" hgroup.long 0x8++0x3 hide.long 0x0 "PIT_PIVR,Periodic Interval Timer Value Register" in rgroup.long 0xC++0x3 line.long 0x0 "PIT_PIIR,Periodic Interval Timer Image Register" hexmask.long.word 0x0 20.--31. 1. " PICNT ,Periodic Interval Counter" hexmask.long.tbyte 0x0 0.--19. 1. " CPIV ,Current Periodic Interval Value" width 0xB tree.end tree "WDT (Watchdog Timer)" base ad:0xFFFFFD40 width 0x8 wgroup.long 0x00++0x03 line.long 0x00 "WDT_CR,Watchdog Timer Control Register" hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password" bitfld.long 0x00 0. " WDRSTT ,Watchdog Restart" "No effect,Restarted" group.long 0x04++0x03 line.long 0x00 "WDT_MR,Watchdog Timer Mode Register" bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog Idle Halt" "Started,Stopped" bitfld.long 0x00 28. " WDDBGHLT ,Watchdog Debug Halt" "Started,Stopped" hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog Delta Value" textline " " bitfld.long 0x00 15. " WDDIS ,Watchdog Disable" "Enabled,Disabled" bitfld.long 0x00 14. " WDRPROC ,Watchdog Reset Processor" "All,Processor" bitfld.long 0x00 13. " WDRSTEN ,Watchdog Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " WDFIEN ,Watchdog Fault Interrupt Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog Counter Value" hgroup.long 0x08++0x03 hide.long 0x00 "WDT_SR,Watchdog Timer Status Register" in base vm:0x0 wgroup 0x0++0x0 width 0xB tree.end tree "SHDWC (Shutdown Controller)" base ad:0xFFFFFD10 width 9. wgroup.long 0x00++0x03 line.long 0x00 "SHDW_CR,Shutdown Control Register" hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password" bitfld.long 0x00 0. " SHDW ,Shut Down Command" "No effect,SHDN asserted" group.long 0x04++0x03 line.long 0x00 "SHDW_MR,Shutdown Mode Register" bitfld.long 0x00 16. " RTTWKEN ,Real-time Timer Wake-up Enable" "Disabled,Enabled" hexmask.long.byte 0x00 4.--7. 1. " CPTWK0 ,Counter on Wake-up 0" bitfld.long 0x00 0.--1. " WKMODE0 ,Wake-up Mode 0" "None,Low to high,High to low,Both levels" hgroup.long 0x08++0x03 hide.long 0x00 "SHDW_SR,Shutdown Status Register" in width 0xb tree.end tree "Matrix" base ad:0xFFFFEE00 width 14. tree "Masters" group.long (0x00+0x0)++0x3 line.long 0x00 "MATRIX_MCFG0,Master (ARM) Configuration Register 0" bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite Length Burst,Single Access,Four Beat Burst,Eight Beat Burst,Sixteen Beat Burst,?..." group.long (0x00+0x4)++0x3 line.long 0x00 "MATRIX_MCFG1,Master (Peripheral DMA Controller) Configuration Register 1" bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite Length Burst,Single Access,Four Beat Burst,Eight Beat Burst,Sixteen Beat Burst,?..." group.long (0x00+0x8)++0x3 line.long 0x00 "MATRIX_MCFG2,Master (Master A) Configuration Register 2" bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite Length Burst,Single Access,Four Beat Burst,Eight Beat Burst,Sixteen Beat Burst,?..." group.long (0x00+0xC)++0x3 line.long 0x00 "MATRIX_MCFG3,Master (Master B) Configuration Register 3" bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite Length Burst,Single Access,Four Beat Burst,Eight Beat Burst,Sixteen Beat Burst,?..." sif (cpuis("AT91CAP7S*")) group.long (0x00+0x10)++0x3 line.long 0x00 "MATRIX_MCFG4,Master (Master C) Configuration Register 4" bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite Length Burst,Single Access,Four Beat Burst,Eight Beat Burst,Sixteen Beat Burst,?..." endif sif (cpuis("AT91CAP7S*")) group.long (0x00+0x14)++0x3 line.long 0x00 "MATRIX_MCFG5,Master (Master D) Configuration Register 5" bitfld.long 0x00 0.--2. " ULBT ,Undefined Length Burst Type" "Infinite Length Burst,Single Access,Four Beat Burst,Eight Beat Burst,Sixteen Beat Burst,?..." endif tree.end tree "Slave 0 (Internal SRAM 96 Kbytes)" if ((d.l(ad:0xFFFFEE00+0x40+0x0)&0x30000)==0x20000) group.long (0x40+0x0)++0x3 line.long 0x00 "MATRIX_SCFG0,Slave Configuration Register 0" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x0)++0x3 line.long 0x00 "MATRIX_SCFG0,Slave Configuration Register 0" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x0)++0x7 line.long 0x00 "MATRIX_PRAS0,Priority Register A for Slave 0" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS0,Priority Register B for Slave 0" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 1 (Internal SRAM 64 Kbytes)" if ((d.l(ad:0xFFFFEE00+0x40+0x8)&0x30000)==0x20000) group.long (0x40+0x8)++0x3 line.long 0x00 "MATRIX_SCFG1,Slave Configuration Register 1" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x8)++0x3 line.long 0x00 "MATRIX_SCFG1,Slave Configuration Register 1" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x8)++0x7 line.long 0x00 "MATRIX_PRAS1,Priority Register A for Slave 1" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS1,Priority Register B for Slave 1" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 2 (Internal ROM 256 Kbytes)" if ((d.l(ad:0xFFFFEE00+0x40+0x10)&0x30000)==0x20000) group.long (0x40+0x10)++0x3 line.long 0x00 "MATRIX_SCFG2,Slave Configuration Register 2" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x10)++0x3 line.long 0x00 "MATRIX_SCFG2,Slave Configuration Register 2" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x10)++0x7 line.long 0x00 "MATRIX_PRAS2,Priority Register A for Slave 2" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS2,Priority Register B for Slave 2" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 3 (Slave A)" if ((d.l(ad:0xFFFFEE00+0x40+0x18)&0x30000)==0x20000) group.long (0x40+0x18)++0x3 line.long 0x00 "MATRIX_SCFG3,Slave Configuration Register 3" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x18)++0x3 line.long 0x00 "MATRIX_SCFG3,Slave Configuration Register 3" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x18)++0x7 line.long 0x00 "MATRIX_PRAS3,Priority Register A for Slave 3" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS3,Priority Register B for Slave 3" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 4 (Slave B)" if ((d.l(ad:0xFFFFEE00+0x40+0x20)&0x30000)==0x20000) group.long (0x40+0x20)++0x3 line.long 0x00 "MATRIX_SCFG4,Slave Configuration Register 4" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x20)++0x3 line.long 0x00 "MATRIX_SCFG4,Slave Configuration Register 4" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x20)++0x7 line.long 0x00 "MATRIX_PRAS4,Priority Register A for Slave 4" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS4,Priority Register B for Slave 4" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 5 (Slave C)" if ((d.l(ad:0xFFFFEE00+0x40+0x28)&0x30000)==0x20000) group.long (0x40+0x28)++0x3 line.long 0x00 "MATRIX_SCFG5,Slave Configuration Register 5" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x28)++0x3 line.long 0x00 "MATRIX_SCFG5,Slave Configuration Register 5" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x28)++0x7 line.long 0x00 "MATRIX_PRAS5,Priority Register A for Slave 5" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS5,Priority Register B for Slave 5" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 6 (Slave D)" if ((d.l(ad:0xFFFFEE00+0x40+0x30)&0x30000)==0x20000) group.long (0x40+0x30)++0x3 line.long 0x00 "MATRIX_SCFG6,Slave Configuration Register 6" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x30)++0x3 line.long 0x00 "MATRIX_SCFG6,Slave Configuration Register 6" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x30)++0x7 line.long 0x00 "MATRIX_PRAS6,Priority Register A for Slave 6" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS6,Priority Register B for Slave 6" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end sif (cpuis("AT91CAP7S*")) tree "Slave 7 (MP Block Slave for ARM control of AHB masters)" if ((d.l(ad:0xFFFFEE00+0x40+0x38)&0x30000)==0x20000) group.long (0x40+0x38)++0x3 line.long 0x00 "MATRIX_SCFG7,Slave Configuration Register 7" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x38)++0x3 line.long 0x00 "MATRIX_SCFG7,Slave Configuration Register 7" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x38)++0x7 line.long 0x00 "MATRIX_PRAS7,Priority Register A for Slave 7" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS7,Priority Register B for Slave 7" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end endif tree "Slave 8 (External Bus Interface)" if ((d.l(ad:0xFFFFEE00+0x40+0x40)&0x30000)==0x20000) group.long (0x40+0x40)++0x3 line.long 0x00 "MATRIX_SCFG8,Slave Configuration Register 8" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x40)++0x3 line.long 0x00 "MATRIX_SCFG8,Slave Configuration Register 8" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x40)++0x7 line.long 0x00 "MATRIX_PRAS8,Priority Register A for Slave 8" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS8,Priority Register B for Slave 8" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Slave 9 (Peripheral Bridge)" if ((d.l(ad:0xFFFFEE00+0x40+0x48)&0x30000)==0x20000) group.long (0x40+0x48)++0x3 line.long 0x00 "MATRIX_SCFG9,Slave Configuration Register 9" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Fixed Default Master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" else group.long (0x40+0x48)++0x3 line.long 0x00 "MATRIX_SCFG9,Slave Configuration Register 9" bitfld.long 0x00 24.--25. " ARBT ,Arbitration Type" "Round-Robin,Fixed Priority,?..." bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default Master Type" "None,Last,Fixed,?..." textline " " hexmask.long.byte 0x00 0.--7. 1. " SLOT_CYCLE ,Maximum Number of Allowed Cycles for a Burst" endif group.long (0x80+0x48)++0x7 line.long 0x00 "MATRIX_PRAS9,Priority Register A for Slave 9" bitfld.long 0x00 28.--29. " M7PR ,Master 7 Priority" "0,1,2,3" bitfld.long 0x00 24.--25. " M6PR ,Master 6 Priority" "0,1,2,3" bitfld.long 0x00 20.--21. " M5PR ,Master 5 Priority" "0,1,2,3" bitfld.long 0x00 16.--17. " M4PR ,Master 4 Priority" "0,1,2,3" bitfld.long 0x00 12.--13. " M3PR ,Master 3 Priority" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " M2PR ,Master 2 Priority" "0,1,2,3" bitfld.long 0x00 4.--5. " M1PR ,Master 1 Priority" "0,1,2,3" bitfld.long 0x00 0.--1. " M0PR ,Master 0 Priority" "0,1,2,3" line.long 0x04 "MATRIX_PRBS9,Priority Register B for Slave 9" bitfld.long 0x04 28.--29. " M15PR ,Master 15 Priority" "0,1,2,3" bitfld.long 0x04 24.--25. " M14PR ,Master 14 Priority" "0,1,2,3" bitfld.long 0x04 20.--21. " M13PR ,Master 13 Priority" "0,1,2,3" bitfld.long 0x04 16.--17. " M12PR ,Master 12 Priority" "0,1,2,3" bitfld.long 0x04 12.--13. " M11PR ,Master 11 Priority" "0,1,2,3" textline " " bitfld.long 0x04 8.--9. " M10PR ,Master 10 Priority" "0,1,2,3" bitfld.long 0x04 4.--5. " M9PR ,Master 9 Priority" "0,1,2,3" bitfld.long 0x04 0.--1. " M8PR ,Master 8 Priority" "0,1,2,3" tree.end tree "Common" group.long 0x100++0x3 line.long 0x00 "MATRIX_MRCR,Master Remap Control Register" bitfld.long 0x00 5. " RCB5 ,Remapped address decoding for Master 5" "Disabled,Enabled" bitfld.long 0x00 4. " RCB4 ,Remapped address decoding for Master 4" "Disabled,Enabled" bitfld.long 0x00 3. " RCB3 ,Remapped address decoding for Master 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RCB2 ,Remapped address decoding for Master 2" "Disabled,Enabled" bitfld.long 0x00 1. " RCB1 ,Remapped address decoding for Master 1" "Disabled,Enabled" bitfld.long 0x00 0. " RCB0 ,Remapped address decoding for Master 0" "Disabled,Enabled" group.long 0x130++0x7 line.long 0x00 "MATRIX_EBICSA,EBI Chip Select Assignment Register" bitfld.long 0x00 8. " EBI_DBPUC ,EBI Data Bus Pull-Up Configuration" "Pulled-up,Not pulled-up" textline " " bitfld.long 0x00 5. " EBI_CS5A ,EBI Chip Select 5 Assignment" "SMC/EBI_NCS5 defined by SMC,SMC/CompactFlash2 Activated" textline " " bitfld.long 0x00 4. " EBI_CS4A ,EBI Chip Select 4 Assignment" "SMC/EBI_NCS4 defined by SMC,SMC/CompactFlash1 Activated" textline " " bitfld.long 0x00 3. " EBI_CS3A ,EBI Chip Select 3 Assignment" "SMC/EBI_NCS3 defined by SMC,SMC/SmartMedia Activated" textline " " bitfld.long 0x00 1. " EBI_CS1A ,EBI Chip Select 1 Assignment" "SMC,SDRAM" line.long 0x04 "MATRIX_USBPCR,USB Pull-up Control Register" bitfld.long 0x04 31. " PUP_IDLE ,Pull-up Idle" "Higher resistance,Lower resistance" bitfld.long 0x04 30. " UDP_PUP_ON ,UDP Pad Pull-up Enable" "Disabled,Enabled" tree.end width 0xb tree.end tree "SMC (Static Memory Controller)" base ad:0xFFFFEC00 width 0xC tree "CS0" group.long 0x0++0xB line.long 0x00 "SMC_SETUP0,SMC Setup Register 0" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE0,SMC Pulse Register 0" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE0,SMC Cycle Register 0" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x0+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x0+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x0+0xc)++0x3 line.long 0x00 "SMC_MODE0,SMC Mode Register 0" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x0+0xc)))&0x1000000)==0x1000000) group.long (0x0+0xc)++0x3 line.long 0x00 "SMC_MODE0,SMC Mode Register 0" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x0+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x0+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x0+0xc)++0x3 line.long 0x00 "SMC_MODE0,SMC Mode Register 0" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x0+0xc)++0x3 line.long 0x00 "SMC_MODE0,SMC Mode Register 0" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS1" group.long 0x10++0xB line.long 0x00 "SMC_SETUP1,SMC Setup Register 1" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE1,SMC Pulse Register 1" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE1,SMC Cycle Register 1" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x10+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x10+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x10+0xc)++0x3 line.long 0x00 "SMC_MODE1,SMC Mode Register 1" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x10+0xc)))&0x1000000)==0x1000000) group.long (0x10+0xc)++0x3 line.long 0x00 "SMC_MODE1,SMC Mode Register 1" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x10+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x10+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x10+0xc)++0x3 line.long 0x00 "SMC_MODE1,SMC Mode Register 1" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x10+0xc)++0x3 line.long 0x00 "SMC_MODE1,SMC Mode Register 1" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS2" group.long 0x20++0xB line.long 0x00 "SMC_SETUP2,SMC Setup Register 2" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE2,SMC Pulse Register 2" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE2,SMC Cycle Register 2" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x20+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x20+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x20+0xc)++0x3 line.long 0x00 "SMC_MODE2,SMC Mode Register 2" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x20+0xc)))&0x1000000)==0x1000000) group.long (0x20+0xc)++0x3 line.long 0x00 "SMC_MODE2,SMC Mode Register 2" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x20+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x20+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x20+0xc)++0x3 line.long 0x00 "SMC_MODE2,SMC Mode Register 2" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x20+0xc)++0x3 line.long 0x00 "SMC_MODE2,SMC Mode Register 2" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS3" group.long 0x30++0xB line.long 0x00 "SMC_SETUP3,SMC Setup Register 3" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE3,SMC Pulse Register 3" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE3,SMC Cycle Register 3" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x30+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x30+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x30+0xc)++0x3 line.long 0x00 "SMC_MODE3,SMC Mode Register 3" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x30+0xc)))&0x1000000)==0x1000000) group.long (0x30+0xc)++0x3 line.long 0x00 "SMC_MODE3,SMC Mode Register 3" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x30+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x30+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x30+0xc)++0x3 line.long 0x00 "SMC_MODE3,SMC Mode Register 3" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x30+0xc)++0x3 line.long 0x00 "SMC_MODE3,SMC Mode Register 3" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS4" group.long 0x40++0xB line.long 0x00 "SMC_SETUP4,SMC Setup Register 4" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE4,SMC Pulse Register 4" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE4,SMC Cycle Register 4" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x40+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x40+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x40+0xc)++0x3 line.long 0x00 "SMC_MODE4,SMC Mode Register 4" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x40+0xc)))&0x1000000)==0x1000000) group.long (0x40+0xc)++0x3 line.long 0x00 "SMC_MODE4,SMC Mode Register 4" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x40+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x40+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x40+0xc)++0x3 line.long 0x00 "SMC_MODE4,SMC Mode Register 4" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x40+0xc)++0x3 line.long 0x00 "SMC_MODE4,SMC Mode Register 4" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS5" group.long 0x50++0xB line.long 0x00 "SMC_SETUP5,SMC Setup Register 5" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE5,SMC Pulse Register 5" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE5,SMC Cycle Register 5" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x50+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x50+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x50+0xc)++0x3 line.long 0x00 "SMC_MODE5,SMC Mode Register 5" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x50+0xc)))&0x1000000)==0x1000000) group.long (0x50+0xc)++0x3 line.long 0x00 "SMC_MODE5,SMC Mode Register 5" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x50+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x50+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x50+0xc)++0x3 line.long 0x00 "SMC_MODE5,SMC Mode Register 5" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x50+0xc)++0x3 line.long 0x00 "SMC_MODE5,SMC Mode Register 5" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS6" group.long 0x60++0xB line.long 0x00 "SMC_SETUP6,SMC Setup Register 6" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE6,SMC Pulse Register 6" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE6,SMC Cycle Register 6" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x60+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x60+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x60+0xc)++0x3 line.long 0x00 "SMC_MODE6,SMC Mode Register 6" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x60+0xc)))&0x1000000)==0x1000000) group.long (0x60+0xc)++0x3 line.long 0x00 "SMC_MODE6,SMC Mode Register 6" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x60+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x60+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x60+0xc)++0x3 line.long 0x00 "SMC_MODE6,SMC Mode Register 6" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x60+0xc)++0x3 line.long 0x00 "SMC_MODE6,SMC Mode Register 6" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end tree "CS7" group.long 0x70++0xB line.long 0x00 "SMC_SETUP7,SMC Setup Register 7" hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS Setup Length in Read Access" hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD Setup Length" hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS Setup Length in Write Access" textline " " hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE Setup Length" line.long 0x4 "SMC_PULSE7,SMC Pulse Register 7" hexmask.long.byte 0x4 24.--30. 1. " NCS_RD_PULSE ,NCS Pulse Length in Read Access" hexmask.long.byte 0x4 16.--22. 1. " NRD_PULSE ,NRD Pulse Length" hexmask.long.byte 0x4 8.--14. 1. " NCS_WR_PULSE ,NCS Pulse Length in Write Access" textline " " hexmask.long.byte 0x4 0.--6. 1. " NWE_PULSE ,NWE Pulse Length" line.long 0x8 "SMC_CYCLE7,SMC Cycle Register 7" hexmask.long.word 0x8 16.--24. 1. " NRD_CYCLE ,Total Read Cycle Length" hexmask.long.word 0x8 0.--8. 1. " NWE_CYCLE ,Total Write Cycle Length" if ((((d.l(ad:(0xFFFFEC00+0x70+0xc)))&0x1000000)==0x1000000)&&(((d.l(ad:(0xFFFFEC00+0x70+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x70+0xc)++0x3 line.long 0x00 "SMC_MODE7,SMC Mode Register 7" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" textline " " bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif (((d.l(ad:(0xFFFFEC00+0x70+0xc)))&0x1000000)==0x1000000) group.long (0x70+0xc)++0x3 line.long 0x00 "SMC_MODE7,SMC Mode Register 7" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " PS ,Page Size" "4-byte,8-byte,16-byte,32-byte" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" elif ((((d.l(ad:(0xFFFFEC00+0x70+0xc)))&0x1000000)==0x0000000)&&(((d.l(ad:(0xFFFFEC00+0x70+0xC)))&0x3000)==(0x1000||0x2000))) group.long (0x70+0xc)++0x3 line.long 0x00 "SMC_MODE7,SMC Mode Register 7" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 8. " BAT ,Byte Access Type" "Select,Write" bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" textline " " bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" else group.long (0x70+0xc)++0x3 line.long 0x00 "SMC_MODE7,SMC Mode Register 7" bitfld.long 0x00 24. " PMEN ,Page Mode Enable" "Disabled,Enabled" bitfld.long 0x00 20. " TDF_MODE ,TDF Optimization" "Disabled,Enabled" bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data Float Time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" textline " " bitfld.long 0x00 12.--13. " DBW ,Data Bus Width" "8-bit,16-bit,32-bit,?..." bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT Mode" "Disabled,Reserved,Frozen,Ready" bitfld.long 0x00 1. " WRITE_MODE ,Write Mode" "NCS,NWE" textline " " bitfld.long 0x00 0. " READ_MODE ,Read Mode" "NCS,NRD" endif tree.end width 0xb tree.end tree "SDRAMC (SDRAM Controller)" base ad:0xFFFFEA00 width 12. group.long 0x00++0x13 line.long 0x00 "SDRAMC_MR,SDRAMC Mode Register" bitfld.long 0x00 0.--2. " MODE ,SDRAMC Command Mode" "Normal,NOP,All Banks Precharge,Load Mode Register,Auto-Refresh,Extended Load Mode Register,Deep Power-Down,?..." line.long 0x04 "SDRAMC_TR,SDRAMC Refresh Timer Register" hexmask.long.word 0x04 0.--11. 1. " COUNT ,SDRAMC Refresh Timer Count" line.long 0x08 "SDRAMC_CR,SDRAMC Configuration Register" bitfld.long 0x08 28.--31. " TXSR ,Exit Self Refresh to Active Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " TRAS ,Active to Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 20.--23. " TRCD ,Row to Column Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 16.--19. " TRP ,Row Precharge Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 12.--15. " TRC ,Row Cycle Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 8.--11. " TWR ,Write Recovery Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 7. " DBW ,Data Bus Width" "32 bits,16 bits" bitfld.long 0x08 5.--6. " CAS ,CAS Latency" "Reserved,1,2,3" bitfld.long 0x08 4. " NB ,Number of Banks" "2,4" textline " " bitfld.long 0x08 2.--3. " NR ,Number of Row Bits" "11,12,13,?..." bitfld.long 0x08 0.--1. " NC ,Number of Column Bits" "8,9,10,11" line.long 0x0C "SDRAMC_HSR,SDRAM High Speed Register" bitfld.long 0x0C 0. " DA ,Decode Cycle Enable" "Disabled,Enabled" line.long 0x10 "SDRAMC_LPR, SDRAMC Low Power Register" bitfld.long 0x10 12.--13. " TIMEOUT ,Time when low-power mode is enabled after the end of the last transfer" "Immediately,64 clock cycles,128 clock cycles,?..." bitfld.long 0x10 10.--11. " DS ,Drive Strength" "0,1,2,3" bitfld.long 0x10 8.--9. " TCSR ,Temperature Compensated Self-Refresh" "0,1,2,3" textline " " bitfld.long 0x10 4.--6. " PASR ,Partial Array Self-Refresh" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--1. " LPCB ,Low-power Configuration" "Disabled,Self-refresh,Power-down,Deep Power-down" group.long 0x1C++0x03 line.long 0x00 "SDRAMC_IMR,SDRAMC Interrupt Mask Register" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RES_set/clr ,Refresh Error Status" "Disabled,Enabled" hgroup.long 0x20++0x3 hide.long 0x00 "SDRAMC_ISR,SDRAMC Interrupt Status Register" in group.long 0x24++0x03 line.long 0x00 "SDRAMC_MDR,SDRAMC Memory Device Register" bitfld.long 0x00 0.--1. " MD ,Memory Device Type" "SDRAM,Low-power SDRAM,?..." width 0xb tree.end tree "PMC (Power Management Controller)" base ad:0xFFFFFC00 width 12. group.long 0x08++0x03 line.long 0x00 "PMC_SCSR,PMC System Clock Status Register" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PCK3_set/clr ,Programmable Clock 3 Output Status" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PCK2_set/clr ,Programmable Clock 2 Output Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " PCK1_set/clr ,Programmable Clock 1 Output Status" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " PCK0_set/clr ,Programmable Clock 0 Output Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UDP_set/clr ,USB Device Port Clock Status" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " UHP_set/clr ,USB Host Port Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " PCK_set/clr ,Processor Clock Status" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "PMC_PCSR,PMC Peripheral Clock Status Register" sif (cpuis("AT91CAP7S*")) setclrfld.long 0x00 29. -0x08 29. -0x04 29. " FPMD_set/clr ,FPGA Master D (HCK3) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " FPMC_set/clr ,FPGA Master C (HCK2) Clock Status" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 27. -0x08 27. -0x04 27. " FPMB_set/clr ,FPGA Master B (HCK1) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " FPMA_set/clr ,FPGA Master A (HCK0) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " FPP13_set/clr ,FPGA Peripheral 13 (PID25) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " FPP12_set/clr ,FPGA Peripheral 12 (PID24) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " FPP11_set/clr ,FPGA Peripheral 11 (PID23) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " FPP10_set/clr ,FPGA Peripheral 10 (PID22) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " FPP9_set/clr ,FPGA Peripheral 9 (PID21) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " FPP8_set/clr ,FPGA Peripheral 8 (PID20) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " FPP7_set/clr ,FPGA Peripheral 7 (PID19) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " FPP6_set/clr ,FPGA Peripheral 6 (PID18) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " FPP5_set/clr ,FPGA Peripheral 5 (PID17) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " FPP4_set/clr ,FPGA Peripheral 4 (PID16) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " FPP3_set/clr ,FPGA Peripheral 3 (PID15) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " FPP2_set/clr ,FPGA Peripheral 2 (PID14) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " FPP1_set/clr ,FPGA Peripheral 1 (PID13) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " FPP0_set/clr ,FPGA Peripheral 0 (PID12) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " ADC_set/clr ,Analog to Digital Converter (PID11) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UDP_set/clr ,USB Device Port (PID10) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TC2_set/clr ,Timer/Counter 2 (PID9) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TC1_set/clr ,Timer/Counter 1 (PID8) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TC0_set/clr ,Timer/Counter 0 (PID7) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " SPI0_set/clr ,Serial Peripheral Interface 0 (PID6) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " US1_set/clr ,USART 1 (PID5) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " US0_set/clr ,USART 0 (PID4) Clock Status" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " PIOB_set/clr ,Parallel I/O Controller B (PID3) Clock Status" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " PIOA_set/clr ,Parallel I/O Controller A (PID2) Clock Status" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "CKGR_MOR,PMC Clock Generator Main Oscillator Register" hexmask.long.byte 0x00 8.--15. 1. " OSCOUNT ,Main Oscillator Start-Up Time" bitfld.long 0x00 1. " OSCBYPASS ,Oscillator Bypass" "No effect,Bypassed" textline " " bitfld.long 0x00 0. " MOSCEN ,Main Oscillator Enable" "Disabled,Enabled" rgroup.long 0x24++0x03 line.long 0x00 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register" bitfld.long 0x00 16. " MAINRDY ,Main Clock Ready" "Not ready,Ready" hexmask.long.word 0x00 0.--15. 1. " MAINF ,Main Clock Frequency" group.long 0x28++0xB line.long 0x00 "CKGR_PLLAR,PMC Clock Generator PLL A Register" hexmask.long.word 0x00 16.--26. 1. " MULA ,PLL A Multiplier" bitfld.long 0x00 14.--15. " OUTA ,PLL A Clock Frequency Range" "0,1,2,3" textline " " bitfld.long 0x00 8.--13. " PLLACOUNT ,PLL A Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 0.--7. 1. " DIVA ,Divider A" line.long 0x04 "CKGR_PLLBR,PMC Clock Generator PLL A Register" bitfld.long 0x04 28.--29. " USBDIV ,Divider for USB Clock" "PLL_B Clock,PLL_B/2,PLL_B/4,?..." hexmask.long.word 0x04 16.--26. 1. " MULB ,PLL B Multiplier" textline " " bitfld.long 0x04 14.--15. " OUTB ,PLL B Clock Frequency Range" "0,1,2,3" bitfld.long 0x04 8.--13. " PLLBCOUNT ,PLL B Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x04 0.--7. 1. " DIVB ,Divider B" line.long 0x08 "PMC_MCKR,PMC Master Clock Register" bitfld.long 0x08 2.--4. " PRES ,Processor Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x08 0.--1. " CSS ,Master Clock Selection" "Slow,Main,PLL_A,PLL_B" group.long 0x40++0x1F line.long 0x0 "PMC_PCK0,PMC Programmable Clock 0 Register" bitfld.long 0x0 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x0 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0x4 "PMC_PCK1,PMC Programmable Clock 1 Register" bitfld.long 0x4 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x4 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0x8 "PMC_PCK2,PMC Programmable Clock 2 Register" bitfld.long 0x8 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x8 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0xC "PMC_PCK3,PMC Programmable Clock 3 Register" bitfld.long 0xC 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0xC 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0x10 "PMC_PCK4,PMC Programmable Clock 4 Register" bitfld.long 0x10 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x10 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0x14 "PMC_PCK5,PMC Programmable Clock 5 Register" bitfld.long 0x14 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x14 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0x18 "PMC_PCK6,PMC Programmable Clock 6 Register" bitfld.long 0x18 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x18 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" line.long 0x1C "PMC_PCK7,PMC Programmable Clock 7 Register" bitfld.long 0x1C 2.--4. " PRES ,Programmable Clock Prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,?..." bitfld.long 0x1C 0.--1. " CSS ,Programmable Clock Selection" "Slow,Main,PLL_A,PLL_B" group.long 0x6c++0x3 line.long 0x0 "PMC_IMR,PMC Interrupt Mask Register" setclrfld.long 0x0 11. -0xc 11. -0x8 11. " PCKRDY3_set/clr ,Programmable Clock Ready 3 Interrupt Mask" "Enabled,Disabled" setclrfld.long 0x0 10. -0xc 10. -0x8 10. " PCKRDY2_set/clr ,Programmable Clock Ready 2 Interrupt Mask" "Enabled,Disabled" textline " " setclrfld.long 0x0 09. -0xc 9. -0x8 9. " PCKRDY1_set/clr ,Programmable Clock Ready 1 Interrupt Mask" "Enabled,Disabled" setclrfld.long 0x0 08. -0xc 8. -0x8 8. " PCKRDY0_set/clr ,Programmable Clock Ready 0 Interrupt Mask" "Enabled,Disabled" textline " " setclrfld.long 0x0 03. -0xc 3. -0x8 3. " MCKRDY_set/clr ,Master Clock Ready Interrupt Mask" "Enabled,Disabled" setclrfld.long 0x0 02. -0xc 2. -0x8 2. " LOCKB_set/clr ,PLL B Lock Interrupt Mask" "Enabled,Disabled" textline " " setclrfld.long 0x0 01. -0xc 1. -0x8 1. " LOCKA_set/clr ,PLL A Lock Interrupt Mask" "Enabled,Disabled" setclrfld.long 0x0 00. -0xc 0. -0x8 0. " MOSCS_set/clr ,Main Oscillator Status Interrupt Mask" "Enabled,Disabled" rgroup.long 0x68++0x3 line.long 0x0 "PMC_SR,PMC Status Register" bitfld.long 0x0 11. " PCKRDY3 ,Programmable Clock Ready 3 Status" "Not ready,Ready" bitfld.long 0x0 10. " PCKRDY2 ,Programmable Clock Ready 2 Status" "Not ready,Ready" textline " " bitfld.long 0x0 09. " PCKRDY1 ,Programmable Clock Ready 1 Status" "Not ready,Ready" bitfld.long 0x0 08. " PCKRDY0 ,Programmable Clock Ready 0 Status" "Not ready,Ready" textline " " bitfld.long 0x0 07. " OSC_SEL ,Slow Clock Oscillator Selection" "Internal,External" bitfld.long 0x0 03. " MCKRDY ,Master Clock Status" "Not ready,Ready" textline " " bitfld.long 0x0 02. " LOCKB ,PLL B Lock Status" "Not locked,Locked" bitfld.long 0x0 01. " LOCKA ,PLL A Lock Status" "Not locked,Locked" textline " " bitfld.long 0x0 00. " MOSCS ,MOSCS Flag Status" "Not stabilized,Stabilized" tree.end tree "AIC (Advanced Interrupt Controller)" base ad:0xFFFFF000 width 11. tree "Source Mode Registers" group.long 0x00++0x3 line.long 0x0 "AIC_SMR0,AIC Source Mode Register 0" bitfld.long 0x0 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" group.long 0x4++0x7B line.long 0x0 "AIC_SMR1 ,AIC Source Mode Register 1 " bitfld.long 0x0 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x0 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x4 "AIC_SMR2 ,AIC Source Mode Register 2 " bitfld.long 0x4 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x4 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x8 "AIC_SMR3 ,AIC Source Mode Register 3 " bitfld.long 0x8 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x8 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0xC "AIC_SMR4 ,AIC Source Mode Register 4 " bitfld.long 0xC 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0xC 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x10 "AIC_SMR5 ,AIC Source Mode Register 5 " bitfld.long 0x10 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x10 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x14 "AIC_SMR6 ,AIC Source Mode Register 6 " bitfld.long 0x14 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x14 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x18 "AIC_SMR7 ,AIC Source Mode Register 7 " bitfld.long 0x18 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x18 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x1C "AIC_SMR8 ,AIC Source Mode Register 8 " bitfld.long 0x1C 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x1C 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x20 "AIC_SMR9 ,AIC Source Mode Register 9 " bitfld.long 0x20 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x20 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x24 "AIC_SMR10,AIC Source Mode Register 10" bitfld.long 0x24 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x24 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x28 "AIC_SMR11,AIC Source Mode Register 11" bitfld.long 0x28 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x28 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x2C "AIC_SMR12,AIC Source Mode Register 12" bitfld.long 0x2C 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x2C 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x30 "AIC_SMR13,AIC Source Mode Register 13" bitfld.long 0x30 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x30 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x34 "AIC_SMR14,AIC Source Mode Register 14" bitfld.long 0x34 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x34 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x38 "AIC_SMR15,AIC Source Mode Register 15" bitfld.long 0x38 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x38 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x3C "AIC_SMR16,AIC Source Mode Register 16" bitfld.long 0x3C 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x3C 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x40 "AIC_SMR17,AIC Source Mode Register 17" bitfld.long 0x40 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x40 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x44 "AIC_SMR18,AIC Source Mode Register 18" bitfld.long 0x44 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x44 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x48 "AIC_SMR19,AIC Source Mode Register 19" bitfld.long 0x48 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x48 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x4C "AIC_SMR20,AIC Source Mode Register 20" bitfld.long 0x4C 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x4C 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x50 "AIC_SMR21,AIC Source Mode Register 21" bitfld.long 0x50 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x50 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x54 "AIC_SMR22,AIC Source Mode Register 22" bitfld.long 0x54 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x54 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x58 "AIC_SMR23,AIC Source Mode Register 23" bitfld.long 0x58 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x58 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x5C "AIC_SMR24,AIC Source Mode Register 24" bitfld.long 0x5C 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x5C 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x60 "AIC_SMR25,AIC Source Mode Register 25" bitfld.long 0x60 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x60 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x64 "AIC_SMR26,AIC Source Mode Register 26" bitfld.long 0x64 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x64 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x68 "AIC_SMR27,AIC Source Mode Register 27" bitfld.long 0x68 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x68 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x6C "AIC_SMR28,AIC Source Mode Register 28" bitfld.long 0x6C 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x6C 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x70 "AIC_SMR29,AIC Source Mode Register 29" bitfld.long 0x70 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x70 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x74 "AIC_SMR30,AIC Source Mode Register 30" bitfld.long 0x74 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x74 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" line.long 0x78 "AIC_SMR31,AIC Source Mode Register 31" bitfld.long 0x78 05.--06. " SRCTYPE ,Internal/External Interrupt Source Type" "High/low,Positive/negative,High,Positive" bitfld.long 0x78 00.--02. " PRIOR ,Priority Level" "0,1,2,3,4,5,6,7" tree.end tree "Source Vector Registers" group.long 0x80++0x7f line.long 0x0 "AIC_SVR0 ,AIC Source Vector Register 0 " line.long 0x4 "AIC_SVR1 ,AIC Source Vector Register 1 " line.long 0x8 "AIC_SVR2 ,AIC Source Vector Register 2 " line.long 0xC "AIC_SVR3 ,AIC Source Vector Register 3 " line.long 0x10 "AIC_SVR4 ,AIC Source Vector Register 4 " line.long 0x14 "AIC_SVR5 ,AIC Source Vector Register 5 " line.long 0x18 "AIC_SVR6 ,AIC Source Vector Register 6 " line.long 0x1C "AIC_SVR7 ,AIC Source Vector Register 7 " line.long 0x20 "AIC_SVR8 ,AIC Source Vector Register 8 " line.long 0x24 "AIC_SVR9 ,AIC Source Vector Register 9 " line.long 0x28 "AIC_SVR10,AIC Source Vector Register 10" line.long 0x2C "AIC_SVR11,AIC Source Vector Register 11" line.long 0x30 "AIC_SVR12,AIC Source Vector Register 12" line.long 0x34 "AIC_SVR13,AIC Source Vector Register 13" line.long 0x38 "AIC_SVR14,AIC Source Vector Register 14" line.long 0x3C "AIC_SVR15,AIC Source Vector Register 15" line.long 0x40 "AIC_SVR16,AIC Source Vector Register 16" line.long 0x44 "AIC_SVR17,AIC Source Vector Register 17" line.long 0x48 "AIC_SVR18,AIC Source Vector Register 18" line.long 0x4C "AIC_SVR19,AIC Source Vector Register 19" line.long 0x50 "AIC_SVR20,AIC Source Vector Register 20" line.long 0x54 "AIC_SVR21,AIC Source Vector Register 21" line.long 0x58 "AIC_SVR22,AIC Source Vector Register 22" line.long 0x5C "AIC_SVR23,AIC Source Vector Register 23" line.long 0x60 "AIC_SVR24,AIC Source Vector Register 24" line.long 0x64 "AIC_SVR25,AIC Source Vector Register 25" line.long 0x68 "AIC_SVR26,AIC Source Vector Register 26" line.long 0x6C "AIC_SVR27,AIC Source Vector Register 27" line.long 0x70 "AIC_SVR28,AIC Source Vector Register 28" line.long 0x74 "AIC_SVR29,AIC Source Vector Register 29" line.long 0x78 "AIC_SVR30,AIC Source Vector Register 30" line.long 0x7C "AIC_SVR31,AIC Source Vector Register 31" tree.end textline "" hgroup.long 0x100++0x3 hide.long 0x00 "AIC_IVR,AIC Interrupt Vector Register" in rgroup.long 0x104++0x7 line.long 0x0 "AIC_FVR,AIC FIQ Vector Register" line.long 0x4 "AIC_ISR,AIC Interrupt Status Register" bitfld.long 0x4 0.--4. " IRQID ,Current Interrupt Identifier" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 8,Source 9,Source 10,Source 11,Source 12,Source 13,Source 14,Source 15,Source 16,Source 17,Source 18,Source 19,Source 20,Source 21,Source 22,Source 23,Source 24,Source 25,Source 26,Source 27,Source 28,Source 29,Source 30,Source 31" group.long 0x10C++0x7 line.long 0x0 "AIC_IPR,AIC Interrupt Pending Register" setclrfld.long 0x0 31. 0x20 31. 0x1C 31. " AIC_IRQ1_set/clr ,Interrupt 31 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 30. 0x20 30. 0x1C 30. " AIC_IRQ0_set/clr ,Interrupt 30 Pending" "No interrupt,Interrupt" textline " " sif (cpuis("AT91CAP7S*")) setclrfld.long 0x0 29. 0x20 29. 0x1C 29. " FPMD_set/clr ,Interrupt 29 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 28. 0x20 28. 0x1C 28. " FPMC_set/clr ,Interrupt 28 Pending" "No interrupt,Interrupt" textline " " endif setclrfld.long 0x0 27. 0x20 27. 0x1C 27. " FPMB_set/clr ,Interrupt 27 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 26. 0x20 26. 0x1C 26. " FPMA_set/clr ,Interrupt 26 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 25. 0x20 25. 0x1C 25. " FPP13_set/clr ,Interrupt 25 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 24. 0x20 24. 0x1C 24. " FPP12_set/clr ,Interrupt 24 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 23. 0x20 23. 0x1C 23. " FPP11_set/clr ,Interrupt 23 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 22. 0x20 22. 0x1C 22. " FPP10_set/clr ,Interrupt 22 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 21. 0x20 21. 0x1C 21. " FPP9_set/clr ,Interrupt 21 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 20. 0x20 20. 0x1C 20. " FPP8_set/clr ,Interrupt 20 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 19. 0x20 19. 0x1C 19. " FPP7_set/clr ,Interrupt 19 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 18. 0x20 18. 0x1C 18. " FPP6_set/clr ,Interrupt 18 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 17. 0x20 17. 0x1C 17. " FPP5_set/clr ,Interrupt 17 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 16. 0x20 16. 0x1C 16. " FPP4_set/clr ,Interrupt 16 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 15. 0x20 15. 0x1C 15. " FPP3_set/clr ,Interrupt 15 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 14. 0x20 14. 0x1C 14. " FPP2_set/clr ,Interrupt 14 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 13. 0x20 13. 0x1C 13. " FPP1_set/clr ,Interrupt 13 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 12. 0x20 12. 0x1C 12. " FPP0_set/clr ,Interrupt 12 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 11. 0x20 11. 0x1C 11. " ADC_set/clr ,Interrupt 11 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 10. 0x20 10. 0x1C 10. " UDP_set/clr ,Interrupt 10 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 9. 0x20 9. 0x1C 9. " TC2_set/clr ,Interrupt 9 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 8. 0x20 8. 0x1C 8. " TC1_set/clr ,Interrupt 8 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 7. 0x20 7. 0x1C 7. " TC0_set/clr ,Interrupt 7 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 6. 0x20 6. 0x1C 6. " SPI0_set/clr ,Interrupt 6 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 5. 0x20 5. 0x1C 5. " US1_set/clr ,Interrupt 5 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 4. 0x20 4. 0x1C 4. " US0_set/clr ,Interrupt 4 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 3. 0x20 3. 0x1C 3. " PIOB_set/clr ,Interrupt 3 Pending" "No interrupt,Interrupt" setclrfld.long 0x0 2. 0x20 2. 0x1C 2. " PIOA_set/clr ,Interrupt 2 Pending" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 1. 0x20 1. 0x1C 1. " SYSC_set/clr ,SYS Interrupt Pending" "No interrupt,Interrupt" setclrfld.long 0x0 0. 0x20 0. 0x1C 0. " FIQ_set/clr ,FIQ Interrupt Pending" "No interrupt,Interrupt" line.long 0x4 "AIC_IMR,AIC Interrupt Mask Register" setclrfld.long 0x4 31. 0x14 31. 0x18 31. " AIC_IRQ1_set/clr ,Interrupt 31 Mask" "Disabled,Enabled" setclrfld.long 0x4 30. 0x14 30. 0x18 30. " AIC_IRQ0_set/clr ,Interrupt 30 Mask" "Disabled,Enabled" textline " " sif (cpuis("AT91CAP7S*")) setclrfld.long 0x4 29. 0x14 29. 0x18 29. " FPMD_set/clr ,Interrupt 29 Mask" "Disabled,Enabled" setclrfld.long 0x4 28. 0x14 28. 0x18 28. " FPMC_set/clr ,Interrupt 28 Mask" "Disabled,Enabled" textline " " endif setclrfld.long 0x4 27. 0x14 27. 0x18 27. " FPMB_set/clr ,Interrupt 27 Mask" "Disabled,Enabled" setclrfld.long 0x4 26. 0x14 26. 0x18 26. " FPMA_set/clr ,Interrupt 26 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 25. 0x14 25. 0x18 25. " FPP13_set/clr ,Interrupt 25 Mask" "Disabled,Enabled" setclrfld.long 0x4 24. 0x14 24. 0x18 24. " FPP12_set/clr ,Interrupt 24 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 23. 0x14 23. 0x18 23. " FPP11_set/clr ,Interrupt 23 Mask" "Disabled,Enabled" setclrfld.long 0x4 22. 0x14 22. 0x18 22. " FPP10_set/clr ,Interrupt 22 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 21. 0x14 21. 0x18 21. " FPP9_set/clr ,Interrupt 21 Mask" "Disabled,Enabled" setclrfld.long 0x4 20. 0x14 20. 0x18 20. " FPP8_set/clr ,Interrupt 20 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 19. 0x14 19. 0x18 19. " FPP7_set/clr ,Interrupt 19 Mask" "Disabled,Enabled" setclrfld.long 0x4 18. 0x14 18. 0x18 18. " FPP6_set/clr ,Interrupt 18 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 17. 0x14 17. 0x18 17. " FPP5_set/clr ,Interrupt 17 Mask" "Disabled,Enabled" setclrfld.long 0x4 16. 0x14 16. 0x18 16. " FPP4_set/clr ,Interrupt 16 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 15. 0x14 15. 0x18 15. " FPP3_set/clr ,Interrupt 15 Mask" "Disabled,Enabled" setclrfld.long 0x4 14. 0x14 14. 0x18 14. " FPP2_set/clr ,Interrupt 14 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 13. 0x14 13. 0x18 13. " FPP1_set/clr ,Interrupt 13 Mask" "Disabled,Enabled" setclrfld.long 0x4 12. 0x14 12. 0x18 12. " FPP0_set/clr ,Interrupt 12 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 11. 0x14 11. 0x18 11. " ADC_set/clr ,Interrupt 11 Mask" "Disabled,Enabled" setclrfld.long 0x4 10. 0x14 10. 0x18 10. " UDP_set/clr ,Interrupt 10 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 9. 0x14 9. 0x18 9. " TC2_set/clr ,Interrupt 9 Mask" "Disabled,Enabled" setclrfld.long 0x4 8. 0x14 8. 0x18 8. " TC1_set/clr ,Interrupt 8 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 7. 0x14 7. 0x18 7. " TC0_set/clr ,Interrupt 7 Mask" "Disabled,Enabled" setclrfld.long 0x4 6. 0x14 6. 0x18 6. " SPI0_set/clr ,Interrupt 6 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 5. 0x14 5. 0x18 5. " US1_set/clr ,Interrupt 5 Mask" "Disabled,Enabled" setclrfld.long 0x4 4. 0x14 4. 0x18 4. " US0_set/clr ,Interrupt 4 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 3. 0x14 3. 0x18 3. " PIOB_set/clr ,Interrupt 3 Mask" "Disabled,Enabled" setclrfld.long 0x4 2. 0x14 2. 0x18 2. " PIOA_set/clr ,Interrupt 2 Mask" "Disabled,Enabled" textline " " setclrfld.long 0x4 01. 0x14 1. 0x18 1. " SYSC_set/clr ,SYS Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x4 00. 0x14 0. 0x18 0. " FIQ_set/clr ,FIQ Interrupt Mask" "Disabled,Enabled" rgroup.long 0x114++0x3 line.long 0x0 "AIC_CISR,AIC Core Interrupt Status Register" bitfld.long 0x0 01. " NIRQ ,NIRQ Status" "Not activated,Activated" bitfld.long 0x0 00. " NFIQ ,NFIQ Status" "Not activated,Activated" wgroup.long 0x130++0x3 line.long 0x0 "AIC_EOICR,AIC End of Interrupt Command Register" group.long 0x134++0x07 line.long 0x00 "AIC_SPU,AIC Spurious Interrupt Vector Register" line.long 0x04 "AIC_DEBUG,AIC Debug Control Register" bitfld.long 0x04 01. " GMSK ,General Mask" "Normal,Masked" bitfld.long 0x04 00. " PROT ,Protection Mode" "Disabled,Enabled" group.long 0x148++0x03 line.long 0x00 "AIC_FFSR,AIC Fast Forcing Status Register" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " AIC_IRQ1_set/clr ,Fast Forcing Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " AIC_IRQ0_set/clr ,Fast Forcing Status 30" "Disabled,Enabled" textline " " sif (cpuis("AT91CAP7S*")) setclrfld.long 0x00 29. -0x08 29. -0x04 29. " FPMD_set/clr ,Fast Forcing Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " FPMC_set/clr ,Fast Forcing Status 28" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 27. -0x08 27. -0x04 27. " FPMB_set/clr ,Fast Forcing Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " FPMA_set/clr ,Fast Forcing Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " FPP13_set/clr ,Fast Forcing Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " FPP12_set/clr ,Fast Forcing Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " FPP11_set/clr ,Fast Forcing Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " FPP10_set/clr ,Fast Forcing Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " FPP9_set/clr ,Fast Forcing Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " FPP8_set/clr ,Fast Forcing Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " FPP7_set/clr ,Fast Forcing Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " FPP6_set/clr ,Fast Forcing Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " FPP5_set/clr ,Fast Forcing Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " FPP4_set/clr ,Fast Forcing Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " FPP3_set/clr ,Fast Forcing Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " FPP2_set/clr ,Fast Forcing Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " FPP1_set/clr ,Fast Forcing Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " FPP0_set/clr ,Fast Forcing Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " ADC_set/clr ,Fast Forcing Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UDP_set/clr ,Fast Forcing Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 09. -0x08 09. -0x04 9. " TC2_set/clr ,Fast Forcing Status 9" "Disabled,Enabled" setclrfld.long 0x00 08. -0x08 08. -0x04 8. " TC1_set/clr ,Fast Forcing Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 07. -0x08 07. -0x04 7. " TC0_set/clr ,Fast Forcing Status 7" "Disabled,Enabled" setclrfld.long 0x00 06. -0x08 06. -0x04 6. " SPI0_set/clr ,Fast Forcing Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 05. -0x08 05. -0x04 5. " US1_set/clr ,Fast Forcing Status 5" "Disabled,Enabled" setclrfld.long 0x00 04. -0x08 04. -0x04 4. " US0_set/clr ,Fast Forcing Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 03. -0x08 03. -0x04 3. " PIOB_set/clr ,Fast Forcing Status 3" "Disabled,Enabled" setclrfld.long 0x00 02. -0x08 02. -0x04 2. " PIOA_set/clr ,Fast Forcing Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 01. -0x08 01. -0x04 01. " SYSC_set/clr ,Fast Forcing Status SYS" "Disabled,Enabled" width 0xb tree.end tree "DBGU (Debug Unit)" base ad:0xFFFFF200 wgroup.long 0x00++0x03 line.long 0x00 "DBGU_CR,Debug Unit Control Register" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" textline " " bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" textline " " bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" bitfld.long 0x00 3. " RSTTX ,Reset Transmitter" "No effect,Reset" textline " " bitfld.long 0x00 2. " RSTRX ,Reset Receiver" "No effect,Reset" group.long 0x04++0x03 line.long 0x00 "DBGU_MR,Debug Unit Mode Register" bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local,Remote" bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,No parity,No parity" group.long 0x10++0x03 line.long 0x00 "DBGU_IMR,Debug Unit Interrupt Mask Register" setclrfld.long 0x00 31. -0x8 31. -0x04 31. " COMMRX_set/clr ,COMMRX Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 30. -0x8 30. -0x04 30. " COMMTX_set/clr ,COMMTX Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. -0x8 12. -0x04 12. " RXBUFF_set/clr ,RXBUFF Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 11. -0x8 11. -0x04 11. " TXBUFE_set/clr ,TXBUFE Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x8 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 7. -0x8 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. -0x8 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 5. -0x8 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. -0x8 4. -0x04 4. " ENDTX_set/clr ,End of Transmit Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 3. -0x8 3. -0x04 3. " ENDRX_set/clr ,End of Receive Transfer Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x8 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Disable" "Disabled,Enabled" setclrfld.long 0x00 0. -0x8 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled" rgroup.long 0x14++0x3 line.long 0x00 "DBGU_SR,Debug Unit Status Register" bitfld.long 0x0 31. " COMMRX ,Debug Communication Channel Read Status" "Not activated,Activated" bitfld.long 0x0 30. " COMMTX ,Debug Communication Channel Write Status" "Not activated,Activated" textline " " bitfld.long 0x0 12. " RXBUFF ,Receive Buffer Full" "Not full,Full" bitfld.long 0x0 11. " TXBUFE ,Transmission Buffer Empty" "Not empty,Empty" textline " " bitfld.long 0x0 9. " TXEMPTY ,Transmitter Empty" "Not empty,Empty" bitfld.long 0x0 7. " PARE ,Parity Error" "No error,Error" textline " " bitfld.long 0x0 6. " FRAME ,Framing Error" "No error,Error" bitfld.long 0x0 5. " OVRE ,Overrun Error" "No error,Error" textline " " bitfld.long 0x0 4. " ENDTX ,Transmitter Transfer End" "Not activated,Activated" bitfld.long 0x0 3. " ENDRX ,Receiver Transfer End" "Not activated,Activated" textline " " bitfld.long 0x0 1. " TXRDY ,Transmitter Ready" "Not ready,Ready" bitfld.long 0x0 0. " RXRDY ,Receiver Ready" "Not ready,Ready" hgroup.long 0x18++0x3 hide.long 0x0 "DBGU_RHR,Debug Unit Receiver Holding Register" in wgroup.long 0x1c++0x03 line.long 0x00 "DBGU_THR,Debug Unit Transmit Holding Register" hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to Transmit" group.long 0x20++0x03 line.long 0x00 "DBGU_BRGR,Debug Unit Baud Rate Generator Register" hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divisor" rgroup.long 0x40++0x07 line.long 0x00 "DBGU_CIDR,Debug Unit Chip ID Register" bitfld.long 0x00 31. " EXT ,Extension Flag" "Not implemented,Implemented" bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile Program Memory Type" "ROM,ROMless/flash,EFM,ROM/EFM,SRAM/ROM,?..." textline " " hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture Identifier" bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM Size" "Reserved,1-KB,2-KB,Reserved,112-KB,4-KB,80-KB,160-KB,8-KB,16-KB,32-KB,64-KB,128-KB,256-KB,96-KB,512-KB" textline " " bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second Nonvolatile Program Memory Size" "Disabled,8-KB,16-KB,32-KB,Reserved,64-KB,Reserved,128-KB,Reserved,256-KB,512-KB,Reserved,1-MB,Reserved,2-MB,?..." bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile Program Memory Size" "Disabled,8-KB,16-KB,32-KB,Reserved,64-KB,Reserved,128-KB,Reserved,256-KB,512-KB,Reserved,1-MB,Reserved,2-MB,?..." textline " " bitfld.long 0x00 5.--7. " EPROC ,Embedded Processor" "Reserved,ARM946E-S,ARM7TDMI,Reserved,ARM920T,ARM926EJ-S,?..." bitfld.long 0x00 0.--4. " VERSION ,Device Version" "Version 0,Version 1,Version 2,Version 3,Version 4,Version 5,Version 6,Version 7,Version 8,Version 9,Version 10,Version 11,Version 12,Version 13,Version 14,Version 15,Version 16,Version 17,Version 18,Version 19,Version 20,Version 21,Version 22,Version 23,Version 24,Version 25,Version 26,Version 27,Version 28,Version 29,Version 30,Version 31" line.long 0x04 "DBGU_EXID,Debug Unit Chip ID Extension Register" group.long 0x48++0x03 line.long 0x00 "DBGU_FNR,Debug Unit Force NTRST Register" bitfld.long 0x00 0. " FNTRST ,NTRST Force" "Not forced,Forced" tree "PDC_DBGU (Peripheral DMA Controller for Debug Unit)" base ad:0xFFFFF200 width 11. group.long 0x100++0x27 line.long 0x00 "DBGU_RPR,PDC/DBGU Receive Pointer Register" line.long 0x04 "DBGU_RCR,PDC/DBGU Receive Counter Register" hexmask.long.word 0x04 00.--15. 1. " RXCTR ,Receive Counter Value" line.long 0x08 "DBGU_TPR,PDC/DBGU Transmit Pointer Register" line.long 0x0C "DBGU_TCR,PDC/DBGU Transmit Counter Register" hexmask.long.word 0x0c 00.--15. 1. " TXCTR ,Transmit Counter Value" line.long 0x10 "DBGU_RNPR,PDC/DBGU Receive Next Pointer Register" line.long 0x14 "DBGU_RNCR,PDC/DBGU Receive Next Counter Register" hexmask.long.word 0x14 00.--15. 1. " RXNCR ,Receive Next Counter Value" line.long 0x18 "DBGU_TNPR,PDC/DBGU Transmit Next Pointer Register" line.long 0x1C "DBGU_TNCR,PDC/DBGU Transmit Next Counter Register" hexmask.long.word 0x1C 00.--15. 1. " TXNCR ,Transmit Next Counter Value" line.long 0x24 "DBGU_PTSR,PDC/DBGU Transfer Status Register" setclrfld.long 0x24 08. 0x20 8. 0x20 9. " TXTEN_set/clr ,Transmitter Transfer Enable" "Disabled,Enabled" setclrfld.long 0x24 00. 0x20 0. 0x20 1. " RXTEN_set/clr ,Receiver Transfer Enable" "Disabled,Enabled" width 0xb tree.end tree.end tree.open "PIO (Parallel Input/Output Controllers)" tree "PIO A" base ad:0xFFFFF400 width 11. tree "PIO Controller Registers" group.long 0x08++0x03 line.long 0x00 "PIO_PSRA,PIO Controller PIO Status Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO" group.long 0x18++0x03 line.long 0x00 "PIO_OSRA,PIO Controller Output Status Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status 31" "Input,Output" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status 30" "Input,Output" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status 29" "Input,Output" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status 28" "Input,Output" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status 27" "Input,Output" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status 26" "Input,Output" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status 25" "Input,Output" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status 24" "Input,Output" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status 23" "Input,Output" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status 22" "Input,Output" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status 21" "Input,Output" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status 20" "Input,Output" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status 19" "Input,Output" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status 18" "Input,Output" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status 17" "Input,Output" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status 16" "Input,Output" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status 15" "Input,Output" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output" group.long 0x28++0x03 line.long 0x00 "PIO_IFSRA,PIO Controller Input Filter Status Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PIO_ODSRA,PIO Controller Output Data Status Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High" rgroup.long 0x3c++0x03 line.long 0x00 "PIO_PDSRA,PIO Controller Pin Data Status Register A" bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High" bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High" bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High" bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High" textline " " bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High" bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High" bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High" bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High" textline " " bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High" bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High" bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High" bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High" textline " " bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High" bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High" bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High" bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High" textline " " bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High" bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High" bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High" bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High" textline " " bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High" bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High" bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High" bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High" textline " " bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High" bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High" bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High" bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High" textline " " bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High" bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High" bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High" bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High" group.long 0x48++0x03 line.long 0x00 "PIO_IMRA,PIO Controller Interrupt Mask Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled" tree.end tree "PIO Status Registers" hgroup.long 0x4c++0x03 hide.long 0x00 "PIO_ISRA,PIO Controller Interrupt Status Register A" in group.long 0x58++0x03 line.long 0x00 "PIO_MDSRA,PIO Multi-Driver Status Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled" group.long 0x68++0x03 line.long 0x00 "PIO_PUSRA,PIO Pull Up Status Register A" setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_Set/Clear ,Pull Up 31 Status" "Enabled,Disabled" setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_Set/Clear ,Pull Up 30 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_Set/Clear ,Pull Up 29 Status" "Enabled,Disabled" setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_Set/Clear ,Pull Up 28 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_Set/Clear ,Pull Up 27 Status" "Enabled,Disabled" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_Set/Clear ,Pull Up 26 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_Set/Clear ,Pull Up 25 Status" "Enabled,Disabled" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_Set/Clear ,Pull Up 24 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_Set/Clear ,Pull Up 23 Status" "Enabled,Disabled" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_Set/Clear ,Pull Up 22 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_Set/Clear ,Pull Up 21 Status" "Enabled,Disabled" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_Set/Clear ,Pull Up 20 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_Set/Clear ,Pull Up 19 Status" "Enabled,Disabled" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_Set/Clear ,Pull Up 18 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_Set/Clear ,Pull Up 17 Status" "Enabled,Disabled" setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_Set/Clear ,Pull Up 16 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_Set/Clear ,Pull Up 15 Status" "Enabled,Disabled" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled" setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled" setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled" setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled" setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled" group.long 0x78++0x03 line.long 0x00 "PIO_ABSRA,PIO Peripheral A B Status Register A" setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Peripheral 31 A B Status" "D31,TIMER2_TIOB2" setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Peripheral 30 A B Status" "D30,TIMER2_TIOA2" textline " " setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Peripheral 29 A B Status" "D29,TIMER1_TIOB1" setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Peripheral 28 A B Status" "D28,TIMER1_TIOA1" textline " " setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Peripheral 27 A B Status" "D27,TIMER0_TIOB0" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Peripheral 26 A B Status" "D26,TIMER0_TIOA0" textline " " setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Peripheral 25 A B Status" "D25,TIMER2_TCLK2" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Peripheral 24 A B Status" "D24,TIMER1_TCLK1" textline " " setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Peripheral 23 A B Status" "D23,TIMER0_TCLK0" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Peripheral 22 A B Status" "D22,USART1_RXD1" textline " " setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Peripheral 21 A B Status" "D21,USART1_TXD1" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Peripheral 20 A B Status" "D20,USART1_CTS1" textline " " setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Peripheral 19 A B Status" "D19,USART1_RTS1" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Peripheral 18 A B Status" "D18,USART1_SCK1" textline " " setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Peripheral 17 A B Status" "D17,APMC_PCK3" setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Peripheral 16 A B Status" "D16,APMC_PCK2" textline " " setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Peripheral 15 A B Status" "A24,APMC_PCK1" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Peripheral 14 A B Status" "A23,APMC_PCK0" textline " " setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Peripheral 13 A B Status" "CFCE2,SPI_NPCS3" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Peripheral 12 A B Status" "NCS5/CFCS1,SPI_NPCS2" textline " " setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Peripheral 11 A B Status" "IRQ1,SPI_NPCS1" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Peripheral 10 A B Status" "IRQ0,SPI_NPCS0" textline " " setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Peripheral 9 A B Status" "ADCTRIG,SPI_SPCK" setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Peripheral 8 A B Status" "NCS7,SPI_MOSI" textline " " setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Peripheral 7 A B Status" "NCS6,SPI_MISO" setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Peripheral 6 A B Status" "NANDWE,USART0_RXD0" textline " " setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Peripheral 5 A B Status" "NANDOE,USART0_TXD0" setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Peripheral 4 A B Status" "A25/CFRNW,USART0_CTS0" textline " " setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Peripheral 3 A B Status" "CFCE1,USART0_RTS0" setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Peripheral 2 A B Status" "NCS4/CFCS0,USART0_SCK0" textline " " setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Peripheral 1 A B Status" "NWAIT,DBG_DTXD" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Peripheral 0 A B Status" "FIQ,DBG_DRXD" group.long 0xA8++0x03 line.long 0x00 "PIO_OWSRA,PIO Output Write Status Register A" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P_set/clr1 ,Output Write Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled" tree.end width 0xb tree.end tree "PIO B" base ad:0xFFFFF600 width 11. tree "PIO Controller Registers" group.long 0x08++0x03 line.long 0x00 "PIO_PSRB,PIO Controller PIO Status Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,PIO31 Status" "Peripheral,PIO" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,PIO30 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,PIO29 Status" "Peripheral,PIO" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,PIO28 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,PIO27 Status" "Peripheral,PIO" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,PIO26 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,PIO25 Status" "Peripheral,PIO" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,PIO24 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,PIO23 Status" "Peripheral,PIO" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,PIO22 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,PIO21 Status" "Peripheral,PIO" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,PIO20 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,PIO19 Status" "Peripheral,PIO" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,PIO18 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,PIO17 Status" "Peripheral,PIO" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,PIO16 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,PIO15 Status" "Peripheral,PIO" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,PIO14 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,PIO13 Status" "Peripheral,PIO" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,PIO12 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,PIO11 Status" "Peripheral,PIO" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,PIO10 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,PIO9 Status" "Peripheral,PIO" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,PIO8 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,PIO7 Status" "Peripheral,PIO" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,PIO6 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,PIO5 Status" "Peripheral,PIO" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,PIO4 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,PIO3 Status" "Peripheral,PIO" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,PIO2 Status" "Peripheral,PIO" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,PIO1 Status" "Peripheral,PIO" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,PIO0 Status" "Peripheral,PIO" group.long 0x18++0x03 line.long 0x00 "PIO_OSRB,PIO Controller Output Status Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Status 31" "Input,Output" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Status 30" "Input,Output" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Status 29" "Input,Output" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Status 28" "Input,Output" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Status 27" "Input,Output" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Status 26" "Input,Output" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Status 25" "Input,Output" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Status 24" "Input,Output" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Status 23" "Input,Output" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Status 22" "Input,Output" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Status 21" "Input,Output" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Status 20" "Input,Output" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Status 19" "Input,Output" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Status 18" "Input,Output" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Status 17" "Input,Output" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Status 16" "Input,Output" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Status 15" "Input,Output" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Status 14" "Input,Output" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Status 13" "Input,Output" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Status 12" "Input,Output" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Status 11" "Input,Output" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Status 10" "Input,Output" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Status 9" "Input,Output" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Status 8" "Input,Output" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Status 7" "Input,Output" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Status 6" "Input,Output" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Status 5" "Input,Output" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Status 4" "Input,Output" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Status 3" "Input,Output" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Status 2" "Input,Output" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Status 1" "Input,Output" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Status 0" "Input,Output" group.long 0x28++0x03 line.long 0x00 "PIO_IFSRB,PIO Controller Input Filter Status Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Filter Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Filter Status 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Filter Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Filter Status 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Filter Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Filter Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Filter Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Filter Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Filter Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Filter Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Filter Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Filter Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Filter Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Filter Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Filter Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Filter Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Filter Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Filter Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Filter Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Filter Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Filter Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Filter Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Filter Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Filter Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Filter Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Filter Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Filter Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Filter Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Filter Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Filter Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Filter Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Filter Status 0" "Disabled,Enabled" group.long 0x38++0x03 line.long 0x00 "PIO_ODSRB,PIO Controller Output Data Status Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Data Status 31" "Low,High" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Data Status 30" "Low,High" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Data Status 29" "Low,High" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Data Status 28" "Low,High" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Data Status 27" "Low,High" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Data Status 26" "Low,High" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Data Status 25" "Low,High" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Data Status 24" "Low,High" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Data Status 23" "Low,High" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Data Status 22" "Low,High" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Data Status 21" "Low,High" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Data Status 20" "Low,High" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Data Status 19" "Low,High" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Data Status 18" "Low,High" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Data Status 17" "Low,High" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Data Status 16" "Low,High" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Data Status 15" "Low,High" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Data Status 14" "Low,High" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Data Status 13" "Low,High" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Data Status 12" "Low,High" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Data Status 11" "Low,High" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Data Status 10" "Low,High" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Data Status 9" "Low,High" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Data Status 8" "Low,High" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Data Status 7" "Low,High" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Data Status 6" "Low,High" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Data Status 5" "Low,High" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Data Status 4" "Low,High" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Data Status 3" "Low,High" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Data Status 2" "Low,High" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Output Data Status 1" "Low,High" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Data Status 0" "Low,High" rgroup.long 0x3c++0x03 line.long 0x00 "PIO_PDSRB,PIO Controller Pin Data Status Register B" bitfld.long 0x00 31. " P31 ,Output Data Status 31" "Low,High" bitfld.long 0x00 30. " P30 ,Output Data Status 30" "Low,High" bitfld.long 0x00 29. " P29 ,Output Data Status 29" "Low,High" bitfld.long 0x00 28. " P28 ,Output Data Status 28" "Low,High" textline " " bitfld.long 0x00 27. " P27 ,Output Data Status 27" "Low,High" bitfld.long 0x00 26. " P26 ,Output Data Status 26" "Low,High" bitfld.long 0x00 25. " P25 ,Output Data Status 25" "Low,High" bitfld.long 0x00 24. " P24 ,Output Data Status 24" "Low,High" textline " " bitfld.long 0x00 23. " P23 ,Output Data Status 23" "Low,High" bitfld.long 0x00 22. " P22 ,Output Data Status 22" "Low,High" bitfld.long 0x00 21. " P21 ,Output Data Status 21" "Low,High" bitfld.long 0x00 20. " P20 ,Output Data Status 20" "Low,High" textline " " bitfld.long 0x00 19. " P19 ,Output Data Status 19" "Low,High" bitfld.long 0x00 18. " P18 ,Output Data Status 18" "Low,High" bitfld.long 0x00 17. " P17 ,Output Data Status 17" "Low,High" bitfld.long 0x00 16. " P16 ,Output Data Status 16" "Low,High" textline " " bitfld.long 0x00 15. " P15 ,Output Data Status 15" "Low,High" bitfld.long 0x00 14. " P14 ,Output Data Status 14" "Low,High" bitfld.long 0x00 13. " P13 ,Output Data Status 13" "Low,High" bitfld.long 0x00 12. " P12 ,Output Data Status 12" "Low,High" textline " " bitfld.long 0x00 11. " P11 ,Output Data Status 11" "Low,High" bitfld.long 0x00 10. " P10 ,Output Data Status 10" "Low,High" bitfld.long 0x00 9. " P9 ,Output Data Status 9" "Low,High" bitfld.long 0x00 8. " P8 ,Output Data Status 8" "Low,High" textline " " bitfld.long 0x00 7. " P7 ,Output Data Status 7" "Low,High" bitfld.long 0x00 6. " P6 ,Output Data Status 6" "Low,High" bitfld.long 0x00 5. " P5 ,Output Data Status 5" "Low,High" bitfld.long 0x00 4. " P4 ,Output Data Status 4" "Low,High" textline " " bitfld.long 0x00 3. " P3 ,Output Data Status 3" "Low,High" bitfld.long 0x00 2. " P2 ,Output Data Status 2" "Low,High" bitfld.long 0x00 1. " P1 ,Output Data Status 1" "Low,High" bitfld.long 0x00 0. " P0 ,Output Data Status 0" "Low,High" group.long 0x48++0x03 line.long 0x00 "PIO_IMRB,PIO Controller Interrupt Mask Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Input Change Interrupt Mask 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Input Change Interrupt Mask 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Input Change Interrupt Mask 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Input Change Interrupt Mask 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Input Change Interrupt Mask 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Input Change Interrupt Mask 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Input Change Interrupt Mask 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Input Change Interrupt Mask 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Input Change Interrupt Mask 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Input Change Interrupt Mask 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Input Change Interrupt Mask 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Input Change Interrupt Mask 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Input Change Interrupt Mask 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Input Change Interrupt Mask 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Input Change Interrupt Mask 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Input Change Interrupt Mask 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Input Change Interrupt Mask 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Input Change Interrupt Mask 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Input Change Interrupt Mask 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Input Change Interrupt Mask 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Input Change Interrupt Mask 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Input Change Interrupt Mask 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Input Change Interrupt Mask 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Input Change Interrupt Mask 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Input Change Interrupt Mask 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Input Change Interrupt Mask 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Input Change Interrupt Mask 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Input Change Interrupt Mask 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Input Change Interrupt Mask 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Input Change Interrupt Mask 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Input Change Interrupt Mask 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Input Change Interrupt Mask 0" "Disabled,Enabled" tree.end tree "PIO Status Registers" hgroup.long 0x4c++0x03 hide.long 0x00 "PIO_ISRB,PIO Controller Interrupt Status Register B" in group.long 0x58++0x03 line.long 0x00 "PIO_MDSRB,PIO Multi-Driver Status Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Multi Drive Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Multi Drive Status 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Multi Drive Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Multi Drive Status 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Multi Drive Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Multi Drive Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Multi Drive Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Multi Drive Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Multi Drive Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Multi Drive Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Multi Drive Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Multi Drive Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Multi Drive Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Multi Drive Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Multi Drive Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Multi Drive Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Multi Drive Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Multi Drive Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Multi Drive Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Multi Drive Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Multi Drive Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Multi Drive Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Multi Drive Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Multi Drive Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Multi Drive Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Multi Drive Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Multi Drive Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Multi Drive Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Multi Drive Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Multi Drive Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P1_set/clr ,Multi Drive Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Multi Drive Status 0" "Disabled,Enabled" group.long 0x68++0x03 line.long 0x00 "PIO_PUSRB,PIO Pull Up Status Register B" setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_Set/Clear ,Pull Up 31 Status" "Enabled,Disabled" setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_Set/Clear ,Pull Up 30 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_Set/Clear ,Pull Up 29 Status" "Enabled,Disabled" setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_Set/Clear ,Pull Up 28 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_Set/Clear ,Pull Up 27 Status" "Enabled,Disabled" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_Set/Clear ,Pull Up 26 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_Set/Clear ,Pull Up 25 Status" "Enabled,Disabled" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_Set/Clear ,Pull Up 24 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_Set/Clear ,Pull Up 23 Status" "Enabled,Disabled" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_Set/Clear ,Pull Up 22 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_Set/Clear ,Pull Up 21 Status" "Enabled,Disabled" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_Set/Clear ,Pull Up 20 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_Set/Clear ,Pull Up 19 Status" "Enabled,Disabled" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_Set/Clear ,Pull Up 18 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_Set/Clear ,Pull Up 17 Status" "Enabled,Disabled" setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_Set/Clear ,Pull Up 16 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_Set/Clear ,Pull Up 15 Status" "Enabled,Disabled" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_Set/Clear ,Pull Up 14 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_Set/Clear ,Pull Up 13 Status" "Enabled,Disabled" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_Set/Clear ,Pull Up 12 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_Set/Clear ,Pull Up 11 Status" "Enabled,Disabled" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_Set/Clear ,Pull Up 10 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_Set/Clear ,Pull Up 9 Status" "Enabled,Disabled" setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_Set/Clear ,Pull Up 8 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_Set/Clear ,Pull Up 7 Status" "Enabled,Disabled" setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_Set/Clear ,Pull Up 6 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_Set/Clear ,Pull Up 5 Status" "Enabled,Disabled" setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_Set/Clear ,Pull Up 4 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_Set/Clear ,Pull Up 3 Status" "Enabled,Disabled" setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_Set/Clear ,Pull Up 2 Status" "Enabled,Disabled" textline " " setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_Set/Clear ,Pull Up 1 Status" "Enabled,Disabled" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_Set/Clear ,Pull Up 0 Status" "Enabled,Disabled" group.long 0x78++0x03 line.long 0x00 "PIO_ABSRB,PIO Peripheral A B Status Register B" setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P31_set/clr ,Peripheral 31 A B Status" "A,B" setclrfld.long 0x00 30. -0x04 30. -0x08 30. " P30_set/clr ,Peripheral 30 A B Status" "A,B" textline " " setclrfld.long 0x00 29. -0x04 29. -0x08 29. " P29_set/clr ,Peripheral 29 A B Status" "A,B" setclrfld.long 0x00 28. -0x04 28. -0x08 28. " P28_set/clr ,Peripheral 28 A B Status" "A,B" textline " " setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P27_set/clr ,Peripheral 27 A B Status" "A,B" setclrfld.long 0x00 26. -0x04 26. -0x08 26. " P26_set/clr ,Peripheral 26 A B Status" "A,B" textline " " setclrfld.long 0x00 25. -0x04 25. -0x08 25. " P25_set/clr ,Peripheral 25 A B Status" "A,B" setclrfld.long 0x00 24. -0x04 24. -0x08 24. " P24_set/clr ,Peripheral 24 A B Status" "A,B" textline " " setclrfld.long 0x00 23. -0x04 23. -0x08 23. " P23_set/clr ,Peripheral 23 A B Status" "A,B" setclrfld.long 0x00 22. -0x04 22. -0x08 22. " P22_set/clr ,Peripheral 22 A B Status" "A,B" textline " " setclrfld.long 0x00 21. -0x04 21. -0x08 21. " P21_set/clr ,Peripheral 21 A B Status" "A,B" setclrfld.long 0x00 20. -0x04 20. -0x08 20. " P20_set/clr ,Peripheral 20 A B Status" "A,B" textline " " setclrfld.long 0x00 19. -0x04 19. -0x08 19. " P19_set/clr ,Peripheral 19 A B Status" "A,B" setclrfld.long 0x00 18. -0x04 18. -0x08 18. " P18_set/clr ,Peripheral 18 A B Status" "A,B" textline " " setclrfld.long 0x00 17. -0x04 17. -0x08 17. " P17_set/clr ,Peripheral 17 A B Status" "A,B" setclrfld.long 0x00 16. -0x04 16. -0x08 16. " P16_set/clr ,Peripheral 16 A B Status" "A,B" textline " " setclrfld.long 0x00 15. -0x04 15. -0x08 15. " P15_set/clr ,Peripheral 15 A B Status" "A,B" setclrfld.long 0x00 14. -0x04 14. -0x08 14. " P14_set/clr ,Peripheral 14 A B Status" "A,B" textline " " setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P13_set/clr ,Peripheral 13 A B Status" "A,B" setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P12_set/clr ,Peripheral 12 A B Status" "A,B" textline " " setclrfld.long 0x00 11. -0x04 11. -0x08 11. " P11_set/clr ,Peripheral 11 A B Status" "A,B" setclrfld.long 0x00 10. -0x04 10. -0x08 10. " P10_set/clr ,Peripheral 10 A B Status" "A,B" textline " " setclrfld.long 0x00 9. -0x04 9. -0x08 9. " P9_set/clr ,Peripheral 9 A B Status" "A,B" setclrfld.long 0x00 8. -0x04 8. -0x08 8. " P8_set/clr ,Peripheral 8 A B Status" "A,B" textline " " setclrfld.long 0x00 7. -0x04 7. -0x08 7. " P7_set/clr ,Peripheral 7 A B Status" "A,B" setclrfld.long 0x00 6. -0x04 6. -0x08 6. " P6_set/clr ,Peripheral 6 A B Status" "A,B" textline " " setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P5_set/clr ,Peripheral 5 A B Status" "A,B" setclrfld.long 0x00 4. -0x04 4. -0x08 4. " P4_set/clr ,Peripheral 4 A B Status" "A,B" textline " " setclrfld.long 0x00 3. -0x04 3. -0x08 3. " P3_set/clr ,Peripheral 3 A B Status" "A,B" setclrfld.long 0x00 2. -0x04 2. -0x08 2. " P2_set/clr ,Peripheral 2 A B Status" "A,B" textline " " setclrfld.long 0x00 1. -0x04 1. -0x08 1. " P1_set/clr ,Peripheral 1 A B Status" "A,B" setclrfld.long 0x00 0. -0x04 0. -0x08 0. " P0_set/clr ,Peripheral 0 A B Status" "A,B" group.long 0xA8++0x03 line.long 0x00 "PIO_OWSRB,PIO Output Write Status Register B" setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P31_set/clr ,Output Write Status 31" "Disabled,Enabled" setclrfld.long 0x00 30. -0x08 30. -0x04 30. " P30_set/clr ,Output Write Status 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. -0x08 29. -0x04 29. " P29_set/clr ,Output Write Status 29" "Disabled,Enabled" setclrfld.long 0x00 28. -0x08 28. -0x04 28. " P28_set/clr ,Output Write Status 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P27_set/clr ,Output Write Status 27" "Disabled,Enabled" setclrfld.long 0x00 26. -0x08 26. -0x04 26. " P26_set/clr ,Output Write Status 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. -0x08 25. -0x04 25. " P25_set/clr ,Output Write Status 25" "Disabled,Enabled" setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P24_set/clr ,Output Write Status 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. -0x08 23. -0x04 23. " P23_set/clr ,Output Write Status 23" "Disabled,Enabled" setclrfld.long 0x00 22. -0x08 22. -0x04 22. " P22_set/clr ,Output Write Status 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. -0x08 21. -0x04 21. " P21_set/clr ,Output Write Status 21" "Disabled,Enabled" setclrfld.long 0x00 20. -0x08 20. -0x04 20. " P20_set/clr ,Output Write Status 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. -0x08 19. -0x04 19. " P19_set/clr ,Output Write Status 19" "Disabled,Enabled" setclrfld.long 0x00 18. -0x08 18. -0x04 18. " P18_set/clr ,Output Write Status 18" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. -0x08 17. -0x04 17. " P17_set/clr ,Output Write Status 17" "Disabled,Enabled" setclrfld.long 0x00 16. -0x08 16. -0x04 16. " P16_set/clr ,Output Write Status 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. -0x08 15. -0x04 15. " P15_set/clr ,Output Write Status 15" "Disabled,Enabled" setclrfld.long 0x00 14. -0x08 14. -0x04 14. " P14_set/clr ,Output Write Status 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P13_set/clr ,Output Write Status 13" "Disabled,Enabled" setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P12_set/clr ,Output Write Status 12" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. -0x08 11. -0x04 11. " P11_set/clr ,Output Write Status 11" "Disabled,Enabled" setclrfld.long 0x00 10. -0x08 10. -0x04 10. " P10_set/clr ,Output Write Status 10" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. -0x08 9. -0x04 9. " P9_set/clr ,Output Write Status 9" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " P8_set/clr ,Output Write Status 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " P7_set/clr ,Output Write Status 7" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " P6_set/clr ,Output Write Status 6" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P5_set/clr ,Output Write Status 5" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " P4_set/clr ,Output Write Status 4" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " P3_set/clr ,Output Write Status 3" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " P2_set/clr ,Output Write Status 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " P_set/clr1 ,Output Write Status 1" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P0_set/clr ,Output Write Status 0" "Disabled,Enabled" tree.end width 0xb tree.end tree.end tree "SPI (Serial Peripheral Interfaces)" base ad:0xFFFAC000 width 10. wgroup.long 0x00++0x03 line.long 0x00 "SPI_CR,SPI Control Register" bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deasserted" bitfld.long 0x00 7. " SWRST ,SPI Software Reset" "No effect,Reset" textline " " bitfld.long 0x00 1. " SPIDIS ,SPI Disable" "No effect,Disabled" bitfld.long 0x00 0. " SPIEN ,SPI Enable" "No effect,Enabled" if ((((data.long(ad:(0xFFFAC000+0x4)))&0x06)==0x00)&&(((data.long(ad:(0xFFFAC000+0x4)))&0x1)==0x1)) ;if PCSDEC=0 and PS=0 and MSTR=1 group.long 0x04++0x03 line.long 0x00 "SPI_MR,SPI Mode Register" hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay" bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder" textline " " bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable" bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..." textline " " bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master" bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled" sif (cpu()=="AT91CAP7E") bitfld.long 0x00 3. " FDIV ,Clock Selection" "MCK,MCK/32" endif elif ((((data.long(ad:(0xFFFAC000+0x4)))&0x06)==0x04)&&(((data.long(ad:(0xFFFAC000+0x4)))&0x1)==0x1)) ;if PCSDEC=1 and PS=0 and MSTR=1 group.long 0x04++0x03 line.long 0x00 "SPI_MR,SPI Mode Register" hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay" bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder" textline " " bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable" bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111" textline " " bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master" bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled" sif (cpu()=="AT91CAP7E") bitfld.long 0x00 3. " FDIV ,Clock Selection" "MCK,MCK/32" endif elif (((data.long(ad:(0xFFFAC000+0x4)))&0x07)==(0x03||0x07)) ;if (PS=1) or (PCSDEC=1 and PS=1 and MSTR=1) group.long 0x04++0x03 line.long 0x00 "SPI_MR,SPI Mode Register" hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay" bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder" textline " " bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable" bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master" textline " " bitfld.long 0x00 7. " LLB ,Local Loopback Enable" "Disabled,Enabled" bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled" sif (cpu()=="AT91CAP7E") textline " " bitfld.long 0x00 3. " FDIV ,Clock Selection" "MCK,MCK/32" endif elif (((data.long(ad:(0xFFFAC000+0x4)))&0x06)==0x00) ;if PCSDEC=0 and PS=0 group.long 0x04++0x03 line.long 0x00 "SPI_MR,SPI Mode Register" hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay" bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder" textline " " bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable" bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..." textline " " bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master" bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled" sif (cpu()=="AT91CAP7E") textline " " bitfld.long 0x00 3. " FDIV ,Clock Selection" "MCK,MCK/32" endif elif (((data.long(ad:(0xFFFAC000+0x4)))&0x06)==0x04) ;if PCSDEC=1 and PS=0 group.long 0x04++0x03 line.long 0x00 "SPI_MR,SPI Mode Register" hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay" bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder" textline " " bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable" bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111" textline " " bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master" bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled" sif (cpu()=="AT91CAP7E") textline " " bitfld.long 0x00 3. " FDIV ,Clock Selection" "MCK,MCK/32" endif else group.long 0x04++0x03 line.long 0x00 "SPI_MR,SPI Mode Register" hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip Selects Delay" bitfld.long 0x00 2. " PCSDEC ,Chip Select Decode" "Directly,Decoder" textline " " bitfld.long 0x00 1. " PS ,Peripheral Selection" "Fixed,Variable" bitfld.long 0x00 0. " MSTR ,Master Mode" "Slave,Master" textline " " bitfld.long 0x00 4. " MODFDIS ,Mode Fault Detection" "Enabled,Disabled" sif (cpu()=="AT91CAP7E") bitfld.long 0x00 3. " FDIV ,Clock Selection" "MCK,MCK/32" endif endif hgroup.long 0x08++0x03 hide.long 0x00 "SPI_RDR,SPI Receive Data Register" in if (((data.long(ad:(0xFFFAC000+0x4)))&0x06)==0x02) ;if PCSDEC=0 and PS=1 wgroup.long 0x0C++0x03 line.long 0x00 "SPI_TDR,SPI Transmit Data Register" bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deasserted" bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..." textline " " hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data" elif (((data.long(ad:(0xFFFAC000+0x4)))&0x06)==0x06) ;if PCSDEC=1 and PS=1 wgroup.long 0x0C++0x03 line.long 0x00 "SPI_TDR,SPI Transmit Data Register" bitfld.long 0x00 24. " LASTXFER ,Last Transfer" "No effect,Deasserted" bitfld.long 0x00 16.--19. " PCS ,Peripheral Chip Select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111" textline " " hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data" else ;if PS=0 wgroup.long 0x0C++0x03 line.long 0x00 "SPI_TDR,SPI Transmit Data Register" hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit Data" endif hgroup.long 0x10++0x03 hide.long 0x00 "SPI_SR,SPI Status Register" in group.long 0x1C++0x03 line.long 0x00 "SPI_IMR,SPI Interrupt Mask Register" setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,Transmission Registers Empty Mask" "Disabled,Enabled" setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR_set/clr ,NSS Rising Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. -0x08 7. -0x04 7. " TXBUFE_set/clr ,Transmit Buffer Empty Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " ENDTX_set/clr ,End of Transmit Buffer Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDRX_set/clr ,End of Receive Buffer Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF_set/clr ,Mode Fault Error Inrerrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE_set/clr ,SPI Transmit Data Register Empty Inrerrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF_set/clr ,Receive Data Register Full Inrerrupt Mask" "Disabled,Enabled" group.long 0x30++0x0F line.long 0x0 "SPI_CSR0,SPI Chip Select Register 0" hexmask.long.byte 0x0 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay" hexmask.long.byte 0x0 16.--23. 1. " DLYBS ,Delay Before SPCK" textline " " hexmask.long.byte 0x0 8.--15. 1. " SCBR ,Serial Clock Baud Rate" bitfld.long 0x0 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..." textline " " bitfld.long 0x0 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen" bitfld.long 0x0 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed" textline " " bitfld.long 0x0 0. " CPOL ,Clock Polarity" "Low,High" line.long 0x4 "SPI_CSR1,SPI Chip Select Register 1" hexmask.long.byte 0x4 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay" hexmask.long.byte 0x4 16.--23. 1. " DLYBS ,Delay Before SPCK" textline " " hexmask.long.byte 0x4 8.--15. 1. " SCBR ,Serial Clock Baud Rate" bitfld.long 0x4 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..." textline " " bitfld.long 0x4 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen" bitfld.long 0x4 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed" textline " " bitfld.long 0x4 0. " CPOL ,Clock Polarity" "Low,High" line.long 0x8 "SPI_CSR2,SPI Chip Select Register 2" hexmask.long.byte 0x8 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay" hexmask.long.byte 0x8 16.--23. 1. " DLYBS ,Delay Before SPCK" textline " " hexmask.long.byte 0x8 8.--15. 1. " SCBR ,Serial Clock Baud Rate" bitfld.long 0x8 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..." textline " " bitfld.long 0x8 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen" bitfld.long 0x8 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed" textline " " bitfld.long 0x8 0. " CPOL ,Clock Polarity" "Low,High" line.long 0xC "SPI_CSR3,SPI Chip Select Register 3" hexmask.long.byte 0xC 24.--31. 1. " DLYBCT ,Consecutive Transfers Delay" hexmask.long.byte 0xC 16.--23. 1. " DLYBS ,Delay Before SPCK" textline " " hexmask.long.byte 0xC 8.--15. 1. " SCBR ,Serial Clock Baud Rate" bitfld.long 0xC 4.--7. " BITS ,Bits Per Transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..." textline " " bitfld.long 0xC 3. " CSAAT ,Chip Select Active After Transfer" "Risen,Not risen" bitfld.long 0xC 1. " NCPHA ,Clock Phase (leading/following edge)" "Changed/captured,Captured/changed" textline " " bitfld.long 0xC 0. " CPOL ,Clock Polarity" "Low,High" width 0xb tree "PDC_SPI (Peripheral DMA Controller for SPI)" base ad:0xFFFAC000 width 10. group.long 0x100++0x27 line.long 0x00 "SPI_RPR,PDC/SPI Receive Pointer Register" line.long 0x04 "SPI_RCR,PDC/SPI Receive Counter Register" hexmask.long.word 0x04 00.--15. 1. " RXCTR ,Receive Counter Value" line.long 0x08 "SPI_TPR,PDC/SPI Transmit Pointer Register" line.long 0x0C "SPI_TCR,PDC/SPI Transmit Counter Register" hexmask.long.word 0x0c 00.--15. 1. " TXCTR ,Transmit Counter Value" line.long 0x10 "SPI_RNPR,PDC/SPI Receive Next Pointer Register" line.long 0x14 "SPI_RNCR,PDC/SPI Receive Next Counter Register" hexmask.long.word 0x14 00.--15. 1. " RXNCR ,Receive Next Counter Value" line.long 0x18 "SPI_TNPR,PDC/SPI Transmit Next Pointer Register" line.long 0x1C "SPI_TNCR,PDC/SPI Transmit Next Counter Register" hexmask.long.word 0x1C 00.--15. 1. " TXNCR ,Transmit Next Counter Value" line.long 0x24 "SPI_PTSR,PDC/SPI Transfer Status Register" setclrfld.long 0x24 08. 0x20 8. 0x20 9. " TXTEN_set/clr ,Transmitter Transfer Enable" "Disabled,Enabled" setclrfld.long 0x24 00. 0x20 0. 0x20 1. " RXTEN_set/clr ,Receiver Transfer Enable" "Disabled,Enabled" width 0xb tree.end tree.end tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitters)" tree "USART 0" base ad:0xFFFB0000 width 0xA if ((((data.long(ad:(0xFFFB0000+0x4)))&0xE00)>=0xC00)&&((((data.long(ad:(0xFFFB0000+0x4)))&0xF)==0x4)||(((data.long(ad:(0xFFFB0000+0x4)))&0xF)==0x6))) wgroup.long 0x00++0x03 line.long 0x00 "US0_CR,USART0 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,Reset" bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,Sent" textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" elif (((data.long(ad:(0xFFFB0000+0x4)))&0xE00)>=0xC00) wgroup.long 0x00++0x03 line.long 0x00 "US0_CR,USART0 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,?..." bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,Sent" textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" elif ((((data.long(ad:(0xFFFB0000+0x4)))&0xE00)<0xC00)&&((((data.long(ad:(0xFFFB0000+0x4)))&0xF)==0x4)||(((data.long(ad:(0xFFFB0000+0x4)))&0xF)==0x6))) wgroup.long 0x00++0x03 line.long 0x00 "US0_CR,USART0 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,Reset" bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,?..." textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" else wgroup.long 0x00++0x03 line.long 0x00 "US0_CR,USART0 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,?..." bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,?..." textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" endif width 0xA if (((data.long(ad:(0xFFFB0000+0x4)))&0x100)==0x100) group.long 0x04++0x03 line.long 0x00 "US0_MR,USART0 Mode Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128") bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit" bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered" bitfld.long 0x00 24.--26. " MAX_ITERATION ,Iterations Maximum Number in ISO7816 Mode (T=0)" "No iteration,1 iteration,2 iterations,3 iterations,4 iterations,5 iterations,6 iterations,7 iterations" textline " " bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "Generated,Not generated" bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x" textline " " bitfld.long 0x00 18. " CLKO ,Clock Output Selection (SCK pin driven)" "Not driven,Driven" bitfld.long 0x00 17. " MODE9 ,9-Bit Character Length" "CHRL,9-bit" textline " " bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first" bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local,Remote" textline " " bitfld.long 0x00 12.--13. " NBSTOP ,Stop Bits Number" "1 bit,Reserved,2 bits,?..." bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,Multidrop,Multidrop" textline " " bitfld.long 0x00 8. " SYNC ,Synchronous Mode Selection" "Asynchronous,Synchronous" bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5-bit,6-bit,7-bit,8-bit" textline " " sif (cpuis("AT91CAP7*")) bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK" else bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK" endif bitfld.long 0x00 0.--3. " USART_MODE ,USART Mode" "Normal,RS485,Handshaking,Modem,IS07816 T=0,Reserved,IS07816 T=1,Reserved,IrDA,?..." textline " " sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" endif sif (cpu()=="AT91SAM7X512"||cpu()=="AT91SAM7X256"||cpu()=="AT91SAM7X128"||cpu()=="AT91SAM7XC512"||cpu()=="AT91SAM7XC256"||cpu()=="AT91SAM7XC128") bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif sif (cpuis("AT91CAP7*")) bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0" bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" textline " " bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif else group.long 0x04++0x03 line.long 0x00 "US0_MR,USART0 Mode Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128") bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit" bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered" bitfld.long 0x00 24.--26. " MAX_ITERATION ,Iterations Maximum Number in ISO7816 Mode (T=0)" "No iteration,1 iteration,2 iterations,3 iterations,4 iterations,5 iterations,6 iterations,7 iterations" textline " " bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "Generated,Not generated" bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x" textline " " bitfld.long 0x00 18. " CLKO ,Clock Output Selection (SCK pin driven)" "Not driven,Driven" bitfld.long 0x00 17. " MODE9 ,9-Bit Character Length" "CHRL,9-bit" textline " " bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first" bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local,Remote" textline " " bitfld.long 0x00 12.--13. " NBSTOP ,Stop Bits Number" "1 bit,1.5 bits,2 bits,?..." bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,Multidrop,Multidrop" textline " " bitfld.long 0x00 8. " SYNC ,Synchronous Mode Selection" "Asynchronous,Synchronous" bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5-bit,6-bit,7-bit,8-bit" textline " " sif (cpuis("AT91CAP7*")) bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK" else bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK" endif bitfld.long 0x00 0.--3. " USART_MODE ,USART Mode" "Normal,RS485,Handshaking,Modem,IS07816 T=0,Reserved,IS07816 T=1,Reserved,IrDA,?..." textline " " sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" endif sif (cpu()=="AT91SAM7X512"||cpu()=="AT91SAM7X256"||cpu()=="AT91SAM7X128"||cpu()=="AT91SAM7XC512"||cpu()=="AT91SAM7XC256"||cpu()=="AT91SAM7XC128") bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif sif (cpuis("AT91CAP7*")) bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0" bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" textline " " bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif endif group.long 0x10++0x3 line.long 0x00 "US0_IMR,USART0 Interrupt Mask Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128") setclrfld.long 0x00 20. -0x08 20. -0x04 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled" else setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 18. -0x08 18. -0x04 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 17. -0x08 17. -0x04 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. -0x08 16. -0x04 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled" setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-Out Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,Transmit End Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Receive Transfer End Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled" width 0xA hgroup.long 0x14++0x03 hide.long 0x00 "US0_CSR,USART0 Channel Status Register" in hgroup.long 0x18++0x03 hide.long 0x00 "US0_RHR,USART0 Receive Holding Register" in wgroup.long 0x1C++0x03 line.long 0x00 "US0_THR,USART0 Transmit Holding Register" bitfld.long 0x00 15. " TXSYNH ,Sync Field to Transmit" "Data,Command" hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to Transmit" group.long 0x20++0x0B line.long 0x00 "US0_BRGR,USART0 Baud Rate Generator Register" bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8" hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider" line.long 0x04 "US0_RTOR,USART0 Receiver Time-Out Register" hexmask.long.word 0x04 0.--15. 1. " TO ,Time-Out Value" line.long 0x08 "US0_TTGR,USART0 Transmitter Timeguard Register" hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value" group.long 0x40++0x03 line.long 0x00 "US0_FIDI,USART0 FI DI Ratio Register" hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value" hgroup.long 0x44++0x3 hide.long 0x00 "US0_NER,USART0 Errors Number Register" in sif (cpuis("AT91CAP7*")) group.long 0x50++0x03 line.long 0x00 "US0_MAN,USART0 Manchester Configuration Register" bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one" textline " " bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO" textline " " bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period" textline " " bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one" textline " " bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO" textline " " bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period" endif group.long 0x4C++0x3 line.long 0x0 "US0_IF,USART0 IrDA Filter Register" hexmask.long.byte 0x0 0.--7. 1. " IRDA_FILTER ,IrDA Filter" tree "PDC_USART0 (Peripheral DMA Controller for USART 0)" base ad:0xFFFB0000 width 13. group.long 0x100++0x27 line.long 0x00 "USART0_RPR,PDC/USART0 Receive Pointer Register" line.long 0x04 "USART0_RCR,PDC/USART0 Receive Counter Register" hexmask.long.word 0x04 00.--15. 1. " RXCTR ,Receive Counter Value" line.long 0x08 "USART0_TPR,PDC/USART0 Transmit Pointer Register" line.long 0x0C "USART0_TCR,PDC/USART0 Transmit Counter Register" hexmask.long.word 0x0c 00.--15. 1. " TXCTR ,Transmit Counter Value" line.long 0x10 "USART0_RNPR,PDC/USART0 Receive Next Pointer Register" line.long 0x14 "USART0_RNCR,PDC/USART0 Receive Next Counter Register" hexmask.long.word 0x14 00.--15. 1. " RXNCR ,Receive Next Counter Value" line.long 0x18 "USART0_TNPR,PDC/USART0 Transmit Next Pointer Register" line.long 0x1C "USART0_TNCR,PDC/USART0 Transmit Next Counter Register" hexmask.long.word 0x1C 00.--15. 1. " TXNCR ,Transmit Next Counter Value" line.long 0x24 "USART0_PTSR,PDC/USART0 Transfer Status Register" setclrfld.long 0x24 08. 0x20 8. 0x20 9. " TXTEN_set/clr ,Transmitter Transfer Enable" "Disabled,Enabled" setclrfld.long 0x24 00. 0x20 0. 0x20 1. " RXTEN_set/clr ,Receiver Transfer Enable" "Disabled,Enabled" width 0xb tree.end tree.end tree "USART 1" base ad:0xFFFB4000 width 0xA if ((((data.long(ad:(0xFFFB4000+0x4)))&0xE00)>=0xC00)&&((((data.long(ad:(0xFFFB4000+0x4)))&0xF)==0x4)||(((data.long(ad:(0xFFFB4000+0x4)))&0xF)==0x6))) wgroup.long 0x00++0x03 line.long 0x00 "US1_CR,USART1 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,Reset" bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,Sent" textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" elif (((data.long(ad:(0xFFFB4000+0x4)))&0xE00)>=0xC00) wgroup.long 0x00++0x03 line.long 0x00 "US1_CR,USART1 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,?..." bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,Sent" textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" elif ((((data.long(ad:(0xFFFB4000+0x4)))&0xE00)<0xC00)&&((((data.long(ad:(0xFFFB4000+0x4)))&0xF)==0x4)||(((data.long(ad:(0xFFFB4000+0x4)))&0xF)==0x6))) wgroup.long 0x00++0x03 line.long 0x00 "US1_CR,USART1 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,Reset" bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,?..." textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" else wgroup.long 0x00++0x03 line.long 0x00 "US1_CR,USART1 Control Register" bitfld.long 0x00 19. " RTSDIS ,Request to Send Disable" "No effect,Disabled" bitfld.long 0x00 18. " RTSEN ,Request to Send Enable" "No effect,Enabled" textline " " bitfld.long 0x00 17. " DTRDIS ,Data Terminal Ready Disable" "No effect,Disabled" bitfld.long 0x00 16. " DTREN ,Data Terminal Ready Enable" "No effect,Enabled" textline " " bitfld.long 0x00 15. " RETTO ,Time-Out Rearm" "No effect,Restarted" bitfld.long 0x00 14. " RSTNACK ,Non Acknowledge Reset" "No effect,Reset" textline " " bitfld.long 0x00 13. " RSTIT ,Iterations Reset" "No effect,?..." bitfld.long 0x00 12. " SENDA ,Address Send" "No effect,?..." textline " " bitfld.long 0x00 11. " STTTO ,Time-Out Start" "No effect,Started" bitfld.long 0x00 10. " STPBRK ,Break Stop" "No effect,Stopped" textline " " bitfld.long 0x00 9. " STTBRK ,Break Start" "No effect,Started" bitfld.long 0x00 8. " RSTSTA ,Status Bits Reset" "No effect,Reset" textline " " bitfld.long 0x00 7. " TXDIS ,Transmitter Disable" "No effect,Disabled" bitfld.long 0x00 6. " TXEN ,Transmitter Enable" "No effect,Enabled" textline " " bitfld.long 0x00 5. " RXDIS ,Receiver Disable" "No effect,Disabled" bitfld.long 0x00 4. " RXEN ,Receiver Enable" "No effect,Enabled" textline " " bitfld.long 0x00 3. " RSTTX ,Transmitter Reset" "No effect,Reset" bitfld.long 0x00 2. " RSTRX ,Receiver Reset" "No effect,Reset" endif width 0xA if (((data.long(ad:(0xFFFB4000+0x4)))&0x100)==0x100) group.long 0x04++0x03 line.long 0x00 "US1_MR,USART1 Mode Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128") bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit" bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered" bitfld.long 0x00 24.--26. " MAX_ITERATION ,Iterations Maximum Number in ISO7816 Mode (T=0)" "No iteration,1 iteration,2 iterations,3 iterations,4 iterations,5 iterations,6 iterations,7 iterations" textline " " bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "Generated,Not generated" bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x" textline " " bitfld.long 0x00 18. " CLKO ,Clock Output Selection (SCK pin driven)" "Not driven,Driven" bitfld.long 0x00 17. " MODE9 ,9-Bit Character Length" "CHRL,9-bit" textline " " bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first" bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local,Remote" textline " " bitfld.long 0x00 12.--13. " NBSTOP ,Stop Bits Number" "1 bit,Reserved,2 bits,?..." bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,Multidrop,Multidrop" textline " " bitfld.long 0x00 8. " SYNC ,Synchronous Mode Selection" "Asynchronous,Synchronous" bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5-bit,6-bit,7-bit,8-bit" textline " " sif (cpuis("AT91CAP7*")) bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK" else bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK" endif bitfld.long 0x00 0.--3. " USART_MODE ,USART Mode" "Normal,RS485,Handshaking,Modem,IS07816 T=0,Reserved,IS07816 T=1,Reserved,IrDA,?..." textline " " sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" endif sif (cpu()=="AT91SAM7X512"||cpu()=="AT91SAM7X256"||cpu()=="AT91SAM7X128"||cpu()=="AT91SAM7XC512"||cpu()=="AT91SAM7XC256"||cpu()=="AT91SAM7XC128") bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif sif (cpuis("AT91CAP7*")) bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0" bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" textline " " bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif else group.long 0x04++0x03 line.long 0x00 "US1_MR,USART1 Mode Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128") bitfld.long 0x00 31. " ONEBIT ,Start Frame Delimiter Selector" "Command/data,One bit" bitfld.long 0x00 29. " MAN ,Manchester Encoder/Decoder Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 28. " FILTER ,Infrared Receive Line Filter" "Not filtered,Filtered" bitfld.long 0x00 24.--26. " MAX_ITERATION ,Iterations Maximum Number in ISO7816 Mode (T=0)" "No iteration,1 iteration,2 iterations,3 iterations,4 iterations,5 iterations,6 iterations,7 iterations" textline " " bitfld.long 0x00 20. " INACK ,Inhibit Non Acknowledge" "Generated,Not generated" bitfld.long 0x00 19. " OVER ,Oversampling Mode" "16x,8x" textline " " bitfld.long 0x00 18. " CLKO ,Clock Output Selection (SCK pin driven)" "Not driven,Driven" bitfld.long 0x00 17. " MODE9 ,9-Bit Character Length" "CHRL,9-bit" textline " " bitfld.long 0x00 16. " MSBF ,Bit Order" "LSB first,MSB first" bitfld.long 0x00 14.--15. " CHMODE ,Channel Mode" "Normal,Automatic,Local,Remote" textline " " bitfld.long 0x00 12.--13. " NBSTOP ,Stop Bits Number" "1 bit,1.5 bits,2 bits,?..." bitfld.long 0x00 9.--11. " PAR ,Parity Type" "Even,Odd,Space,Mark,No parity,No parity,Multidrop,Multidrop" textline " " bitfld.long 0x00 8. " SYNC ,Synchronous Mode Selection" "Asynchronous,Synchronous" bitfld.long 0x00 6.--7. " CHRL ,Character Length" "5-bit,6-bit,7-bit,8-bit" textline " " sif (cpuis("AT91CAP7*")) bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/8,Reserved,SCK" else bitfld.long 0x00 4.--5. " USCLKS ,Clock Selection" "MCK,MCK/DIV,Reserved,SCK" endif bitfld.long 0x00 0.--3. " USART_MODE ,USART Mode" "Normal,RS485,Handshaking,Modem,IS07816 T=0,Reserved,IS07816 T=1,Reserved,IrDA,?..." textline " " sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" endif sif (cpu()=="AT91SAM7X512"||cpu()=="AT91SAM7X256"||cpu()=="AT91SAM7X128"||cpu()=="AT91SAM7XC512"||cpu()=="AT91SAM7XC256"||cpu()=="AT91SAM7XC128") bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif sif (cpuis("AT91CAP7*")) bitfld.long 0x00 30. " MODSYNC ,Manchester Synchronization Mode" "From 0 to 1,From 1 to 0" bitfld.long 0x00 22. " VAR_SYNC ,Variable Synchronization Command/Data Sync Start Frame Delimiter" "SYNC,US_THR" textline " " bitfld.long 0x00 21. " DSNACK ,Successive NACK Disable" "No,Yes" endif endif group.long 0x10++0x3 line.long 0x00 "US1_IMR,USART1 Interrupt Mask Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128") setclrfld.long 0x00 20. -0x08 20. -0x04 20. " MANE_set/clr ,Manchester Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled" else setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC_set/clr ,Clear to Send Input Change Interrupt Mask" "Disabled,Enabled" endif textline " " setclrfld.long 0x00 18. -0x08 18. -0x04 18. " DCDIC_set/clr ,Data Carrier Detect Input Change Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 17. -0x08 17. -0x04 17. " DSRIC_set/clr ,Data Set Ready Input Change Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. -0x08 16. -0x04 16. " RIIC_set/clr ,Ring Indicator Input Change Mask" "Disabled,Enabled" setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK_set/clr ,Non Acknowledge Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. -0x08 12. -0x04 12. " RXBUFF_set/clr ,Buffer Full Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " TXBUFE_set/clr ,Buffer Empty Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITERATION_set/clr ,Iteration Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY_set/clr ,TXEMPTY Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT_set/clr ,Time-Out Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE_set/clr ,Parity Error Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME_set/clr ,Framing Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE_set/clr ,Overrun Error Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. -0x08 4. -0x04 4. " ENDTX_set/clr ,Transmit End Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 3. -0x08 3. -0x04 3. " ENDRX_set/clr ,Receive Transfer End Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK_set/clr ,Receiver Break Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY_set/clr ,TXRDY Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY_set/clr ,RXRDY Interrupt Mask" "Disabled,Enabled" width 0xA hgroup.long 0x14++0x03 hide.long 0x00 "US1_CSR,USART1 Channel Status Register" in hgroup.long 0x18++0x03 hide.long 0x00 "US1_RHR,USART1 Receive Holding Register" in wgroup.long 0x1C++0x03 line.long 0x00 "US1_THR,USART1 Transmit Holding Register" bitfld.long 0x00 15. " TXSYNH ,Sync Field to Transmit" "Data,Command" hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to Transmit" group.long 0x20++0x0B line.long 0x00 "US1_BRGR,USART1 Baud Rate Generator Register" bitfld.long 0x00 16.--18. " FP ,Fractional Part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8" hexmask.long.word 0x00 0.--15. 1. " CD ,Clock Divider" line.long 0x04 "US1_RTOR,USART1 Receiver Time-Out Register" hexmask.long.word 0x04 0.--15. 1. " TO ,Time-Out Value" line.long 0x08 "US1_TTGR,USART1 Transmitter Timeguard Register" hexmask.long.byte 0x08 0.--7. 1. " TG ,Timeguard Value" group.long 0x40++0x03 line.long 0x00 "US1_FIDI,USART1 FI DI Ratio Register" hexmask.long.word 0x00 0.--10. 1. " FI_DI_RATIO ,FI Over DI Ratio Value" hgroup.long 0x44++0x3 hide.long 0x00 "US1_NER,USART1 Errors Number Register" in sif (cpuis("AT91CAP7*")) group.long 0x50++0x03 line.long 0x00 "US1_MAN,USART1 Manchester Configuration Register" bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " RX_MPOL ,Receiver Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one" textline " " bitfld.long 0x00 24.--25. " RX_PP ,Receiver Preamble Pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO" textline " " bitfld.long 0x00 16.--19. " RX_PL ,Receiver Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period" textline " " bitfld.long 0x00 12. " TX_MPOL ,Transmitter Manchester Polarity" "0:zero-to-one/1:one-to-zero,0:one-to-zero/1:zero-to-one" textline " " bitfld.long 0x00 8.--9. " TX_PP ,Transmitter Preamble Pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO" textline " " bitfld.long 0x00 0.--3. " TX_PL ,Transmitter Preamble Length" "Disabled,1 x Bit Period,2 x Bit Period,3 x Bit Period,4 x Bit Period,5 x Bit Period,6 x Bit Period,7 x Bit Period,8 x Bit Period,9 x Bit Period,10 x Bit Period,11 x Bit Period,12 x Bit Period,13 x Bit Period,14 x Bit Period,15 x Bit Period" endif group.long 0x4C++0x3 line.long 0x0 "US1_IF,USART1 IrDA Filter Register" hexmask.long.byte 0x0 0.--7. 1. " IRDA_FILTER ,IrDA Filter" tree "PDC_USART1 (Peripheral DMA Controller for USART 1)" base ad:0xFFFB4000 width 13. group.long 0x100++0x27 line.long 0x00 "USART1_RPR,PDC/USART1 Receive Pointer Register" line.long 0x04 "USART1_RCR,PDC/USART1 Receive Counter Register" hexmask.long.word 0x04 00.--15. 1. " RXCTR ,Receive Counter Value" line.long 0x08 "USART1_TPR,PDC/USART1 Transmit Pointer Register" line.long 0x0C "USART1_TCR,PDC/USART1 Transmit Counter Register" hexmask.long.word 0x0c 00.--15. 1. " TXCTR ,Transmit Counter Value" line.long 0x10 "USART1_RNPR,PDC/USART1 Receive Next Pointer Register" line.long 0x14 "USART1_RNCR,PDC/USART1 Receive Next Counter Register" hexmask.long.word 0x14 00.--15. 1. " RXNCR ,Receive Next Counter Value" line.long 0x18 "USART1_TNPR,PDC/USART1 Transmit Next Pointer Register" line.long 0x1C "USART1_TNCR,PDC/USART1 Transmit Next Counter Register" hexmask.long.word 0x1C 00.--15. 1. " TXNCR ,Transmit Next Counter Value" line.long 0x24 "USART1_PTSR,PDC/USART1 Transfer Status Register" setclrfld.long 0x24 08. 0x20 8. 0x20 9. " TXTEN_set/clr ,Transmitter Transfer Enable" "Disabled,Enabled" setclrfld.long 0x24 00. 0x20 0. 0x20 1. " RXTEN_set/clr ,Receiver Transfer Enable" "Disabled,Enabled" width 0xb tree.end tree.end tree.end tree "TC (Timer/Counter)" base ad:0xFFFA0000 width 0x8 wgroup.long 0xc0++0x03 line.long 0x00 "TC_BCR,TC Block Control Register" bitfld.long 0x00 0. " SYNC , Synchro Command" "No effect,Asserted" group.long 0xc4++0x03 line.long 0x00 "TC_BMR,TC Block Mode Register" bitfld.long 0x00 4.--5. " TC2XC2S ,External Clock Signal 2 Selection" "TCLK2,No signal,TIOA0,TIOA1" bitfld.long 0x00 2.--3. " TC1XC1S ,External Clock Signal 1 Selection" "TCLK1,No signal,TIOA0,TIOA2" bitfld.long 0x00 0.--1. " TC0XC0S ,External Clock Signal 0 Selection" "TCLK0,No signal,TIOA1,TIOA2" width 0x9 tree "TC Channel 0" wgroup.long (0x00+(0*0x40))++0x03 line.long 0x00 "TC0_CCR,TC0 Channel Control Register" bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed" bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled" textline " " bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled" if (((data.long(ad:(0xFFFA0000+0x4)))&0x8000)==0x8000) group.long (0x04+(0*0x40))++0x03 line.long 0x00 "TC0_CMR,TC0 Channel Mode Register" bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform" bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto" textline " " bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started" bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2" textline " " bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both" bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled" textline " " bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped" bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2" textline " " bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling" bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2" else group.long (0x04+(0*0x40))++0x03 line.long 0x00 "TC0_CMR,TC0 Channel Mode Register" bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both" bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both" textline " " bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform" bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started" textline " " bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA" bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both" textline " " bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "Not disabled,Disabled" bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped" textline " " bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2" bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling" textline " " bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2" endif rgroup.long (0x10+(0*0x40))++0x03 line.long 0x00 "TC0_CV,TC0 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value" if (((data.long(ad:(0xFFFA0000+0x4)))&0x8000)==0x8000) group.long (0x14+(0*0x40))++0x7 line.long 0x00 "TC0_RA,TC0 Register A" hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value" line.long 0x04 "TC0_RB,TC0 Register B" hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value" else rgroup.long (0x14+(0*0x40))++0x07 line.long 0x00 "TC0_RA,TC0 Register A" hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value" line.long 0x04 "TC0_RB,TC0 Register B" hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value" endif group.long (0x1C+(0*0x40))++0x03 line.long 0x00 "TC0_RC,TC0 Register C" hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value" hgroup.long (0x20+(0*0x40))++0x03 hide.long 0x00 "TC0_SR,TC0 Status Register" in group.long (0x2C+(0*0x40))++0x03 line.long 0x00 "TC0_IMR,TC0 Interrupt Mask Register" setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled" tree.end width 0xB width 0x9 tree "TC Channel 1" wgroup.long (0x00+(1*0x40))++0x03 line.long 0x00 "TC1_CCR,TC1 Channel Control Register" bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed" bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled" textline " " bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled" if (((data.long(ad:(0xFFFA0040+0x4)))&0x8000)==0x8000) group.long (0x04+(1*0x40))++0x03 line.long 0x00 "TC1_CMR,TC1 Channel Mode Register" bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform" bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto" textline " " bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started" bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2" textline " " bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both" bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled" textline " " bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped" bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2" textline " " bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling" bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2" else group.long (0x04+(1*0x40))++0x03 line.long 0x00 "TC1_CMR,TC1 Channel Mode Register" bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both" bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both" textline " " bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform" bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started" textline " " bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA" bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both" textline " " bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "Not disabled,Disabled" bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped" textline " " bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2" bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling" textline " " bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2" endif rgroup.long (0x10+(1*0x40))++0x03 line.long 0x00 "TC1_CV,TC1 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value" if (((data.long(ad:(0xFFFA0040+0x4)))&0x8000)==0x8000) group.long (0x14+(1*0x40))++0x7 line.long 0x00 "TC1_RA,TC1 Register A" hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value" line.long 0x04 "TC1_RB,TC1 Register B" hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value" else rgroup.long (0x14+(1*0x40))++0x07 line.long 0x00 "TC1_RA,TC1 Register A" hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value" line.long 0x04 "TC1_RB,TC1 Register B" hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value" endif group.long (0x1C+(1*0x40))++0x03 line.long 0x00 "TC1_RC,TC1 Register C" hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value" hgroup.long (0x20+(1*0x40))++0x03 hide.long 0x00 "TC1_SR,TC1 Status Register" in group.long (0x2C+(1*0x40))++0x03 line.long 0x00 "TC1_IMR,TC1 Interrupt Mask Register" setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled" tree.end width 0xB width 0x9 tree "TC Channel 2" wgroup.long (0x00+(2*0x40))++0x03 line.long 0x00 "TC2_CCR,TC2 Channel Control Register" bitfld.long 0x00 2. " SWTRG ,Software Trigger Command" "No effect,Performed" bitfld.long 0x00 1. " CLKDIS ,Counter Clock Disable Command" "No effect,Disabled" textline " " bitfld.long 0x00 0. " CLKEN ,Counter Clock Enable Command" "No effect,Enabled" if (((data.long(ad:(0xFFFA0080+0x4)))&0x8000)==0x8000) group.long (0x04+(2*0x40))++0x03 line.long 0x00 "TC2_CMR,TC2 Channel Mode Register" bitfld.long 0x00 30.--31. " BSWTRG ,Software Trigger Effect on TIOB" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 28.--29. " BEEVT ,External Event Effect on TIOB" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform" bitfld.long 0x00 26.--27. " BCPC ,RC Compare Effect on TIOB" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 24.--25. " BCPB ,RB Compare Effect on TIOB" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 22.--23. " ASWTRG ,Software Trigger Effect on TIOA" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 20.--21. " AEEVT ,External Event Effect on TIOA" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 18.--19. " ACPC ,RC Compare Effect on TIOA" "No effect,Set,Cleared,Toggled" textline " " bitfld.long 0x00 16.--17. " ACPA ,RA Compare Effect on TIOA" "No effect,Set,Cleared,Toggled" bitfld.long 0x00 13.--14. " WAVSEL ,Waveform Selection" "UP/non-auto,UPDOWN/non-auto,UP/auto,UPDOWN/auto" textline " " bitfld.long 0x00 12. " ENETRG ,External Event Trigger Enable" "No effect,Reset/started" bitfld.long 0x00 10.--11. " EEVT ,External Event Selection" "TIOB,XC0,XC1,XC2" textline " " bitfld.long 0x00 8.--9. " EEVTEDG ,External Event Edge Selection" "No edge,Rising,Falling,Both" bitfld.long 0x00 7. " CPCDIS ,Counter Clock Disable with RC Compare" "Not disabled,Disabled" textline " " bitfld.long 0x00 6. " CPCSTOP ,Counter Clock Stopped With RC Compare" "Not stopped,Stopped" bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2" textline " " bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling" bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2" else group.long (0x04+(2*0x40))++0x03 line.long 0x00 "TC2_CMR,TC2 Channel Mode Register" bitfld.long 0x00 18.--19. " LDRB ,RB Loading Selection" "No edge,Rising,Falling,Both" bitfld.long 0x00 16.--17. " LDRA ,RA Loading Selection" "No edge,Rising,Falling,Both" textline " " bitfld.long 0x00 15. " WAVE ,Waveform Mode Enable" "Capture,Waveform" bitfld.long 0x00 14. " CPCTRG ,RC Compare Trigger Enable" "No effect,Reset/started" textline " " bitfld.long 0x00 10. " ABETRG ,External Trigger Selection" "TIOB,TIOA" bitfld.long 0x00 8.--9. " ETRGEDG ,External Trigger Edge Selection" "No edge,Rising,Falling,Both" textline " " bitfld.long 0x00 7. " LDBDIS ,Counter Clock Disable With RB Loading" "Not disabled,Disabled" bitfld.long 0x00 6. " LDBSTOP ,Counter Clock Stop With RB Loading" "Not stopped,Stopped" textline " " bitfld.long 0x00 4.--5. " BURST ,Burst Signal Selection" "Not gated,XC0,XC1,XC2" bitfld.long 0x00 3. " CLKI ,Clock Invertion" "Rising,Falling" textline " " bitfld.long 0x00 0.--2. " TCCLKS ,Clock Selection" "CLOCK1,CLOCK2,CLOCK3,CLOCK4,CLOCK5,XC0,XC1,XC2" endif rgroup.long (0x10+(2*0x40))++0x03 line.long 0x00 "TC2_CV,TC2 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Counter Value" if (((data.long(ad:(0xFFFA0080+0x4)))&0x8000)==0x8000) group.long (0x14+(2*0x40))++0x7 line.long 0x00 "TC2_RA,TC2 Register A" hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value" line.long 0x04 "TC2_RB,TC2 Register B" hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value" else rgroup.long (0x14+(2*0x40))++0x07 line.long 0x00 "TC2_RA,TC2 Register A" hexmask.long.word 0x00 0.--15. 1. " RA ,Register A Value" line.long 0x04 "TC2_RB,TC2 Register B" hexmask.long.word 0x04 0.--15. 1. " RB ,Register B Value" endif group.long (0x1C+(2*0x40))++0x03 line.long 0x00 "TC2_RC,TC2 Register C" hexmask.long.word 0x00 0.--15. 1. " RC ,Register C Value" hgroup.long (0x20+(2*0x40))++0x03 hide.long 0x00 "TC2_SR,TC2 Status Register" in group.long (0x2C+(2*0x40))++0x03 line.long 0x00 "TC2_IMR,TC2 Interrupt Mask Register" setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS_set/clr ,External Trigger" "Disabled,Enabled" setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS_set/clr ,RB Loading" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS_set/clr ,RA Loading" "Disabled,Enabled" setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS_set/clr ,RC Compare" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS_set/clr ,RB Compare" "Disabled,Enabled" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS_set/clr ,RA Compare" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS_set/clr ,Load Overrun" "Disabled,Enabled" setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS_set/clr ,Counter Overflow" "Disabled,Enabled" tree.end width 0xB tree.end tree "UDP (USB Device Port)" base ad:0xFFFA4000 width 0xe rgroup.long 0x00++0x03 line.long 0x00 "UDP_FRM_NUM,UDP Frame Number Register" bitfld.long 0x00 17. " FRM_OK ,Frame OK" "-,OK" bitfld.long 0x00 16. " FRM_ERR ,Frame Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--10. 1. " FRM_NUM ,Frame Number" group.long 0x04++0x07 line.long 0x00 "UDP_GLB_STAT,UDP Global State Register" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 4. " RMWUPE ,Remote Wake Up Enable" "Disabled,Enabled" bitfld.long 0x00 3. " RSMINPR ,Resume to the Host Send Status" "No effect,Sent" textline " " bitfld.long 0x00 2. " ESR ,Send Resume Enable" "Disabled,Enabled" endif bitfld.long 0x00 0. " FADDEN ,Function Address Enable" "Not addressed,Addressed" textline " " sif (cpu()=="AT91SAM7X512"||cpu()=="AT91SAM7X256"||cpu()=="AT91SAM7X128"||cpu()=="AT91SAM7XC512"||cpu()=="AT91SAM7XC256"||cpu()=="AT91SAM7XC128"||cpuis("AT91CAP7*")) bitfld.long 0x00 1. " CONFG ,Configure" "Not configured,Configured" endif line.long 0x04 "UDP_FADDR,UDP Function Address Register" bitfld.long 0x04 8. " FEN ,Function Enable" "Disabled,Enabled" hexmask.long.byte 0x04 0.--6. 1. " FADD[6:0] ,Function Address Value" group.long 0x18++0x03 line.long 0x00 "UDP_IMR,UDP Interrupt Mask Register" setclrfld.long 0x00 13. -0x08 13. -0x04 13. " WAKEUP_set/clr ,USB Bus Wakeup Interrupt" "Disabled,Enabled" setclrfld.long 0x00 11. -0x08 11. -0x04 11. " SOFINT_set/clr ,Frame Start Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. -0x08 8. -0x04 8. " RXSUSP_set/clr ,UDP Suspend Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EP5INT_set/clr ,Endpoint 5 Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EP4INT_set/clr ,Endpoint 4 Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 3. -0x08 3. -0x04 3. " EP3INT_set/clr ,Endpoint 3 Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. -0x08 2. -0x04 2. " EP2INT_set/clr ,Endpoint 2 Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x00 1. -0x08 1. -0x04 1. " EP1INT_set/clr ,Endpoint 1 Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EP0INT_set/clr ,Endpoint 0 Interrupt Mask" "Disabled,Enabled" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) setclrfld.long 0x00 10. -0x08 10. -0x04 10. " EXTRSM_set/clr ,External Resume Interrupt Mask" "Disabled,Enabled" endif sif (cpu()=="AT91SAM7X512"||cpu()=="AT91SAM7X256"||cpu()=="AT91SAM7X128"||cpu()=="AT91SAM7XC512"||cpu()=="AT91SAM7XC256"||cpu()=="AT91SAM7XC128"||cpuis("AT91CAP7*")) setclrfld.long 0x00 9. -0x08 9. -0x04 9. " RXRSM_set/clr ,UDP Resume Interrupt Mask" "Disabled,Enabled" endif width 9. rgroup.long 0x1C++0x03 line.long 0x00 "UDP_ISR,UDP Interrupt Status Register" bitfld.long 0x00 13. " WAKEUP ,UDP Resume Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 12. " ENDBUSRES ,End of BUS Reset Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " SOFINT ,Start Of Frame Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " RXRSM ,UDP Resume Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " RXSUSP ,UDP Suspend Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " EP5INT ,Endpoint 5 Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " EP4INT ,Endpoint 4 Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 3. " EP3INT ,Endpoint 3 Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " EP2INT ,Endpoint 2 Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " EP1INT ,Endpoint 1 Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " EP0INT ,Endpoint 0 Interrupt Status" "Not occurred,Occurred" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 10. " EXTRSM ,External Resume Interrupt Status" "Not occurred,Occurred" endif width 0xe wgroup.long 0x20++0x03 line.long 0x00 "UDP_ICR,UDP Interrupt Clear Register" bitfld.long 0x00 13. " WAKEUP ,Wakeup Interrupt Clear" "No effect,Cleared" bitfld.long 0x00 12. " ENDBUSRES ,BUS End Reset Interrupt Clear" "No effect,Cleared" textline " " bitfld.long 0x00 11. " SOFINT ,Frame Start Interrupt Clear" "No effect,Cleared" bitfld.long 0x00 9. " RXRSM ,UDP Resume Interrupt Clear" "No effect,Cleared" textline " " bitfld.long 0x00 8. " RXSUSP ,UDP Suspend Interrupt Clear" "No effect,Cleared" sif (cpu()!="AT91SAM7X512"&&cpu()!="AT91SAM7X256"&&cpu()!="AT91SAM7X128"&&cpu()!="AT91SAM7XC512"&&cpu()!="AT91SAM7XC256"&&cpu()!="AT91SAM7XC128"&&!cpuis("AT91CAP7*")) bitfld.long 0x00 10. " EXTRSM ,External Resume Interrupt Clear" "No effect,Cleared" endif group.long 0x28++0x03 line.long 0x00 "UDP_RST_EP,UDP Reset Endpoint Register" bitfld.long 0x00 5. " EP5 ,Endpoint 5 Reset" "No reset,Reset" bitfld.long 0x00 4. " EP4 ,Endpoint 4 Reset" "No reset,Reset" textline " " bitfld.long 0x00 3. " EP3 ,Endpoint 3 Reset" "No reset,Reset" bitfld.long 0x00 2. " EP2 ,Endpoint 2 Reset" "No reset,Reset" textline " " bitfld.long 0x00 1. " EP1 ,Endpoint 1 Reset" "No reset,Reset" bitfld.long 0x00 0. " EP0 ,Endpoint 0 Reset" "No reset,Reset" width 0xA tree "UDP Endpoint Control and Status Registers" if ((((data.long(ad:(0xFFFA4000+0x30+0x0)))&0x700)==0x100)||(((data.long(ad:(0xFFFA4000+0x30+0x0)))&0x700)==0x500)) group.long (0x30+0x0)++0x3 line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " ISOERROR ,Isochronous Error" "No error,Error" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x0)))&0x700)==0x400) group.long (0x30+0x0)++0x3 line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x0)))&0x700)==0x000) group.long (0x30+0x0)++0x3 line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 7. " DIR ,Transfer Direction" "Out,In" bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" textline " " bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" else group.long (0x30+0x0)++0x3 line.long 0x0 "UDP_CSR0,UDP Endpoint 0 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" endif if ((((data.long(ad:(0xFFFA4000+0x30+0x4)))&0x700)==0x100)||(((data.long(ad:(0xFFFA4000+0x30+0x4)))&0x700)==0x500)) group.long (0x30+0x4)++0x3 line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " ISOERROR ,Isochronous Error" "No error,Error" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x4)))&0x700)==0x400) group.long (0x30+0x4)++0x3 line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x4)))&0x700)==0x000) group.long (0x30+0x4)++0x3 line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 7. " DIR ,Transfer Direction" "Out,In" bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" textline " " bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" else group.long (0x30+0x4)++0x3 line.long 0x0 "UDP_CSR1,UDP Endpoint 1 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" endif if ((((data.long(ad:(0xFFFA4000+0x30+0x8)))&0x700)==0x100)||(((data.long(ad:(0xFFFA4000+0x30+0x8)))&0x700)==0x500)) group.long (0x30+0x8)++0x3 line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " ISOERROR ,Isochronous Error" "No error,Error" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x8)))&0x700)==0x400) group.long (0x30+0x8)++0x3 line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x8)))&0x700)==0x000) group.long (0x30+0x8)++0x3 line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 7. " DIR ,Transfer Direction" "Out,In" bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" textline " " bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" else group.long (0x30+0x8)++0x3 line.long 0x0 "UDP_CSR2,UDP Endpoint 2 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" endif if ((((data.long(ad:(0xFFFA4000+0x30+0xC)))&0x700)==0x100)||(((data.long(ad:(0xFFFA4000+0x30+0xC)))&0x700)==0x500)) group.long (0x30+0xC)++0x3 line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " ISOERROR ,Isochronous Error" "No error,Error" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0xC)))&0x700)==0x400) group.long (0x30+0xC)++0x3 line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0xC)))&0x700)==0x000) group.long (0x30+0xC)++0x3 line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 7. " DIR ,Transfer Direction" "Out,In" bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" textline " " bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" else group.long (0x30+0xC)++0x3 line.long 0x0 "UDP_CSR3,UDP Endpoint 3 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" endif if ((((data.long(ad:(0xFFFA4000+0x30+0x10)))&0x700)==0x100)||(((data.long(ad:(0xFFFA4000+0x30+0x10)))&0x700)==0x500)) group.long (0x30+0x10)++0x3 line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " ISOERROR ,Isochronous Error" "No error,Error" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x10)))&0x700)==0x400) group.long (0x30+0x10)++0x3 line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x10)))&0x700)==0x000) group.long (0x30+0x10)++0x3 line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 7. " DIR ,Transfer Direction" "Out,In" bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" textline " " bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" else group.long (0x30+0x10)++0x3 line.long 0x0 "UDP_CSR4,UDP Endpoint 4 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" endif if ((((data.long(ad:(0xFFFA4000+0x30+0x14)))&0x700)==0x100)||(((data.long(ad:(0xFFFA4000+0x30+0x14)))&0x700)==0x500)) group.long (0x30+0x14)++0x3 line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " ISOERROR ,Isochronous Error" "No error,Error" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x14)))&0x700)==0x400) group.long (0x30+0x14)++0x3 line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" elif (((data.long(ad:(0xFFFA4000+0x30+0x14)))&0x700)==0x000) group.long (0x30+0x14)++0x3 line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 7. " DIR ,Transfer Direction" "Out,In" bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" textline " " bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" textline " " bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" else group.long (0x30+0x14)++0x3 line.long 0x0 "UDP_CSR5,UDP Endpoint 5 Control and Status Register" hexmask.long.word 0x0 16.--26. 1. " RXBYTECNT[10:0] ,FIFO Available Bytes Number" bitfld.long 0x0 15. " EPEDS ,Endpoint Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " DTGLE ,Data Toggle" "DATA0,DATA1" bitfld.long 0x0 8.--10. " EPTYPE[2:0] ,Endpoint Type" "Control,Isochronous out,Bulk out,Interrupt out,Reserved,Isochronous in,Bulk in,Interrupt in" textline " " bitfld.long 0x0 6. " RX_DATA_BK1 ,Bank 1 Data Receive" "Not received,Received" bitfld.long 0x0 5. " FORCESTALL ,Force Stall" "No effect,Forced" textline " " bitfld.long 0x0 4. " TXPKTRDY ,Transmit Packet Ready" "Ready,Busy" bitfld.long 0x0 3. " STALLSENT ,Stall Sent" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x0 2. " RXSETUP ,Setup Data Packet Receive" "Not received,Received" bitfld.long 0x0 1. " RX_DATA_BK0 ,Bank 0 Data Receive" "Not received,Received" textline " " bitfld.long 0x0 0. " TXCOMP ,IN Packet With Data Previously Written in the DPR Generation" "Not acknowledged,Acknowledged" endif tree.end tree "UDP FIFO Data Registers" hgroup.long 0x50++0x03 hide.long 0x00 "UDP_FDR0,UDP FIFO Data Register 0" in hgroup.long 0x54++0x03 hide.long 0x00 "UDP_FDR1,UDP FIFO Data Register 1" in hgroup.long 0x58++0x03 hide.long 0x00 "UDP_FDR2,UDP FIFO Data Register 2" in hgroup.long 0x5C++0x03 hide.long 0x00 "UDP_FDR3,UDP FIFO Data Register 3" in hgroup.long 0x60++0x03 hide.long 0x00 "UDP_FDR4,UDP FIFO Data Register 4" in hgroup.long 0x64++0x03 hide.long 0x00 "UDP_FDR5,UDP FIFO Data Register 5" in wgroup 0x0++0x0 tree.end textline " " group.long 0x74++0x03 line.long 0x00 "UDP_TXVC,UDP Transceiver Control Register" bitfld.long 0x00 8. " TXVDIS ,Transceiver Disable" "No,Yes" width 0xB tree.end tree "ADC (Analog-to-Digital Converter)" base ad:0xFFFA8000 wgroup.long 0x00++0x03 line.long 0x00 "ADC_CR,ADC Control Register" bitfld.long 0x00 1. " START ,Conversion Start" "No effect,Started" bitfld.long 0x00 0. " SWRST ,Software Reset" "No effect,Reset" group.long 0x04++0x03 line.long 0x00 "ADC_MR,ADC Mode Register" bitfld.long 0x00 24.--27. " SHTIM ,Sample and Hold Time" "1/clock,2/clock,3/clock,4/clock,5/clock,6/clock,7/clock,8/clock,9/clock,10/clock,11/clock,12/clock,13/clock,14/clock,15/clock,16/clock" bitfld.long 0x00 16.--20. " STARTUP ,Start Up Time" "8/clock,16/clock,24/clock,32/clock,40/clock,48/clock,56/clock,64/clock,72/clock,80/clock,88/clock,96/clock,104/clock,112/clock,120/clock,128/clock,136/clock,144/clock,152/clock,160/clock,168/clock,176/clock,184/clock,192/clock,200/clock,208/clock,216/clock,224/clock,232/clock,240/clock,248/clock,256/clock" textline " " bitfld.long 0x00 8.--13. " PRESCAL ,Prescaler Rate Selection" "MCK/2,MCK/4,MCK/6,MCK/8,MCK/10,MCK/12,MCK/14,MCK/16,MCK/18,MCK/20,MCK/22,MCK/24,MCK/26,MCK/28,MCK/30,MCK/32,MCK/34,MCK/36,MCK/38,MCK/40,MCK/42,MCK/44,MCK/46,MCK/48,MCK/50,MCK/52,MCK/54,MCK/56,MCK/58,MCK/60,MCK/62,MCK/64,MCK/66,MCK/68,MCK/70,MCK/72,MCK/74,MCK/76,MCK/78,MCK/80,MCK/82,MCK/84,MCK/86,MCK/88,MCK/90,MCK/92,MCK/94,MCK/96,MCK/98,MCK/100,MCK/102,MCK/104,MCK/106,MCK/108,MCK/110,MCK/112,MCK/114,MCK/116,MCK/118,MCK/120,MCK/122,MCK/124,MCK/126,MCK/128" bitfld.long 0x00 5. " SLEEP ,Sleep Mode" "Normal,Sleep" textline " " bitfld.long 0x00 4. " LOWRES ,Resolution" "10-bit,8-bit" sif (cpuis("AT91CAP7*")) bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,External,?..." elif (cpuis("UC3*")) bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "TIOA0,TIOA1,TIOA2,TIOA3,TIOA4,TIOA5,External,?..." else bitfld.long 0x00 1.--3. " TRGSEL ,Trigger Selection" "Channel 0,Channel 1,Channel 2,Reserved,Reserved,Reserved,External,?..." endif textline " " bitfld.long 0x00 0. " TRGEN ,Trigger Enable" "Disabled,Enabled" group.long 0x10++0x0b line.long 0x08 "ADC_CHSR,ADC Channel Status Register" setclrfld.long 0x08 7. 0x00 7. 0x04 7. " CH7_set/clr ,Channel 7 Status" "Disabled,Enabled" setclrfld.long 0x08 6. 0x00 6. 0x04 6. " CH6_set/clr ,Channel 6 Status" "Disabled,Enabled" textline " " setclrfld.long 0x08 5. 0x00 5. 0x04 5. " CH5_set/clr ,Channel 5 Status" "Disabled,Enabled" setclrfld.long 0x08 4. 0x00 4. 0x04 4. " CH4_set/clr ,Channel 4 Status" "Disabled,Enabled" textline " " setclrfld.long 0x08 3. 0x00 3. 0x04 3. " CH3_set/clr ,Channel 3 Status" "Disabled,Enabled" setclrfld.long 0x08 2. 0x00 2. 0x04 2. " CH2_set/clr ,Channel 2 Status" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x00 1. 0x04 1. " CH1_set/clr ,Channel 1 Status" "Disabled,Enabled" setclrfld.long 0x08 0. 0x00 0. 0x04 0. " CH0_set/clr ,Channel 0 Status" "Disabled,Enabled" hgroup.long 0x1c++0x3 hide.long 0x00 "ADC_SR,ADC Status Register" in rgroup.long 0x20++0x3 line.long 0x0 "ADC_LCDR,ADC Last Converted Data Register" hexmask.long.word 0x0 0.--9. 1. " LDATA ,Last Data Converted" group.long 0x24++0x0b line.long 0x08 "ADC_IMR,ADC Interrupt Mask Register" setclrfld.long 0x08 19. 0x00 19. 0x04 19. " RXBUFF_set/clr ,Receive Buffer Full Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x08 18. 0x00 18. 0x04 18. " ENDRX_set/clr ,Receive Buffer End Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x08 17. 0x00 17. 0x04 17. " GOVRE_set/clr ,General Overrun Error Interrupt Mask" "Disabled,Enabled" setclrfld.long 0x08 16. 0x00 16. 0x04 16. " DRDY_set/clr ,Data Ready Interrupt Mask" "Disabled,Enabled" textline " " setclrfld.long 0x08 15. 0x00 15. 0x04 15. " OVRE7_set/clr ,Overrun Error Interrupt Mask 7" "Disabled,Enabled" setclrfld.long 0x08 14. 0x00 14. 0x04 14. " OVRE6_set/clr ,Overrun Error Interrupt Mask 6" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x00 13. 0x04 13. " OVRE5_set/clr ,Overrun Error Interrupt Mask 5" "Disabled,Enabled" setclrfld.long 0x08 12. 0x00 12. 0x04 12. " OVRE4_set/clr ,Overrun Error Interrupt Mask 4" "Disabled,Enabled" textline " " setclrfld.long 0x08 11. 0x00 11. 0x04 11. " OVRE3_set/clr ,Overrun Error Interrupt Mask 3" "Disabled,Enabled" setclrfld.long 0x08 10. 0x00 10. 0x04 10. " OVRE2_set/clr ,Overrun Error Interrupt Mask 2" "Disabled,Enabled" textline " " setclrfld.long 0x08 9. 0x00 9. 0x04 9. " OVRE1_set/clr ,Overrun Error Interrupt Mask 1" "Disabled,Enabled" setclrfld.long 0x08 8. 0x00 8. 0x04 8. " OVRE0_set/clr ,Overrun Error Interrupt Mask 0" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x00 7. 0x04 7. " EOC7_set/clr ,Conversion End Interrupt Mask 7" "Disabled,Enabled" setclrfld.long 0x08 6. 0x00 6. 0x04 6. " EOC6_set/clr ,Conversion End Interrupt Mask 6" "Disabled,Enabled" textline " " setclrfld.long 0x08 5. 0x00 5. 0x04 5. " EOC5_set/clr ,Conversion End Interrupt Mask 5" "Disabled,Enabled" setclrfld.long 0x08 4. 0x00 4. 0x04 4. " EOC4_set/clr ,Conversion End Interrupt Mask 4" "Disabled,Enabled" textline " " setclrfld.long 0x08 3. 0x00 3. 0x04 3. " EOC3_set/clr ,Conversion End Interrupt Mask 3" "Disabled,Enabled" setclrfld.long 0x08 2. 0x00 2. 0x04 2. " EOC2_set/clr ,Conversion End Interrupt Mask 2" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x00 1. 0x04 1. " EOC1_set/clr ,Conversion End Interrupt Mask 1" "Disabled,Enabled" setclrfld.long 0x08 0. 0x00 0. 0x04 0. " EOC0_set/clr ,Conversion End Interrupt Mask 0" "Disabled,Enabled" rgroup.long 0x30++0x1f line.long 0x00 "ADC_CDR0,ADC Channel Data Register 0" hexmask.long.word 0x00 0.--9. 1. " DATA ,Converted Data" line.long 0x04 "ADC_CDR1,ADC Channel Data Register 1" hexmask.long.word 0x04 0.--9. 1. " DATA ,Converted Data" line.long 0x08 "ADC_CDR2,ADC Channel Data Register 2" hexmask.long.word 0x08 0.--9. 1. " DATA ,Converted Data" line.long 0x0c "ADC_CDR3,ADC Channel Data Register 3" hexmask.long.word 0x0c 0.--9. 1. " DATA ,Converted Data" line.long 0x10 "ADC_CDR4,ADC Channel Data Register 4" hexmask.long.word 0x10 0.--9. 1. " DATA ,Converted Data" line.long 0x14 "ADC_CDR5,ADC Channel Data Register 5" hexmask.long.word 0x14 0.--9. 1. " DATA ,Converted Data" line.long 0x18 "ADC_CDR6,ADC Channel Data Register 6" hexmask.long.word 0x18 0.--9. 1. " DATA ,Converted Data" line.long 0x1c "ADC_CDR7,ADC Channel Data Register 7" hexmask.long.word 0x1c 0.--9. 1. " DATA ,Converted Data" sif (cpuis("UC3*")) rgroup.long 0xFC++0x03 line.long 0x00 "VERSION,Version Register" hexmask.long.word 0x00 0.--11. 1. " VERSION ,Version Number" endif tree "PDC_ADC (Peripheral DMA Controller for ADC)" base ad:0xFFFA8000 width 10. group.long 0x100++0x27 line.long 0x00 "ADC_RPR,PDC/ADC Receive Pointer Register" line.long 0x04 "ADC_RCR,PDC/ADC Receive Counter Register" hexmask.long.word 0x04 00.--15. 1. " RXCTR ,Receive Counter Value" line.long 0x08 "ADC_TPR,PDC/ADC Transmit Pointer Register" line.long 0x0C "ADC_TCR,PDC/ADC Transmit Counter Register" hexmask.long.word 0x0c 00.--15. 1. " TXCTR ,Transmit Counter Value" line.long 0x10 "ADC_RNPR,PDC/ADC Receive Next Pointer Register" line.long 0x14 "ADC_RNCR,PDC/ADC Receive Next Counter Register" hexmask.long.word 0x14 00.--15. 1. " RXNCR ,Receive Next Counter Value" line.long 0x18 "ADC_TNPR,PDC/ADC Transmit Next Pointer Register" line.long 0x1C "ADC_TNCR,PDC/ADC Transmit Next Counter Register" hexmask.long.word 0x1C 00.--15. 1. " TXNCR ,Transmit Next Counter Value" line.long 0x24 "ADC_PTSR,PDC/ADC Transfer Status Register" setclrfld.long 0x24 08. 0x20 8. 0x20 9. " TXTEN_set/clr ,Transmitter Transfer Enable" "Disabled,Enabled" setclrfld.long 0x24 00. 0x20 0. 0x20 1. " RXTEN_set/clr ,Receiver Transfer Enable" "Disabled,Enabled" width 0xb tree.end tree.end textline ""